diff --git a/qcom/video/Kbuild b/qcom/video/Kbuild new file mode 100644 index 00000000..e1ab6d69 --- /dev/null +++ b/qcom/video/Kbuild @@ -0,0 +1,31 @@ + +ifeq ($(CONFIG_ARCH_WAIPIO), y) +dtbo-y += waipio-vidc.dtbo +endif + +ifeq ($(CONFIG_ARCH_KALAMA), y) +dtbo-y += kalama-vidc.dtbo +dtbo-y += kalama-vidc-v2.dtbo +endif + +ifeq ($(CONFIG_ARCH_PINEAPPLE), y) +dtbo-y += pineapple-vidc.dtbo +dtbo-y += pineapple-vidc-v2.dtbo +endif + +ifeq ($(CONFIG_ARCH_SUN), y) +dtbo-y += sun-vidc.dtbo +dtbo-y += sun-vidc-v2.dtbo +endif + +ifeq ($(CONFIG_ARCH_TUNA), y) +dtbo-y += tuna-vidc.dtbo +endif + +ifeq ($(CONFIG_ARCH_KERA), y) +dtbo-y += kera-vidc.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/qcom/video/Makefile b/qcom/video/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/qcom/video/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/qcom/video/kalama-vidc-v2.dts b/qcom/video/kalama-vidc-v2.dts new file mode 100644 index 00000000..57c66469 --- /dev/null +++ b/qcom/video/kalama-vidc-v2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "kalama-vidc-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x20000>, <536 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/kalama-vidc-v2.dtsi b/qcom/video/kalama-vidc-v2.dtsi new file mode 100644 index 00000000..671e709b --- /dev/null +++ b/qcom/video/kalama-vidc-v2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kalama-vidc.dtsi" + +/* KalamaV2-specific changes */ +&msm_vidc { + compatible = "qcom,sm8550-vidc-v2"; +}; + diff --git a/qcom/video/kalama-vidc.dts b/qcom/video/kalama-vidc.dts new file mode 100644 index 00000000..2bf746c3 --- /dev/null +++ b/qcom/video/kalama-vidc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "kalama-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kalama"; + compatible = "qcom,kalama"; + qcom,msm-id = <519 0x10000>, <536 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/kalama-vidc.dtsi b/qcom/video/kalama-vidc.dtsi new file mode 100644 index 00000000..b7c91d75 --- /dev/null +++ b/qcom/video/kalama-vidc.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,sm8550-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi0", + "core_clk", + "vcodec_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "video_axi_reset"; + + /* MMUs */ + non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x1947 0x0000>; + qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; + + non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x1940 0x0000>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; + + secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x1944 0x0000>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x1941 0x0004>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x1943 0x0000>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/video/kera-vidc.dts b/qcom/video/kera-vidc.dts new file mode 100644 index 00000000..103d5fd8 --- /dev/null +++ b/qcom/video/kera-vidc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "kera-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kera"; + compatible = "qcom,kera"; + qcom,msm-id = <659 0x10000>, <686 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/kera-vidc.dtsi b/qcom/video/kera-vidc.dtsi new file mode 100644 index 00000000..288de4d2 --- /dev/null +++ b/qcom/video/kera-vidc.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,kera-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Power Domains */ + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>; + power-domain-names = "iris-ctl", "vcodec"; + + /* Clocks */ + clocks = + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi0_clk", + "video_cc_mvs0c_clk", + "video_cc_mvs0_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_MVP &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_CLK_ARES>; + reset-names = + "video_axi_reset", + "video_xo_reset", + "video_mvs0c_reset", + "video_mvs0_reset"; + + /* MMUs */ + iommu_region_partition: iommu_region_partition { + /* These IOVA regions are unique per context bank */ + iommu-addresses = <&non_secure_pixel_cb 0x0 0x00100000>, + <&non_secure_pixel_cb 0xe0000000 0x20000000>, + <&non_secure_cb 0x0 0x25800000>, + <&non_secure_cb 0xe0000000 0x20000000>, + <&secure_non_pixel_cb 0x0 0x01000000>, + <&secure_non_pixel_cb 0x25800000 0xda800000>, + <&secure_bitstream_cb 0x0 0x00500000>, + <&secure_bitstream_cb 0xe0000000 0x20000000>, + <&secure_pixel_cb 0x0 0x00500000>, + <&secure_pixel_cb 0xe0000000 0x20000000>; + }; + + non_secure_pixel_cb: non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x1947 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + /* log2 of desired alignment (1MB) - log2 of PAGE_SIZE; (8 = 20 - 12) */ + qcom,iova-max-align-shift = <8>; + dma-coherent; + }; + + non_secure_cb: non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x1940 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + dma-coherent; + }; + + secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x1944 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb: secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x1941 0x0004>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x1943 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/video/pineapple-vidc-v2.dts b/qcom/video/pineapple-vidc-v2.dts new file mode 100644 index 00000000..ca37f254 --- /dev/null +++ b/qcom/video/pineapple-vidc-v2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "pineapple-vidc-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x20000>, <577 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/pineapple-vidc-v2.dtsi b/qcom/video/pineapple-vidc-v2.dtsi new file mode 100644 index 00000000..529d8243 --- /dev/null +++ b/qcom/video/pineapple-vidc-v2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-vidc.dtsi" + +/* Pineapple V2-specific changes */ +&msm_vidc { + compatible = "qcom,sm8650-vidc-v2"; +}; + diff --git a/qcom/video/pineapple-vidc.dts b/qcom/video/pineapple-vidc.dts new file mode 100644 index 00000000..d863acdc --- /dev/null +++ b/qcom/video/pineapple-vidc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "pineapple-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>, <577 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/pineapple-vidc.dtsi b/qcom/video/pineapple-vidc.dtsi new file mode 100644 index 00000000..36e49831 --- /dev/null +++ b/qcom/video/pineapple-vidc.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,sm8650-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clocks = + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi0_clk", + "video_cc_mvs0c_clk", + "video_cc_mvs0_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = + "video_axi_reset", + "video_xo_reset", + "video_mvs0c_reset"; + + /* MMUs */ + non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x1947 0x0000>; + qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + /* log2 of desired alignment (1MB) - log2 of PAGE_SIZE; (8 = 20 - 12) */ + qcom,iova-max-align-shift = <8>; + dma-coherent; + }; + + non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x1940 0x0000>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + dma-coherent; + }; + + secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x1944 0x0000>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x1941 0x0004>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x1943 0x0000>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/video/sun-vidc-v2.dts b/qcom/video/sun-vidc-v2.dts new file mode 100644 index 00000000..d8e521a1 --- /dev/null +++ b/qcom/video/sun-vidc-v2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "sun-vidc-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x20000>, <639 0x20000>, + <0x100026a 0x20000>, + <0x100027f 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/sun-vidc-v2.dtsi b/qcom/video/sun-vidc-v2.dtsi new file mode 100755 index 00000000..c2f4b370 --- /dev/null +++ b/qcom/video/sun-vidc-v2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-vidc.dtsi" + +/* sun V2-specific changes */ +&msm_vidc { + compatible = "qcom,sm8750-vidc-v2"; +}; + diff --git a/qcom/video/sun-vidc.dts b/qcom/video/sun-vidc.dts new file mode 100644 index 00000000..eaefe01a --- /dev/null +++ b/qcom/video/sun-vidc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "sun-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun"; + compatible = "qcom,sun"; + qcom,msm-id = <618 0x10000>, <639 0x10000>, + <0x100026a 0x10000>, + <0x100027f 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/sun-vidc.dtsi b/qcom/video/sun-vidc.dtsi new file mode 100644 index 00000000..51365718 --- /dev/null +++ b/qcom/video/sun-vidc.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,sm8750-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Power Domains */ + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>; + power-domain-names = "iris-ctl", "vcodec"; + + /* Clocks */ + clocks = + <&gcc GCC_VIDEO_AXI1_CLK>, + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi1_clk", + "gcc_video_axi0_clk", + "video_cc_mvs0c_freerun_clk", + "video_cc_mvs0_freerun_clk", + "video_cc_mvs0c_clk", + "video_cc_mvs0_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_MVP &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = + "video_axi1_reset", + "video_axi0_reset", + "video_mvs0c_freerun_reset", + "video_mvs0_freerun_reset"; + + /* MMUs */ + iommu_region_partition: iommu_region_partition { + /* These IOVA regions are unique per context bank */ + iommu-addresses = <&non_secure_pixel_cb 0x0 0x00100000>, + <&non_secure_pixel_cb 0xe0000000 0x20000000>, + <&non_secure_cb 0x0 0x25800000>, + <&non_secure_cb 0xe0000000 0x20000000>, + <&secure_non_pixel_cb 0x0 0x01000000>, + <&secure_non_pixel_cb 0x25800000 0xda800000>, + <&secure_bitstream_cb 0x0 0x00500000>, + <&secure_bitstream_cb 0xe0000000 0x20000000>, + <&secure_pixel_cb 0x0 0x00500000>, + <&secure_pixel_cb 0xe0000000 0x20000000>; + }; + + non_secure_pixel_cb: non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x1947 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + /* log2 of desired alignment (1MB) - log2 of PAGE_SIZE; (8 = 20 - 12) */ + qcom,iova-max-align-shift = <8>; + dma-coherent; + }; + + non_secure_cb: non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x1940 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + dma-coherent; + }; + + secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x1944 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb: secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x1941 0x0004>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x1943 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/video/tuna-vidc.dts b/qcom/video/tuna-vidc.dts new file mode 100644 index 00000000..c96b1be2 --- /dev/null +++ b/qcom/video/tuna-vidc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "tuna-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna"; + compatible = "qcom,tuna"; + qcom,msm-id = <655 0x10000>, <681 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/tuna-vidc.dtsi b/qcom/video/tuna-vidc.dtsi new file mode 100644 index 00000000..eb8e91b6 --- /dev/null +++ b/qcom/video/tuna-vidc.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,tuna-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Power Domains */ + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>; + power-domain-names = "iris-ctl", "vcodec"; + + /* Clocks */ + clocks = + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi0_clk", + "video_cc_mvs0c_clk", + "video_cc_mvs0_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_MVP &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_XO_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_CLK_ARES>; + reset-names = + "video_axi_reset", + "video_xo_reset", + "video_mvs0c_reset", + "video_mvs0_reset"; + + /* MMUs */ + iommu_region_partition: iommu_region_partition { + /* These IOVA regions are unique per context bank */ + iommu-addresses = <&non_secure_pixel_cb 0x0 0x00100000>, + <&non_secure_pixel_cb 0xe0000000 0x20000000>, + <&non_secure_cb 0x0 0x25800000>, + <&non_secure_cb 0xe0000000 0x20000000>, + <&secure_non_pixel_cb 0x0 0x01000000>, + <&secure_non_pixel_cb 0x25800000 0xda800000>, + <&secure_bitstream_cb 0x0 0x00500000>, + <&secure_bitstream_cb 0xe0000000 0x20000000>, + <&secure_pixel_cb 0x0 0x00500000>, + <&secure_pixel_cb 0xe0000000 0x20000000>; + }; + + non_secure_pixel_cb: non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x1947 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + /* log2 of desired alignment (1MB) - log2 of PAGE_SIZE; (8 = 20 - 12) */ + qcom,iova-max-align-shift = <8>; + dma-coherent; + }; + + non_secure_cb: non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x1940 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + dma-coherent; + }; + + secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x1944 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb: secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x1941 0x0004>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + + secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x1943 0x0000>; + memory-region = <&iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,iova-best-fit; + qcom,iova-max-align-shift = <8>; /* 1 MB */ + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/video/waipio-vidc.dts b/qcom/video/waipio-vidc.dts new file mode 100644 index 00000000..63d2b372 --- /dev/null +++ b/qcom/video/waipio-vidc.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "waipio-vidc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. waipio v1 SoC"; + compatible = "qcom,waipio"; + qcom,msm-id = <457 0x10000>, <482 0x10000>, + <457 0x20000>, <482 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/video/waipio-vidc.dtsi b/qcom/video/waipio-vidc.dtsi new file mode 100644 index 00000000..6b8696c8 --- /dev/null +++ b/qcom/video/waipio-vidc.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,sm8450-vidc"; + status = "okay"; + + /* IOMMU Config */ + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x0aa00000 0xF0000>; + interrupts = ; + + /* Supply */ + iris-ctl-supply = <&video_cc_mvs0c_gdsc>; + vcodec-supply = <&video_cc_mvs0_gdsc>; + + /* Clocks */ + clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_videocc VIDEO_CC_MVS0C_CLK>, + <&clock_videocc VIDEO_CC_MVS0_CLK>, + <&clock_videocc VIDEO_CC_MVS0_CLK_SRC>; + clock-names = + "gcc_video_axi0", + "core_clk", + "vcodec_clk", + "video_cc_mvs0_clk_src"; + + /* Bus Interconnects */ + interconnects = + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_VIDEO_P0 &gem_noc SLAVE_LLCC>; + interconnect-names = + "venus-cnoc", + "venus-ddr", + "venus-llcc"; + + /* FW load region */ + memory-region = <&video_mem>; + + /* Clock Resets */ + resets = + <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = + "video_axi_reset", + "video_core_reset"; + + /* MMUs */ + non_secure_pixel_cb { + compatible = "qcom,vidc,cb-ns-pxl"; + iommus = <&apps_smmu 0x2187 0x0400>; + qcom,iommu-dma-addr-pool = <0x00100000 0xdff00000>; + qcom,iommu-faults = "non-fatal", "stall-disable"; + qcom,iommu-pagetable = "LLC"; + dma-coherent; + }; + + non_secure_cb { + compatible = "qcom,vidc,cb-ns"; + iommus = <&apps_smmu 0x2180 0x0400>; + qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>; + qcom,iommu-faults = "non-fatal", "stall-disable"; + qcom,iommu-pagetable = "LLC"; + dma-coherent; + }; + + secure_non_pixel_cb { + compatible = "qcom,vidc,cb-sec-non-pxl"; + iommus = <&apps_smmu 0x2184 0x0400>; + qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>; + qcom,iommu-faults = "non-fatal", "stall-disable"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xB>; /* VMID_CP_NON_PIXEL */ + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,vidc,cb-sec-bitstream"; + iommus = <&apps_smmu 0x2181 0x0404>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,vidc,cb-sec-pxl"; + iommus = <&apps_smmu 0x2183 0x0400>; + qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-pagetable = "LLC"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + qcom,secure-context-bank; + }; + }; +};