samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge "dt-bindings: buses: Add QCOM geni serial bindings for Sun"

Browse Source
This commit is contained in:
qctecmdr
2023-07-14 18:36:28 -07:00
committed by Gerrit - the friendly Code Review server
parent a71a9dcd3a f6a2bfe1ee
commit cc46666579
1 changed files with 15 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
bindings/serial/qcom,serial-geni-qcom.yaml
View File

@@ -23,21 +23,21 @@ properties:
maxItems: 1 maxItems: 1
clock-names: clock-names:
const: se const: se-clk
interconnects: interconnects:
maxItems: 2 maxItems: 3
interconnect-names: interconnect-names:
items: items:
- const: qup-core - const: qup-core
- const: qup-config - const: qup-config
- const: qup-memory
interrupts: interrupts:
minItems: 1 minItems: 1
items: items:
- description: UART core irq - description: UART core irq
- description: Wakeup irq (RX GPIO)
operating-points-v2: true operating-points-v2: true
@@ -68,19 +68,23 @@ unevaluatedProperties: false
examples: examples:
- | - |
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/interconnect/qcom,sc7180.h> #include <dt-bindings/interconnect/qcom,sun.h>
serial@a88000 { qupv3_se0_2uart: qcom,qup_uart@a88000 {
compatible = "qcom,geni-uart"; compatible = "qcom,geni-uart";
reg = <0xa88000 0x7000>; reg = <0xa88000 0x7000>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se"; clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-0 = <&qup_uart0_default>; pinctrl-0 = <&qup_uart0_default>;
pinctrl-names = "default"; pinctrl-names = "default", "sleep";
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, interconnect-names = "qup-core", "qup-config", "qup-memory";
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
interconnect-names = "qup-core", "qup-config"; <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
pinctrl-1 = <&qupv3_se0_2uart_sleep>;
}; };
... ...