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ARM: dts: msm: Add turbo_l4 power level to Sun GPU

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Add supported higher power level to Sun GPU.

Change-Id: Icfbdae6f7b44edea00fbf3374224cb407bd0968d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
This commit is contained in:
Mohammed Mirza Mandayappurath Manzoor
2024-03-05 10:23:28 -08:00
parent 2cc3321179
commit cb1a9008b3
1 changed files with 43 additions and 29 deletions
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72
gpu/sun-gpu-pwrlevels.dtsi
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@@ -4,6 +4,7 @@
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L4 0x802e5ffd
#define ACD_LEVEL_TURBO_L3 0xa02f5ffd
#define ACD_LEVEL_TURBO_L1 0xa8285ffd
#define ACD_LEVEL_NOM_L1 0x88295ffd
@@ -194,13 +195,26 @@
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <12>;
qcom,initial-min-pwrlevel = <12>;
qcom,initial-pwrlevel = <13>;
qcom,initial-min-pwrlevel = <13>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L3 */
/* TURBO_L4 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
};
/* TURBO_L3 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
@@ -212,8 +226,8 @@
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
@@ -225,8 +239,8 @@
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -238,8 +252,8 @@
};
/* NOM */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -251,8 +265,8 @@
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -264,8 +278,8 @@
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -277,8 +291,8 @@
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -290,8 +304,8 @@
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -303,8 +317,8 @@
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -316,8 +330,8 @@
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -329,8 +343,8 @@
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -342,8 +356,8 @@
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -355,8 +369,8 @@
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
@@ -368,8 +382,8 @@
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-pwrlevel@14 {
reg = <14>;
qcom,gpu-freq = <125000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;