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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/qcom,qpnp-power-on.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral
+
+maintainers:
+  - David Collins <quic_collinsd@quicinc.com>
+
+description: >
+  qpnp-power-on devices support the power-on (PON) peripheral found on
+  Qualcomm Technologies, Inc. PMICs. The supported functionality includes power
+  on/off reason, kerelease detection, PMIC reset configurations and other
+  PON specific features. The PON module supports multiple physical power-on
+  (KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This
+  peripheral is connected to the host processor via the SPMI interface.y press/
+
+properties:
+  compatible:
+    const: qcom,qpnp-power-on
+
+  reg:
+    description: Specifies the SPMI base address for this
+                 PON (power-on) peripheral. For PMICs that have
+                 PON peripheral (GEN3) split into PON_HLOS and
+                 PON_PBS, this can hold addresses of both.
+                 PON_PBS base address needs to be specified for
+                 such devices if "qcom,kdpwr-sw-debounce" is specified.
+
+  reg-names:
+    description: For PON GEN1 and GEN2, it should be "pon".
+                 and for PON GEN3, it should include "pon_hlos" and
+                 optionally "pon_pbs".
+
+  interrupts:
+    description: Specifies the interrupts associated with PON.
+
+  interrupt-names:
+    description: Specifies the interrupt names associated with
+                 the interrupts property. Must be a subset of
+                 "kpdpwr", "kpdpwr-bark", "resin", "resin-bark",
+                 "cblpwr", "kpdpwr-resin-bark", and
+                 "pmic-wd-bark". Bark interrupts are associated
+                  with system reset configuration to allow default
+                  reset configuration to be activated. If system
+                  reset configuration is not supported then bark
+                  interrupts are nops. Additionally, the
+                  "pmic-wd-bark" interrupt can be added if the
+                  system needs to handle PMIC watchdog barks.
+
+  qcom,pon-dbc-delay:
+    description: The debounce delay for the power-key interrupt
+                 specified in us.
+                 Possible values for GEN1 PON are
+                 15625, 31250, 62500, 125000, 250000, 500000,
+                 1000000 and 2000000.
+                 Possible values for GEN2 PON are
+                 62, 123, 245, 489, 977, 1954, 3907, 7813,
+                 15625, 31250, 62500, 125000 and 250000.
+                 Intermediate value is rounded down to the
+                 nearest valid value.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,system-reset:
+    description: Boolean which specifies that this PON peripheral
+                 can be used to reset the system. This property
+                 can only be used by one device on the system. It
+                 is an error to include it more than once.
+    type: boolean
+
+  qcom,modem-reset:
+    description: Boolean which specifies that this PON peripheral
+                 can be used to reset the attached modem chip.
+                 This property can only be used by one PON device
+                 on the system. qcom,modem-reset and
+                 qcom,system-reset cannot be specified for the
+                 same PON device.
+    type: boolean
+
+  qcom,s3-debounce:
+    description: The debounce delay for stage 3 reset trigger in
+                 secs. The values range from 0 to 128.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,s3-src:
+    description: The source for stage 3 reset. It can be one of
+                 "kpdpwr", "resin", "kpdpwr-or-resin" or
+                 "kpdpwr-and-resin".
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,clear-warm-reset:
+    description: Boolean which specifies that the WARM_RESET
+                 reason registers need to be cleared for this
+                 target. The property is used for the targets
+                 which have a hardware feature to catch resets
+                 which aren't triggered by the application
+                 processor. In such cases clearing WARM_REASON
+                 registers across processor resets keeps the
+                 registers in a useful state.
+    type: boolean
+
+  qcom,secondary-pon-reset:
+    description: Boolean property which indicates that the PON
+                 peripheral is a secondary PON device which
+                 needs to be configured during reset in addition
+                 to the primary PON device that is configured
+                 for system reset through qcom,system-reset
+                 property.
+                 This should not be defined along with the
+                 qcom,system-reset or qcom,modem-reset property.
+    type: boolean
+
+  qcom,store-hard-reset-reason:
+    description: Boolean property which if set will store the
+                 hardware reset reason to SOFT_RB_SPARE register
+                 of the core PMIC PON peripheral.
+    type: boolean
+
+  qcom,hard-reset-poweroff-type:
+    description: Same description as
+                 qcom,warm-reset-poweroff-type but this applies
+                 for the system hard reset case.
+    type: boolean
+
+  qcom,kpdpwr-sw-debounce:
+    description: Boolean property to enable the debounce logic
+                 on the KPDPWR_N rising edge.
+    type: boolean
+
+  qcom,pon_X:
+    description: These PON child nodes correspond to features
+                 supported by the PON peripheral including reset
+                 configurations, pushbutton keys, and regulators.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+
+patternProperties:
+  "^pon-[0-9]+$":
+    type: object
+    $ref: input.yaml#
+    unevaluatedProperties: false
+
+    properties:
+      regulator-name:
+        description: Regulator name for the PON regulator that is being configured.
+
+      qcom,pon-spare-reg-addr:
+        description: Register offset from the base address of the
+                 PON peripheral that needs to be configured for
+                 the regulator being controlled.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pon-spare-reg-bit:
+        description: Bit position in the specified register that
+                 needs to be configured for the regulator being
+                 controlled.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pon-type:
+        description: The type of PON/RESET source. Supported values are
+                    0 = KPDPWR
+                    1 = RESIN
+                    2 = CBLPWR
+                    3 = KPDPWR_RESIN
+                    These values are PON_POWER_ON_TYPE_* found in
+                    include/dt-bindings/input/qcom,qpnp-power-on.h
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      qcom,pull-up:
+        description: Boolean flag indicating if a pull-up resistor
+                    should be enabled for the input.
+        type: boolean
+
+      qcom,support-reset:
+        description: Indicates if this PON source supports
+                    reset functionality.
+                    0 = Not supported
+                    1 = Supported
+                    If this property is not defined, then default S2
+                    reset configurations should not be modified.
+        type: boolean
+
+      qcom,use-bark:
+        description: Specify if this PON type needs to handle a bark
+                     interrupt.
+        type: boolean
+
+      linux,code:
+        description: The input key-code associated with the reset
+                     source. The reset source in its default
+                     configuration can be used to support standard keys.
+
+      qcom,s1-timer:
+        description: The debounce timer for the BARK interrupt for
+                     the reset source. Value is specified in ms.
+                     Supported values are
+                     0, 32, 56, 80, 128, 184, 272, 408, 608, 904,
+                     1352, 2048, 3072, 4480, 6720, 10256
+        type: boolean
+
+      qcom,s2-timer:
+        description: The debounce timer for the S2 reset specified
+                     in ms. On the expiry of this timer, the PMIC
+                     executes the reset sequence.
+                     Supported values are
+                     0, 10, 50, 100, 250, 500, 1000, 2000
+        type: boolean
+
+      qcom,s2-type:
+        description: The type of reset associated with this source.
+                     Supported values
+                     0 = SOFT_RESET (legacy)
+                     1 = WARM_RESET
+                     4 = SHUTDOWN
+                     5 = DVDD_SHUTDOWN
+                     7 = HARD_RESET
+                     8 = DVDD_HARD_RESET
+                     These values are PON_POWER_OFF_TYPE_* found in
+                     include/dt-bindings/input/qcom,qpnp-power-on.h
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+    required:
+      - regulator-name
+      - qcom,pon-spare-reg-addr
+      - qcom,pon-spare-reg-bit
+      - qcom,pon-type
+      - qcom,s1-timer
+      - qcom,s2-timer
+      - qcom,s2-type
+
+    additionalProperties: false
+
+allOf:
+  - $ref: input.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    qcom,power-on@800 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x800>;
+               interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+                            <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>,
+                            <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>,
+                            <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>;
+               interrupt-names = "kpdpwr", "resin", "resin-bark",
+                                 "kpdpwr-resin-bark";
+               qcom,pon-dbc-delay = <15625>;
+               qcom,system-reset;
+               qcom,s3-debounce = <32>;
+               qcom,s3-src = "resin";
+               qcom,clear-warm-reset;
+               qcom,store-hard-reset-reason;
+               qcom,pon_1 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+                           qcom,pull-up;
+                           linux,code = <KEY_POWER>;
+               };
+               qcom,pon_2 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+                           qcom,support-reset = <1>;
+                           qcom,pull-up;
+                           qcom,s1-timer = <0>;
+                           qcom,s2-timer = <2000>;
+                           qcom,s2-type = <PON_POWER_OFF_TYPE_WARM_RESET>;
+                           linux,code = <KEY_VOLUMEDOWN>;
+                           qcom,use-bark;
+               };
+               qcom,pon_3 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR_RESIN>;
+                           qcom,support-reset = <1>;
+                           qcom,s1-timer = <6720>;
+                           qcom,s2-timer = <2000>;
+                           qcom,s2-type = <PON_POWER_OFF_TYPE_HARD_RESET>;
+                           qcom,pull-up;
+                           qcom,use-bark;
+               };
+    };
+  - |
+    qcom,power-on@800 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x800>;
+               qcom,secondary-pon-reset;
+               qcom,hard-reset-poweroff-type = <PON_POWER_OFF_TYPE_SHUTDOWN>;
+
+               pon_perph_reg:qcom,pon_perph_reg {
+                                                 regulator-name = "pon_spare_reg";
+                                                 qcom,pon-spare-reg-addr = <0x8c>;
+                                                 qcom,pon-spare-reg-bit = <1>;
+               };
+    };
+  - |
+    pon_hlos@1300 {
+               compatible = "qcom,qpnp-power-on";
+               reg = <0x1300>, <0x800>;
+               reg-names = "pon_hlos", "pon_pbs";
+               interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>
+                            <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+               interrupt-names = "kpdpwr", "resin";
+               qcom,kpdpwr-sw-debounce;
+
+               qcom,pon_1 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+                           linux,code = <KEY_POWER>;
+               };
+               qcom,pon_2 {
+                           qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+                           linux,code = <KEY_VOLUMEDOWN>;
+               };
+    };
+...