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Merge "ARM: dts: msm: Update wlan device tree support for Canoe" into wlan-platform.lnx.2.0

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CNSS_WLAN Service
2024-10-21 13:44:17 -07:00
committed by Gerrit - the friendly Code Review server
parent e3646d145f 3059aac8f8
commit ca0a9492d6
2 changed files with 11 additions and 104 deletions
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10
canoe-kiwi-cnss.dts
View File

@@ -12,8 +12,10 @@
/ {
model = "Qualcomm Technologies, Inc. Canoe SoCs";
compatible = "qcom,canoe", "qcom,canoep", "qcom,canoe-mtp", "qcom,canoe-cdp";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0x20001 0>, <0x20008 0>, <0x40015 0>;
qcom,msm-id = <0x10294 0x10000>, <0x10294 0x20000>, <0x10295 0x10000>, <0x10295 0x20000>,
<0x30294 0x10000>, <0x30294 0x20000>, <0x30295 0x10000>, <0x30295 0x20000>,
<0x1010294 0x10000>, <0x1010294 0x20000>, <0x1010295 0x10000>,
<0x1010295 0x20000>, <0x1030294 0x10000>, <0x1030294 0x20000>,
<0x1030295 0x10000>, <0x1030295 0x20000>;
qcom,board-id = <0x1000001 0>, <0x1000008 0>, <0x1000015 0>;
};

105
canoe-kiwi-cnss.dtsi
View File

@@ -65,13 +65,13 @@
&soc {
wlan_kiwi: qcom,cnss-kiwi@b0000000 {
compatible = "qcom,cnss-kiwi";
reg = <0xb0000000 0x10000>;
reg = <0x0 0xb0000000 0x0 0x10000>;
reg-names = "smmu_iova_ipa";
qcom,wlan-sw-ctrl-gpio = <&tlmm 19 0>;
supported-ids = <0x1107>;
wlan-en-gpio = <&tlmm 16 0>;
qcom,bt-en-gpio = <&pm8550vs_f_gpios 3 0>;
qcom,bt-en-gpio = <&pmh0104_gpios 5 0>;
qcom,sw-ctrl-gpio = <&tlmm 18 0>;
/* List of GPIOs to be setup for interrupt wakeup capable */
mpm_wake_set_gpios = <18 19>;
@@ -91,104 +91,9 @@
/* For AOP communication, use direct QMP instead of mailbox */
qcom,qmp = <&aoss_qmp>;
vdd-wlan-io-supply = <&L3F>;
qcom,vdd-wlan-io-config = <1800000 1800000 30000 0 1>;
vdd-wlan-io12-supply = <&L2F>;
qcom,vdd-wlan-io12-config = <1200000 1200000 30000 0 1>;
vdd-wlan-supply = <&S4J>;
qcom,vdd-wlan-config = <932000 1000000 0 0 0>;
vdd-wlan-aon-supply = <&S4D>;
qcom,vdd-wlan-aon-config = <976000 1036000 0 0 1>;
vdd-wlan-dig-supply = <&S1D>;
qcom,vdd-wlan-dig-config = <916000 1100000 0 0 1>;
vdd-wlan-rfa1-supply = <&S3G>;
qcom,vdd-wlan-rfa1-config = <1864000 2000000 0 0 1>;
vdd-wlan-rfa2-supply = <&S7I>;
qcom,vdd-wlan-rfa2-config = <1316000 1340000 0 0 1>;
vdd-wlan-ant-share-supply = <&L6K>;
qcom,vdd-wlan-ant-share-config = <1800000 1800000 0 0 1>;
// TODO REGULATORS
interconnects =
<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <9>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
<2250 800000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
<7500 800000>,
/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
<30000 800000>,
/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
<100000 800000>,
/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
<175000 3224000>,
/* ultra high: DBS mode snoc/anoc: 403 Mhz */
<312500 3224000>,
/* super high: DBS mode snoc/anoc: 533 Mhz */
<587500 4264000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
<7500 1600000>,
/** ICC Path 2 **/
<0 0>,
/* idle: 0-18 Mbps ddr: 547.2 MHz */
<2250 2188800>,
/* low: 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>,
/* medium: 60-240 Mbps ddr: 547.2 MHz */
<30000 2188800>,
/* high: 240-1200 Mbps ddr: 547.2 MHz */
<100000 2188800>,
/* very high: > 1200 Mbps ddr: 1555 MHz */
<175000 6220800>,
/* ultra high: DBS mode ddr: 2092 MHz */
<312500 8368000>,
/* super high: DBS mode ddr: 3.2 GHz */
<587500 12800000>,
/* low (latency critical): 18-60 Mbps ddr: 547.2 MHz */
<7500 2188800>;
qcom,vreg_pdc_map =
"s4j", "bb",
"s4d", "bb",
"s3g", "rf",
"s7i", "rf",
"s1d", "rf";
qcom,pmu_vreg_map =
"VDD095_MX_PMU", "s4d",
"VDD095_PMU", "s4j",
"VDD_PMU_AON_I", "s1d",
"VDD095_PMU_BT", "s1d",
"VDD09_PMU_RFA_I", "s1d",
"VDD13_PMU_PCIE_I", "s7i",
"VDD13_PMU_RFA_I", "s7i",
"VDD19_PMU_PCIE_I", "s3g",
"VDD19_PMU_RFA_I", "s3g";
qcom,pdc_init_table =
"{class: wlan_pdc, ss: rf, res: s3g.v, upval: 1856}",
"{class: wlan_pdc, ss: rf, res: s3g.v, dwnval: 1844}",
"{class: wlan_pdc, ss: rf, res: s7i.v, upval: 1316}",
"{class: wlan_pdc, ss: rf, res: s7i.v, dwnval: 972}",
"{class: wlan_pdc, ss: rf, res: s1d.m, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, enable: 1}",
"{class: wlan_pdc, ss: rf, res: s1d.v, upval: 916}",
"{class: wlan_pdc, ss: rf, res: s1d.v, dwnval: 880}",
"{class: wlan_pdc, ss: rf, res: s4j.m, enable: 0}",
"{class: wlan_pdc, ss: rf, res: s4j.v, enable: 0}",
"{class: wlan_pdc, ss: bb, res: s4d.v, upval: 976}",
"{class: wlan_pdc, ss: bb, res: s4d.v, dwnval: 536}",
"{class: wlan_pdc, ss: bb, res: s4j.m, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s4j.v, enable: 1}",
"{class: wlan_pdc, ss: bb, res: s4j.v, upval: 932}",
"{class: wlan_pdc, ss: bb, res: s4j.v, dwnval: 444}";
// TODO PDC TABLE BUS BW
/* cpu mask used for wlan tx rx interrupt affinity
* <cpumask_for_rx_interrupts cpumask_for_tx_comp_interrupts>
@@ -208,7 +113,7 @@
#size-cells = <1>;
cnss_pci0_iommu_region_partition: cnss_pci0_iommu_region_partition {
/* address-cells =3 size-cells=2 from sun-pcie.dtsi */
/* address-cells =3 size-cells=2 from canoe-pcie.dtsi */
iommu-addresses = <&cnss_pci0 0x0 0x0 0x0 0x0 0x98000000>,
<&cnss_pci0 0x0 0x0 0xB0000000 0x0 0x50000000>;
};