diff --git a/tuna-audio-overlay.dtsi b/tuna-audio-overlay.dtsi
index 66bcccf9..2ae45331 100644
--- a/tuna-audio-overlay.dtsi
+++ b/tuna-audio-overlay.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <bindings/qcom,audio-ext-clk.h>
@@ -32,7 +32,19 @@
 		reg = <0x7660000 0x0>;
 		clock-names = "lpass_audio_hw_vote";
 		clocks = <&lpass_audio_hw_vote 0>;
-		qcom,va-dmic-sample-rate = <600000>;
+		/*
+		 * Clk divding factors for each DMIC pair.
+		 * Valid entries for each DMIC pair:
+		 *	2, 3, 4, 6, 8, 16
+		 *
+		 * These factors are translated to corresponding config values
+		 *  for the following registers,
+		 *   -- LPASS_VA_TOP_CSR_DMIC0_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC1_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC2_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC3_CTL,
+		 */
+		qcom,va-dmic-clk-div-factor = <16 16 16 16>;
 		qcom,va-clk-mux-select = <1>;
 		qcom,default-clk-id = <TX_CORE_CLK>;
 		qcom,use-clk-id = <VA_CORE_CLK>;
@@ -84,7 +96,19 @@
 		compatible = "qcom,lpass-cdc-tx-macro";
 		reg = <0x6AE0000 0x0>;
 		qcom,default-clk-id = <TX_CORE_CLK>;
-		qcom,tx-dmic-sample-rate = <2400000>;
+		/*
+		 * Clk divding factors for each DMIC pair.
+		 * Valid entries for each DMIC pair:
+		 *	2, 3, 4, 6, 8, 16
+		 *
+		 * These factors are translated to corresponding config values
+		 *  for the following registers,
+		 *   -- LPASS_VA_TOP_CSR_DMIC0_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC1_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC2_CTL,
+		 *   -- LPASS_VA_TOP_CSR_DMIC3_CTL,
+		 */
+		qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
 		qcom,is-used-swr-gpio = <0>;
 	};