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Merge 7dc162272f on remote branch

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Change-Id: Idb500f314025d7e8569f9574aa70ee7f42591912
This commit is contained in:
Linux Build Service Account
2025-04-02 01:08:42 -07:00
parent 4b053c109a 7dc162272f
commit c99076b99c
27 changed files with 1509 additions and 13 deletions
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12
qcom/Makefile
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@@ -112,6 +112,18 @@ sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS) $(KE
dtb-y += $(sun-dtb-y)
QCS610_BASE_DTB += qcs610.dtb
QCS610_BOARDS += \
qcs610-iot-overlay.dtbo \
qcs610-ipc-overlay.dtbo \
qcs610-opk-overlay.dtbo
qcs610-dtb-$(CONFIG_ARCH_SM6150) += \
$(call add-overlays, $(QCS610_BOARDS),$(QCS610_BASE_DTB))
qcs610-overlays-dtb-$(CONFIG_ARCH_SM6150) += $(QCS610_BOARDS) $(QCS610_BASE_DTB)
dtb-y += $(qcs610-dtb-y)
PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb
PINEAPPLE_APQ_BASE_DTB += pineapplep.dtb pineapplep-v2.dtb

2
qcom/kera-reserved-memory.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&reserved_memory {

2
qcom/kera.dtsi
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@@ -3295,7 +3295,7 @@
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 441600 364800 >,
< 595200 556800 >,
< 595200 518400 >,
< 787200 710400 >,
< 902400 806400 >,
< 1113600 998400 >,

12
qcom/platform_map.bzl
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@@ -127,6 +127,18 @@ _platform_map = {
],
"binary_compatible_with": ["tuna", "kera"],
},
"qcs610": {
"dtb_list": [
# keep sorted
{"name": "qcs610.dtb"},
],
"dtbo_list": [
# keep sorted
{"name": "qcs610-iot-overlay.dtbo"},
{"name": "qcs610-ipc-overlay.dtbo"},
{"name": "qcs610-opk-overlay.dtbo"},
],
},
"tuna": {
"dtb_list": [
{"name": "tuna.dtb"},

15
qcom/qcs610-iot-overlay.dts Normal file
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT Overlay";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 0>;
};

10
qcom/qcs610-iot.dtsi Normal file
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 0>;
};

16
qcom/qcs610-ipc-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-ipc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT IPC";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 1>;
};

12
qcom/qcs610-ipc.dtsi Normal file
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@@ -0,0 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "qcs610-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IPC";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 1>;
};

16
qcom/qcs610-opk-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-opk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Openkit Overlay";
compatible = "qcom,qcs610-opk", "qcom,qcs610", "qcom,opk";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 3>;
};

14
qcom/qcs610-opk.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 0>;
};

14
qcom/qcs610.dts Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "qcs610.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 SoC";
compatible = "qcom,qcs610";
qcom,board-id = <0 0>;
};

12
qcom/qcs610.dtsi Normal file
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@@ -0,0 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sm6150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610";
qcom,msm-name = "QCS610";
qcom,msm-id = <401 0>;
};

568
qcom/sm6150.dtsi Normal file
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@@ -0,0 +1,568 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
model = "Qualcomm Technologies, Inc. SM6150";
compatible = "qcom,sm6150";
qcom,msm-name = "SM6150";
qcom,msm-id = <355 0x0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=2M earlycon=msm_geni_serial,0x880000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
aliases: aliases { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
};
cluster1 {
core0 {
cpu = <&CPU6>;
};
core1 {
cpu = <&CPU7>;
};
};
};
};
soc: soc { };
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_region: hyp_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
no-map;
reg = <0x0 0x85e00000 0x0 0x120000>;
};
aop_cmd_db: memory@85f20000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85f20000 0x0 0x20000>;
no-map;
};
sec_apps_mem: sec_apps_region@85fff000 {
no-map;
reg = <0x0 0x85fff000 0x0 0x1000>;
};
smem_region: smem@86000000 {
no-map;
reg = <0x0 0x86000000 0x0 0x200000>;
};
removed_region: removed_region@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x2d00000>;
};
pil_camera_mem: camera_region@8ab00000 {
no-map;
reg = <0x0 0x8ab00000 0x0 0x500000>;
};
pil_modem_mem: modem_region@8b000000 {
no-map;
reg = <0x0 0x8b000000 0x0 0x8400000>;
};
pil_video_mem: pil_video_region@93400000 {
no-map;
reg = <0x0 0x93400000 0x0 0x500000>;
};
wlan_msa_mem: wlan_msa_region@93900000 {
no-map;
reg = <0x0 0x93900000 0x0 0x200000>;
};
pil_cdsp_mem: cdsp_regions@93b00000 {
no-map;
reg = <0x0 0x93b00000 0x0 0x1e00000>;
};
pil_adsp_mem: pil_adsp_region@95900000 {
no-map;
reg = <0x0 0x95900000 0x0 0x1e00000>;
};
pil_ipa_fw_mem: ips_fw_region@97700000 {
no-map;
reg = <0x0 0x97700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
no-map;
reg = <0x0 0x97710000 0x0 0x5000>;
};
pil_gpu_mem: gpu_region@97715000 {
no-map;
reg = <0x0 0x97715000 0x0 0x2000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x9e400000 0x0 0x1400000>;
};
cdsp_sec_mem: cdsp_sec_regions@9f800000 {
no-map;
reg = <0x0 0x9f800000 0x0 0x1e00000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x1000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
reusable;
alignment = <0 0x400000>;
size = <0 0x800000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x8c00000>;
};
cont_splash_memory: splash_region {
reg = <0x0 0x9c000000 0x0 0x0f00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@9cf00000 {
reg = <0x0 0x9cf00000 0x0 0x0100000>;
label = "dfps_data_region";
};
disp_rdump_memory: disp_rdump_region@9c000000 {
reg = <0x0 0x9c000000 0x0 0x01000000>;
label = "disp_rdump_region";
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
size = <0 0x2800000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x2000000>;
linux,cma-default;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,drv-count = <3>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>,
<FAST_PATH_TCS 0>;
};
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
qcom,drv-count = <1>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
disp_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x1c00>;
channel@0 {
qcom,tcs-config = <SLEEP_TCS 1>,
<WAKE_TCS 1>,
<ACTIVE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
interrupt-parent = <&intc>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6150-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 6 0x4>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
qcom_tzlog: tz-log@146aa720 {
compatible = "qcom,tz-log";
reg = <0x146aa720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq",
"l1-l2-errirq",
"l3-scu-errirq",
"l3-scu-faultirq";
};
};

8
qcom/sun.dtsi
View File

@@ -2333,15 +2333,15 @@
"ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>;
resets = <&ufshc_mem 0>;
status = "disabled";
};

60
qcom/tuna-atp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-mtp.dtsi"
@@ -14,3 +14,61 @@
&L3G {
regulator-always-on;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

60
qcom/tuna-mtp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -113,3 +113,61 @@
&usb0 {
qcom,wcd_usbss = <&wcd_usbss>;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

14
qcom/tuna-pmic-overlay.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -120,6 +120,14 @@
nvmem-names = "pon_log0", "pon_log1";
depends-on-supply = <&gh_watchdog>;
};
regulator_ocp_notifier: regulator-ocp-notifier {
compatible = "qcom,regulator-ocp-notifier";
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0x71 0x1 IRQ_TYPE_EDGE_RISING>;
nvmem-cells = <&ocp_log>;
nvmem-cell-names = "ocp_log";
};
};
&thermal_zones {
@@ -435,3 +443,7 @@
io-channels = <&pmk8550_vadc PMXR2230_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&battery_charger {
qcom,ship-mode-immediate;
};

60
qcom/tuna-qrd.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -174,3 +174,61 @@
qcom,wcd_usbss = <&wcd_usbss>;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

4
qcom/tuna-vm-cdp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

4
qcom/tuna-vm-mtp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

3
qcom/tuna-vm-qrd.dtsi
View File

@@ -13,6 +13,9 @@
st_fts@0 {
compatible = "st,fts";
reg = <0x0>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

4
qcom/tuna-vm-rcm.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;