Merge "bindings: soc: qcom: add Glink PMIC debug controller binding documentation"

2023-08-02 09:25:03 -07:00
parent 89b6608129 1da4900b9b
commit c85e9ca667
1 changed files with 132 additions and 0 deletions
--- a/bindings/soc/qcom/qcom,pmic-glink-debug.yaml
+++ b/bindings/soc/qcom/qcom,pmic-glink-debug.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,pmic-glink-debug.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Glink PMIC Debug Controller
+
+maintainers:
+  - David Collins <quic_collinsd@quicinc.com>
+
+description: |
+  The Qualcomm Technologies, Inc. Glink PMIC debug controller device provides an
+  interface to read and write PMIC registers over PMIC Glink using a remote
+  subsytem (e.g. DSP).  This allows for debugging PMIC peripherals on either
+  SPMI bus or I2C bus that would typically only be accessible to the charger
+  and fuel gauging firmware running on the remote subsystem.
+
+  The Glink PMIC debug controller node must contain at least one child node.
+  Each child node corresponds to either an SPMI bus or I2C bus accessible from
+  the remote subsystem.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - qcom,pmic-glink-debug
+          - qcom,spmi-glink-debug
+          - qcom,i2c-glink-debug
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
+
+patternProperties:
+  "spmi@[0-9a-f]+$":
+    description: SPMI bus node
+    $ref: /schemas/spmi/spmi.yaml#
+    type: object
+
+    properties:
+      qcom,bus-type:
+        description: |
+          Specifies the bus type on the remote subsystem to access the PMIC
+          devices defined in the child nodes.
+        $ref: /schemas/types.yaml#/definitions/string
+        const: spmi
+        default: spmi
+
+      reg:
+        description: |
+          The bus ID used by firmware.
+
+          For a directly connected SPMI bus, this is the physical SPMI bus ID in
+          the system.
+
+          For an SPMI-bridge bus which relies on the brain PMIC for the real
+          SPMI bus transaction, the bus ID is specified with an offset of 0x200.
+        items:
+          items:
+            - oneOf:
+                - minimum: 0x0
+                  maximum: 0x7
+                - minimum: 0x200
+                  maximum: 0x207
+
+    required:
+      - reg
+
+  "i2c@[0-9a-f]+$":
+    description: I2C bus node
+    $ref: /schemas/i2c/i2c-controller.yaml#
+    type: object
+
+    properties:
+      qcom,bus-type:
+        description: |
+          Specifies the bus type on the remote subsystem to access the PMIC
+          devices defined in the child nodes.
+        $ref: /schemas/types.yaml#/definitions/string
+        const: i2c
+
+      reg:
+        description: |
+          The bus ID used by firmware.
+
+          This is the I2C bus instance ID (indexed from 1) in the remote
+          subsystem along with an added offset of 0x100.
+        minimum: 0x101
+        maximum: 0x1ff
+
+    required:
+      - reg
+      - qcom,bus-type
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    pmic_glink_log {
+        spmi_glink_debug {
+            compatible = "qcom,spmi-glink-debug";
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            spmi@0 {
+                reg = <0>;
+            };
+
+            spmi@1 {
+                reg = <1>;
+                qcom,bus-type = "spmi";
+            };
+
+            /* I2C bus with instance ID 7 in ADSP for SE6 */
+            i2c@107 {
+                reg = <0x107>;
+                qcom,bus-type = "i2c";
+            };
+
+            /* SPMI-bridge bus 0 */
+            spmi@200 {
+                reg = <0x200>;
+                qcom,bus-type = "spmi";
+            };
+        };
+    };