From c7e6793e97b71f74a3215525edf8f01f7a352c05 Mon Sep 17 00:00:00 2001
From: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Date: Thu, 12 Dec 2024 16:49:59 +0530
Subject: [PATCH] ARM: dts: msm: Update WLAN IB voting for tuna

Currently the WLAN SNOC voting is set based on
PCIe SN4 BCM width as 16.The PCIe port width has been
updated to 8 for tuna. Hence, this change will
bring in the corresponding WLAN SNOC voting to support
the new width.

Also, update the DDR voting accordingly.

CRs-Fixed: 3999629
Change-Id: Iff5b87616f1f340257096826906ca77bdba4ce29
---
 tuna-kiwi-cnss.dtsi | 30 +++++++++++++++---------------
 tuna-wcn7750.dtsi   | 30 +++++++++++++++---------------
 2 files changed, 30 insertions(+), 30 deletions(-)

diff --git a/tuna-kiwi-cnss.dtsi b/tuna-kiwi-cnss.dtsi
index 1eed8a92..f0f48637 100644
--- a/tuna-kiwi-cnss.dtsi
+++ b/tuna-kiwi-cnss.dtsi
@@ -133,39 +133,39 @@
 		/** ICC Path 1 **/
 		<0 0>, /* no vote */
 		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
-		<2250 1200000>,
+		<2250 400000>,
 		/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
-		<7500 1200000>,
+		<7500 400000>,
 		/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
-		<30000 1200000>,
+		<30000 400000>,
 		/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
-		<100000 1200000>,
+		<100000 400000>,
 		/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
-		<175000 3224000>,
+		<175000 1612000>,
 		/* ultra high: DBS mode snoc/anoc: 403 Mhz */
-		<312500 3224000>,
+		<312500 1612000>,
 		/* super high: DBS mode snoc/anoc: 533 Mhz */
-		<587500 4264000>,
+		<587500 2171000>,
 		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
-		<7500 1600000>,
+		<7500 800000>,
 
 		/** ICC Path 2 **/
 		<0 0>,
-		/* idle: 0-18 Mbps ddr: 451.2 MHz */
+		/* idle: 0-18 Mbps ddr: 547 MHz */
 		<2250 2188800>,
-		/* low: 18-60 Mbps ddr: 451.2 MHz */
+		/* low: 18-60 Mbps ddr: 547 MHz */
 		<7500 2188800>,
-		/* medium: 60-240 Mbps ddr: 451.2 MHz */
+		/* medium: 60-240 Mbps ddr: 547 MHz */
 		<30000 2188800>,
-		/* high: 240-1200 Mbps ddr: 451.2 MHz */
+		/* high: 240-1200 Mbps ddr: 547 MHz */
 		<100000 2188800>,
 		/* very high: > 1200 Mbps ddr: 1555 MHz */
 		<175000 6220800>,
 		/* ultra high: DBS mode ddr: 2092 MHz */
-		<312500 8368000>,
+		<312500 8371200>,
 		/* super high: DBS mode ddr: 3.2 GHz */
-		<587500 12800000>,
-		/* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */
+		<587500 14745600>,
+		/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
 		<7500 2188800>;
 
 		qcom,pdc_init_table =
diff --git a/tuna-wcn7750.dtsi b/tuna-wcn7750.dtsi
index 97d70346..c0c276c3 100644
--- a/tuna-wcn7750.dtsi
+++ b/tuna-wcn7750.dtsi
@@ -125,39 +125,39 @@
 		/** ICC Path 1 **/
 		<0 0>, /* no vote */
 		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz */
-		<2250 1200000>,
+		<2250 400000>,
 		/* low: 18-60 Mbps snoc/anoc: 100 Mhz */
-		<7500 1200000>,
+		<7500 400000>,
 		/* medium: 60-240 Mbps snoc/anoc: 100 Mhz */
-		<30000 1200000>,
+		<30000 400000>,
 		/* high: 240-1200 Mbps snoc/anoc: 100 Mhz */
-		<100000 1200000>,
+		<100000 400000>,
 		/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
-		<175000 3224000>,
+		<175000 1612000>,
 		/* ultra high: DBS mode snoc/anoc: 403 Mhz */
-		<312500 3224000>,
+		<312500 1612000>,
 		/* super high: DBS mode snoc/anoc: 533 Mhz */
-		<587500 4264000>,
+		<587500 2171000>,
 		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz */
-		<7500 1600000>,
+		<7500 800000>,
 
 		/** ICC Path 2 **/
 		<0 0>,
-		/* idle: 0-18 Mbps ddr: 451.2 MHz */
+		/* idle: 0-18 Mbps ddr: 547 MHz */
 		<2250 2188800>,
-		/* low: 18-60 Mbps ddr: 451.2 MHz */
+		/* low: 18-60 Mbps ddr: 547 MHz */
 		<7500 2188800>,
-		/* medium: 60-240 Mbps ddr: 451.2 MHz */
+		/* medium: 60-240 Mbps ddr: 547 MHz */
 		<30000 2188800>,
-		/* high: 240-1200 Mbps ddr: 451.2 MHz */
+		/* high: 240-1200 Mbps ddr: 547 MHz */
 		<100000 2188800>,
 		/* very high: > 1200 Mbps ddr: 1555 MHz */
 		<175000 6220800>,
 		/* ultra high: DBS mode ddr: 2092 MHz */
-		<312500 8368000>,
+		<312500 8371200>,
 		/* super high: DBS mode ddr: 3.2 GHz */
-		<587500 12800000>,
-		/* low (latency critical): 18-60 Mbps ddr: 451.2 MHz */
+		<587500 14745600>,
+		/* low (latency critical): 18-60 Mbps ddr: 547 MHz */
 		<7500 2188800>;
 
 		icnss_cdev_apss: qcom,icnss_cdev1 {