From b75b1742d60b9a8b54f4c0e4e97dcdd97491e7d9 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 11 Dec 2024 18:21:01 +0530 Subject: [PATCH 1/5] ARM: dts: msm: Add tzone-names for Tuna GPU Add GPU tzone-names to get the GPU temperature on Tuna gpu. Change-Id: I71ab003259484ea0fa7f9c9613967909bef6c6c3 Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index c56c55ff..80807520 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -41,6 +41,9 @@ qcom,ubwc-mode = <5>; + qcom,tzone-names = "gpu-0", "gpu-1", "gpu-2", "gpu-3", + "gpu-4", "gpu-5"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From 1f4df4368b9112b8ad63e20fcbe248a3c8366b14 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Fri, 1 Nov 2024 14:35:44 +0530 Subject: [PATCH 2/5] ARM: dts: msm: Add dt support for TunaP gpu Add the necessary initial support for TunaP variant. Change-Id: Iff04d6992010da8a496a53727378fc5e1e5cd88c Signed-off-by: SIVA MULLATI --- gpu/tuna-gpu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gpu/tuna-gpu.dts b/gpu/tuna-gpu.dts index 0c480c2d..2f29cdef 100644 --- a/gpu/tuna-gpu.dts +++ b/gpu/tuna-gpu.dts @@ -19,7 +19,7 @@ / { model = "Qualcomm Technologies, Inc. tuna"; - compatible = "qcom,tuna"; - qcom,msm-id = <0x28f 0x10000>; + compatible = "qcom,tuna", "qcom,tunap"; + qcom,msm-id = <0x28f 0x10000>, <0x2b6 0x10000>; qcom,board-id = <0 0>; }; From af0e7a0660bfbe4c218711f0776c9e7b1f45fcc6 Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 13 Nov 2024 20:06:34 +0530 Subject: [PATCH 3/5] ARM: dts: msm: Add support for Tuna7 GPU Add initial support for Tuna7 GPU in the devicetree. Change-Id: I66ac7382ce0dfc10291a2318e0da3d9880c24790 Signed-off-by: SIVA MULLATI --- Kbuild | 3 +- gpu/tuna-gpu-pwrlevels.dtsi | 390 ++++++++++++++++++++++++++++-------- gpu/tuna-gpu.dtsi | 3 + gpu/tuna7-gpu.dts | 30 +++ gpu/tuna7-gpu.dtsi | 10 + 5 files changed, 352 insertions(+), 84 deletions(-) create mode 100644 gpu/tuna7-gpu.dts create mode 100644 gpu/tuna7-gpu.dtsi diff --git a/Kbuild b/Kbuild index eef19472..d56aed40 100644 --- a/Kbuild +++ b/Kbuild @@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \ endif ifeq ($(CONFIG_ARCH_TUNA), y) -dtbo-y += gpu/tuna-gpu.dtbo +dtbo-y += gpu/tuna-gpu.dtbo \ + gpu/tuna7-gpu.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/gpu/tuna-gpu-pwrlevels.dtsi b/gpu/tuna-gpu-pwrlevels.dtsi index 8294ea31..5d8edc86 100644 --- a/gpu/tuna-gpu-pwrlevels.dtsi +++ b/gpu/tuna-gpu-pwrlevels.dtsi @@ -5,111 +5,335 @@ &msm_gpu { /* Power levels */ - qcom,initial-pwrlevel = <8>; - - qcom,gpu-pwrlevels { - compatible="qcom,gpu-pwrlevels"; - + qcom,gpu-pwrlevel-bins { #address-cells = <1>; #size-cells = <0>; - /* Turbo_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <1050000000>; - qcom,level = ; + compatible = "qcom,gpu-pwrlevels-bins"; - qcom,bus-freq = <11>; - qcom,bus-min = <11>; - qcom,bus-max = <11>; + /* + * The bins need to match based on speed bin first and then SKU. + * Keep pwrlevel bins sorted in ascending order of the fmax of the bins. + */ + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Turbo */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <937000000>; - qcom,level = ; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <10>; - qcom,bus-min = <9>; - qcom,bus-max = <10>; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xd8>; + + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1025000000>; + qcom,level = ; + + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; + + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; + + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; + + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; + + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; + + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; - /* Nom_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <873000000>; - qcom,level = ; + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; - qcom,bus-freq = <9>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,initial-pwrlevel = <8>; + qcom,speed-bin = <0xf2>; - /* Nom */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <763000000>; - qcom,level = ; + /* Turbo_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <1050000000>; + qcom,level = ; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; - /* SVS_L2 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <688000000>; - qcom,level = ; + /* Turbo */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <937000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <10>; + }; - /* SVS_L1 */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <644000000>; - qcom,level = ; + /* Nom_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <873000000>; + qcom,level = ; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <510000000>; - qcom,level = ; + /* Nom */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <763000000>; + qcom,level = ; - qcom,bus-freq = <4>; - qcom,bus-min = <2>; - qcom,bus-max = <6>; - }; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - /* Low_SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <362000000>; - qcom,level = ; + /* SVS_L2 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <688000000>; + qcom,level = ; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; - }; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; - /* Low_SVS_D1 */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <264000000>; - qcom,level = ; + /* SVS_L1 */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <644000000>; + qcom,level = ; - qcom,bus-freq = <1>; - qcom,bus-min = <1>; - qcom,bus-max = <3>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <510000000>; + qcom,level = ; + + qcom,bus-freq = <4>; + qcom,bus-min = <2>; + qcom,bus-max = <6>; + }; + + /* Low_SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <362000000>; + qcom,level = ; + + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* Low_SVS_D1 */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <264000000>; + qcom,level = ; + + qcom,bus-freq = <1>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; }; }; }; diff --git a/gpu/tuna-gpu.dtsi b/gpu/tuna-gpu.dtsi index c56c55ff..2adffa7d 100644 --- a/gpu/tuna-gpu.dtsi +++ b/gpu/tuna-gpu.dtsi @@ -62,6 +62,9 @@ , /* TURBO_L1 index=10 */ ; /* TURBO_L2 index=11 */ + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + zap-shader { memory-region = <&gpu_microcode_mem>; }; diff --git a/gpu/tuna7-gpu.dts b/gpu/tuna7-gpu.dts new file mode 100644 index 00000000..5e5ce5e9 --- /dev/null +++ b/gpu/tuna7-gpu.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include +#include +#include + +#include "tuna-gpu.dtsi" +#include "tuna-gpu-pwrlevels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. tuna7 SoC"; + compatible = "qcom,tuna"; + qcom,msm-id = <0x2a9 0x10000>; + qcom,board-id = <0 0>; +}; + +&msm_gpu { + /delete-property/qcom,gpu-model; + qcom,gpu-model = "Adreno822"; +}; diff --git a/gpu/tuna7-gpu.dtsi b/gpu/tuna7-gpu.dtsi new file mode 100644 index 00000000..2a286fac --- /dev/null +++ b/gpu/tuna7-gpu.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-gpu.dtsi" + +&msm_gpu { + qcom,gpu-model = "Adreno822"; +}; From bc0f760601174e6bbd1c7187a98ae30ab14639ba Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 20 Dec 2024 15:38:15 +0530 Subject: [PATCH 4/5] ARM: dts: msm: Enable GenPD support for Kera GPU Enable GenPD support for Kera GPU. Change-Id: Ia9b1a99c694fc7d64f99c572d09388f82dc0a78c Signed-off-by: Harshitha Sai Neelati --- gpu/kera-gpu.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index c1c2eb31..2cec634e 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -115,7 +115,7 @@ compatible = "qcom,kgsl-smmu-v2"; reg = <0x3da0000 0x40000>; - vddcx-supply = <&gpu_cc_cx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>; gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; @@ -140,10 +140,10 @@ <0 305 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hfi", "gmu"; - regulator-names = "vddcx", "vdd"; - - vddcx-supply = <&gpu_cc_cx_gdsc>; - vdd-supply = <&gpu_cc_gx_gdsc>; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_CX_GMU_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", "gmu_cx", "gx"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, From f033f869e101c8830f8a81fdfd64494e6a579845 Mon Sep 17 00:00:00 2001 From: Siva Srinivas Venigalla Date: Wed, 25 Dec 2024 15:07:19 +0530 Subject: [PATCH 5/5] ARM: dts: msm: Add tzone-names for Kera GPU Add GPU tzone-names to get the GPU temperature on Kera gpu. Change-Id: Id4f45ffc3b9d34d9019fdbc4b27820c5868590ab Signed-off-by: Siva Srinivas Venigalla --- gpu/kera-gpu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi index 2cec634e..22834a3f 100644 --- a/gpu/kera-gpu.dtsi +++ b/gpu/kera-gpu.dtsi @@ -29,6 +29,8 @@ qcom,ubwc-mode = <4>; + qcom,tzone-names = "gpuss-0", "gpuss-1"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path";