From c5d0b9f392490703c11e4d36a21267287ac8a36a Mon Sep 17 00:00:00 2001 From: Ruchira Revdekar Date: Tue, 9 Jul 2024 11:11:09 +0530 Subject: [PATCH] ARM: dts: msm: Add a node for cpufreq cycle counter driver Add cpufreq cycle counter register information to devicetree in a separate node for use by driver. This will initialize walt for Monaco. Change-Id: Iddbbd81168d49e0aea4076f18669ffb6a5d342a8 Signed-off-by: Ruchira Revdekar --- qcom/monaco-walt.dtsi | 18 ++++++++++++++++++ qcom/monaco.dtsi | 1 + 2 files changed, 19 insertions(+) create mode 100644 qcom/monaco-walt.dtsi diff --git a/qcom/monaco-walt.dtsi b/qcom/monaco-walt.dtsi new file mode 100644 index 00000000..da618cdd --- /dev/null +++ b/qcom/monaco-walt.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + walt { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom,cycle-cntr { + compatible = "qcom,cycle-cntr-hw"; + reg = <0xf521000 0x1400>; + reg-names = "freq-domain0"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index b1777b35..c21691ab 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -2099,6 +2099,7 @@ #include "monaco-usb.dtsi" #include "monaco-thermal.dtsi" #include "msm-rdbg-monaco.dtsi" +#include "monaco-walt.dtsi" &gcc_camss_top_gdsc { parent-supply = <&VDD_CX_LEVEL>;