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Merge "ARM: dts: msm: Add UFS support for tuna"

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QCTECMDR Service
2024-10-04 10:57:44 -07:00
committed by Gerrit - the friendly Code Review server
parent fa909859d0 54e77dd206
commit c52ee8125b
4 changed files with 177 additions and 0 deletions
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45
qcom/tuna-cdp.dtsi
View File

@@ -38,3 +38,48 @@
&tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>;
}; };
}; };
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L1F>;
vdda-phy-max-microamp = <213100>;
/*
* Platforms supporting Gear 5 && Rate B require a different
* voltage supply. Check the Power Grid document.
*/
vdda-phy-min-microvolt = <912000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18340>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <1200000>;
vccq-supply = <&L3F>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L5B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};

44
qcom/tuna-mtp.dtsi
View File

@@ -38,3 +38,47 @@
}; };
}; };
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L1F>;
vdda-phy-max-microamp = <213100>;
/*
* Platforms supporting Gear 5 && Rate B require a different
* voltage supply. Check the Power Grid document.
*/
vdda-phy-min-microvolt = <912000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18340>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <1200000>;
vccq-supply = <&L3F>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L5B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};

45
qcom/tuna-qrd.dtsi
View File

@@ -41,3 +41,48 @@
}; };
}; };
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-pineapple";
/* VDDA_UFS_CORE */
vdda-phy-supply = <&L1F>;
vdda-phy-max-microamp = <213100>;
/*
* Platforms supporting Gear 5 && Rate B require a different
* voltage supply. Check the Power Grid document.
*/
vdda-phy-min-microvolt = <912000>;
/* VDDA_UFS_0_1P2 */
vdda-pll-supply = <&L4B>;
vdda-pll-max-microamp = <18340>;
/* Phy GDSC for VDD_MX, always on */
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
/* Qref power supply, Refer Qref diagram */
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <64500>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&L12B>;
vcc-max-microamp = <1200000>;
vccq-supply = <&L3F>;
vccq-max-microamp = <1200000>;
/* VDD_PX10 is voted for the ufs_reset_n */
qcom,vddp-ref-clk-supply = <&L5B>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&S2B>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};

43
qcom/tuna.dtsi
View File

@@ -1953,6 +1953,34 @@
status = "disabled"; status = "disabled";
}; };
ice_cfg: shared_ice {
alg1 {
alg-name = "alg1";
rx-alloc-percent = <60>;
status = "disabled";
};
alg2 {
alg-name = "alg2";
status = "disabled";
};
alg3 {
alg-name = "alg3";
num-core = <28 28 15 13>;
status = "ok";
};
};
ufshc_dma_resv: ufshc_dma_resv_region {
/*
* Restrict IOVA mappings for UFSHC buffers to the 3 GB region
* from 0x1000 - 0xffffffff.
*/
iommu-addresses = <&ufshc_mem 0x0 0x1000>;
};
ufshc_mem: ufshc@1d84000 { ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc"; compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>, reg = <0x1d84000 0x3000>,
@@ -2007,6 +2035,8 @@
iommus = <&apps_smmu 0x60 0x0>; iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "bypass"; qcom,iommu-dma = "bypass";
memory-region = <&ufshc_dma_resv>;
shared-ice-cfg = <&ice_cfg>;
dma-coherent; dma-coherent;
qcom,bypass-pbl-rst-wa; qcom,bypass-pbl-rst-wa;
@@ -2017,6 +2047,19 @@
reset-names = "rst"; reset-names = "rst";
status = "disabled"; status = "disabled";
qos0 {
mask = <0xfc>;
vote = <44>;
perf;
cpu_freq_vote = <2 5 7>;
};
qos1 {
mask = <0x03>;
vote = <44>;
cpu_freq_vote = <0>;
};
}; };
qcom_tzlog: tz-log@14680720 { qcom_tzlog: tz-log@14680720 {