diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 25357b7c..5612ec26 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -32,6 +32,7 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e219d5ed..e417cdb2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -34,6 +34,7 @@ qcom,mdss-dsi-te-dcs-command = <1>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 83152a0e..53de247a 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -22,6 +22,7 @@ qcom,mdss-dsi-tx-eot-append; qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 70ba9540..d4647340 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -27,6 +27,7 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c517fc02..bec6e766 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -177,8 +177,8 @@ qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; - qcom,sde-max-bw-low-kbps = <17000000>; - qcom,sde-max-bw-high-kbps = <27000000>; + qcom,sde-max-bw-low-kbps = <18900000>; + qcom,sde-max-bw-high-kbps = <28500000>; qcom,sde-min-core-ib-kbps = <2500000>; qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <800000>; @@ -285,10 +285,10 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; }; @@ -298,10 +298,10 @@ qcom,sde-fp16-unmult = <0x280 0x00010000>; qcom,sde-fp16-gc = <0x280 0x00010000>; qcom,sde-fp16-csc = <0x280 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; }; }; @@ -314,10 +314,10 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; }; @@ -327,24 +327,24 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; }; }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-igc = <0x1260 0x00050000>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone = <0x900 0x00020000>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; qcom,sde-dspp-gamut = <0x1000 0x00040003>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; qcom,sde-dspp-dither = <0x82c 0x00010007>; }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index ae31c68c..18c83c8e 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -181,10 +181,16 @@ }; }; + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd5500000 0x02b00000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x800 0x2>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + memory-region = <&smmu_sde_iommu_region_partition>; qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ dma-coherent; @@ -193,7 +199,7 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + memory-region = <&smmu_sde_iommu_region_partition>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; @@ -231,7 +237,7 @@ qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <2500000 0 800000>; - qcom,sde-dspp-ltm-version = <0x00010002>; + qcom,sde-dspp-ltm-version = <0x00010003>; /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;