From f2e0a783250535f8f218bd4b7fee687a1efc7559 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 27 May 2024 11:46:07 +0530 Subject: [PATCH 01/66] bindings: interrupt-controller: Document PDC compatible for kera Document PDC compatible for kera. Change-Id: I17786ef1035dbaf56ad7077c8d936d5514c034a8 Signed-off-by: Sneh Mankad --- bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/interrupt-controller/qcom,pdc.yaml b/bindings/interrupt-controller/qcom,pdc.yaml index 35da8d13..3a8e786d 100644 --- a/bindings/interrupt-controller/qcom,pdc.yaml +++ b/bindings/interrupt-controller/qcom,pdc.yaml @@ -37,6 +37,7 @@ properties: - qcom,parrot-pdc - qcom,ravelin-pdc - qcom,tuna-pdc + - qcom,kera-pdc - const: qcom,pdc reg: From b751e5268caf9bd8679d1d064b1ca1bfc26be3ef Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Tue, 30 Apr 2024 16:43:09 +0530 Subject: [PATCH 02/66] ARM: dts: msm: Add support for GCC and TCSRCC on Tuna Add support for GCC and TCSRCC on Tuna platform. While at it, move gcc's GDSC to real. Change-Id: Ife8d7c141b80c84767bdd2f8b54b6fa2603d5881 Signed-off-by: Ajit Pandey --- qcom/tuna.dtsi | 46 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 2a8e2d8a..b3413c74 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -398,8 +398,25 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,tuna-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_0_pipe_clk>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -411,9 +428,10 @@ #reset-cells = <1>; }; - tcsrcc: clock-controller@f100000 { - compatible = "qcom,dummycc"; - clock-output-names = "tcsrcc_clocks"; + tcsrcc: clock-controller@1fbf000 { + compatible = "qcom,tuna-tcsrcc", "syscon"; + reg = <0x1fbf000 0x14>; + reg-name = "cc_base"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -480,32 +498,38 @@ }; &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_0_phy_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_mem_phy_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb3_phy_gdsc { - compatible = "regulator-fixed"; + compatible = "qcom,gdsc"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; From 2bf1b02b657030c49adb2be4ad8eff5cb3349ece Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 17 May 2024 16:52:50 +0530 Subject: [PATCH 03/66] dt-bindings: clock: qcom: add VIDEO/EVA clock controller bindings on tuna Add Video and Eva clock controller bindings on tuna device. Change-Id: If59f876f716ba68a64f6c6b5c5acdf203b3ed472 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,evacc-sun.yaml | 7 +++++-- bindings/clock/qcom,videocc.yaml | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/bindings/clock/qcom,evacc-sun.yaml b/bindings/clock/qcom,evacc-sun.yaml index 73579e42..8c610f17 100644 --- a/bindings/clock/qcom,evacc-sun.yaml +++ b/bindings/clock/qcom,evacc-sun.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/qcom,evacc-sun.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. Eva Clock Controller Binding for SUN +title: Qualcomm Technologies, Inc. Eva Clock Controller for SUN maintainers: - Xubin Bai @@ -14,10 +14,13 @@ description: | See also: - dt-bindings/clock/qcom,evacc-sun.h + - dt-bindings/clock/qcom,evacc-tuna.h properties: compatible: - const: qcom,sun-evacc + enum: + - qcom,sun-evacc + - qcom,tuna-evacc clocks: items: diff --git a/bindings/clock/qcom,videocc.yaml b/bindings/clock/qcom,videocc.yaml index d9f1ad18..a7d51c36 100644 --- a/bindings/clock/qcom,videocc.yaml +++ b/bindings/clock/qcom,videocc.yaml @@ -22,6 +22,7 @@ description: | dt-bindings/clock/qcom,videocc-pineapple.h dt-bindings/clock/qcom,videocc-sun.h dt-bindings/clock/qcom,videocc-parrot.h + dt-bindings/clock/qcom,videocc-tuna.h properties: compatible: @@ -36,6 +37,7 @@ properties: - qcom,sun-videocc - qcom,sun-videocc-v2 - qcom,parrot-videocc + - qcom,tuna-videocc clocks: items: From f57588b209e113e83396fd9bde8a47162f230e09 Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Wed, 10 Apr 2024 11:46:23 +0530 Subject: [PATCH 04/66] ARM: dts: msm: Add QUPv3 UART console node for tuna Enable console support on tuna. Change-Id: I0ece6ae1ba50d94f90404522403c24176c3770e0 Signed-off-by: Prasanna S --- qcom/tuna-pinctrl.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ qcom/tuna-qupv3.dtsi | 33 +++++++++++++++++++++++++++++++++ qcom/tuna-rumi.dtsi | 4 ++++ qcom/tuna.dtsi | 9 ++++++++- 4 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 qcom/tuna-qupv3.dtsi diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi index f0567b81..83a10696 100644 --- a/qcom/tuna-pinctrl.dtsi +++ b/qcom/tuna-pinctrl.dtsi @@ -4,4 +4,44 @@ */ &tlmm { + qupv3_se7_2uart_pins: qupv3_se7_2uart_pins { + qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active { + mux { + pins = "gpio30"; + function = "qup1_se7_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active { + mux { + pins = "gpio31"; + function = "qup1_se7_l3"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; diff --git a/qcom/tuna-qupv3.dtsi b/qcom/tuna-qupv3.dtsi new file mode 100644 index 00000000..f7100943 --- /dev/null +++ b/qcom/tuna-qupv3.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3_1 Wrapper Instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + ranges; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se7_2uart: qcom,qup_uart@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xA9C000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>; + pinctrl-1 = <&qupv3_se7_2uart_sleep>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index d378dc43..7ece493c 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -46,3 +46,7 @@ &disp_rsc { status = "disabled"; }; + +&qupv3_se7_2uart { + qcom,rumi_platform; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 23941f21..b049e46f 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -38,7 +38,9 @@ firmware: firmware {}; - aliases {}; + aliases { + serial0 = &qupv3_se7_2uart; + }; cpus { #address-cells = <2>; @@ -695,3 +697,8 @@ #include "tuna-pinctrl.dtsi" #include "tuna-stub-regulators.dtsi" #include "tuna-usb.dtsi" +#include "tuna-qupv3.dtsi" + +&qupv3_se7_2uart { + status = "ok"; +}; From fb27e2135251682e1187e9b77ba5bb7dc5ca5842 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Thu, 9 May 2024 15:04:19 +0530 Subject: [PATCH 05/66] ARM: dts: msm: Add GLINK PKT loopback node for sun GLINK PKT provides a userspace interface to RPMSG GLINK through character device nodes. Add the loopback node and corresponding channel device to enable GLINK communication from userspace to communicate with loopback test server. Change-Id: I8777564c695c5b5718d5016e79ec09beeb353d90 Signed-off-by: Vishnu Santhosh --- qcom/sun.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 6e2bc13c..d10a0b49 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -618,6 +618,42 @@ qcom,glinkpkt-dev-name = "at_mdm0"; }; + qcom,glinkpkt-ctrl-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp"; + }; + + qcom,glinkpkt-data-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp"; + }; + + qcom,glinkpkt-ctrl-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_lpass"; + }; + + qcom,glinkpkt-data-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_lpass"; + }; + + qcom,glinkpkt-ctrl-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_mpss"; + }; + + qcom,glinkpkt-data-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_mpss"; + }; + qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; From d7483f4aed76ece5f725328b71dabcea2cae9d68 Mon Sep 17 00:00:00 2001 From: Gokul krishna Krishnakumar Date: Fri, 7 Jun 2024 13:47:02 -0700 Subject: [PATCH 06/66] ARM: dts: qcom: Add ready ack to the list of soccp interrupts Add an extra bit in the SOCCP SMP2P to check if the soccp is in D0. Change-Id: I0df3ab9b135e4273d028443cecf8887e7ad794ab Signed-off-by: Gokul krishna Krishnakumar --- qcom/sun.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 51449f47..d16cf590 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3482,14 +3482,16 @@ <&soccp_smp2p_in 1 0>, <&soccp_smp2p_in 3 0>, <&soccp_smp2p_in 2 0>, - <&soccp_smp2p_in 9 0>; + <&soccp_smp2p_in 9 0>, + <&soccp_smp2p_in 10 0>; interrupt-names = "wdog", "fatal", "ready", "stop-ack", "handover", - "pong"; + "pong", + "wake-ack"; /* Outputs to soccp */ qcom,smem-states = <&soccp_smp2p_out 0>, <&soccp_smp2p_out 10>, <&soccp_smp2p_out 9>; From 2f39297be8515ef36ead23864dadc6bf84495a41 Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Fri, 26 Apr 2024 16:05:25 +0530 Subject: [PATCH 07/66] ARM: dts: msm: Add compatible string for cc nodes monaco Add the compatible strings for clk controller nodes in monaco. Change-Id: I2acb4c9520bb217711a75eb8e79fc75ba98e587f Signed-off-by: Prerna Singh --- qcom/monaco.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..01a9a5b2 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1065,13 +1065,13 @@ }; rpmcc: qcom,rpmcc { - /* compatible = "qcom,rpmcc-monaco"; */ + compatible = "qcom,rpmcc-monaco"; #clock-cells = <1>; #reset-cells = <1>; }; gcc: clock-controller@1410000 { - /* compatible = "qcom,monaco-gcc", "syscon"; */ + compatible = "qcom,monaco-gcc", "syscon"; reg = <0x1400000 0x1e0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; @@ -1085,7 +1085,7 @@ }; dispcc: clock-controller@5f00000 { - /* compatible = "qcom,monaco-dispcc", "syscon"; */ + compatible = "qcom,monaco-dispcc", "syscon"; reg = <0x05f00000 0x20000>; reg-names = "cc_base"; clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main", @@ -1098,7 +1098,7 @@ }; gpucc: clock-controller@5990000 { - /* compatible = "qcom,monaco-gpucc", "syscon"; */ + compatible = "qcom,monaco-gpucc", "syscon"; reg = <0x5990000 0x9000>; reg-names = "cc_base"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, @@ -1122,7 +1122,7 @@ }; debugcc: clock-controller@0 { - /* compatible = "qcom,monaco-debugcc"; */ + compatible = "qcom,monaco-debugcc"; qcom,gcc = <&gcc>; qcom,dispcc = <&dispcc>; qcom,gpucc = <&gpucc>; From 96c9f00c8ba8e24e77ea200b0c67dc18dd6f3518 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 6 Jun 2024 14:11:00 +0530 Subject: [PATCH 08/66] ARM: dts: msm: Add UFS ESI CPU mask for sun Add CPUs for each CQ in qcom,esi-affinity-mask. Change-Id: I78dd9b6ffa28aceaeb5feeaec543172c672bb986 Signed-off-by: Manish Pandey --- qcom/sun.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 18647e7a..ed85cf11 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2372,7 +2372,8 @@ qcom,ice-use-hwkm; qcom,prime-mask = <0xc0>; qcom,silver-mask = <0x3f>; - qcom,esi-affinity-mask = <0xe0>; + /* affine cpu for each CQ starting from CQ:0 to CQ:max_cqs */ + qcom,esi-affinity-mask = <4 5 3 4 5 3 7 7>; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ From f085d759f88128c5cdb8cefaeb4a67b52a4b61ad Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Thu, 13 Jun 2024 15:05:58 +0530 Subject: [PATCH 09/66] ARM: dts: msm: enable rpm-smd and mpm device node for Monaco This change adds the compatible string for rpm-smd and mpm device nodes so that rpm-smd and mpm drivers will probe during device boot up. Change-Id: I8816a9e3dd8c9cef39440a1bf912d6d5f06f9f59 Signed-off-by: Raghavendra Kakarla --- qcom/monaco.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..46a5d051 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1716,7 +1716,7 @@ }; rpm_bus: qcom,rpm-smd { - /* compatible = "qcom,rpm-smd"; */ + compatible = "qcom,rpm-smd"; rpm-channel-name = "rpm_requests"; interrupts = ; rpm-channel-type = <15>; /* SMD_APPS_RPM */ @@ -1825,7 +1825,7 @@ }; mpm: interrupt-controller@45f01b8 { - /* compatible = "qcom,mpm-monaco", "qcom,mpm"; */ + compatible = "qcom,mpm-monaco", "qcom,mpm"; interrupts = ; reg = <0x45f01b8 0x1000>, <0xf111008 0x4>, From 33159c610323c391b66b4f9633520af891648991 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 14 Jun 2024 11:10:49 +0530 Subject: [PATCH 10/66] ARM: dts: msm: Add cpucp scmi nodes for ravelin Add nodes to enable scmi communication to cpucp on ravelin. Update tx and rx regname for cpucp. Change-Id: I9674a974e58d8be1eb02063846f5e9e0d1b046c6 Signed-off-by: Swetha Chikkaboraiah --- qcom/ravelin.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 03f7f28e..09b4e06d 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -62,8 +62,8 @@ reg = <0x0 0x17D09100 0x0 0x200>; ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>; - cpu_scp_lpri: scp-shmem@0 { - compatible = "arm,scp-shmem"; + cpu_scmi_lpri: scmi-shmem@0 { + compatible = "arm,scmi-shmem"; reg = <0x0 0x0 0x0 0x200>; }; }; @@ -746,7 +746,7 @@ compatible = "qcom,cpucp"; reg = <0x17400000 0x10>, <0x17d90000 0x2000>; - reg-names = "rx", "tx"; + reg-names = "tx", "rx"; #mbox-cells = <1>; interrupts = ; }; @@ -757,7 +757,7 @@ compatible = "arm,scmi"; mboxes = <&cpucp 0>; mbox-names = "tx"; - shmem = <&cpu_scp_lpri>; + shmem = <&cpu_scmi_lpri>; scmi_pmu: protocol@86 { reg = <0x86>; From db31e6dd0cd4b34c2168dccead6afbc990e6fec0 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 14 Jun 2024 11:55:26 +0530 Subject: [PATCH 11/66] ARM: dts: msm: Remove events specific to SPM feature SPM feature is deprecated from 5.15 kernel. So remove events specific to SPM feature for Ravelin. Change-Id: Idbcbbd6f3736ad19cb1b0ea479809548a020195d Signed-off-by: Swetha Chikkaboraiah --- qcom/ravelin.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 09b4e06d..7719173a 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1444,8 +1444,7 @@ < 0x0008 0xFF 0xFF 0x02 >, < 0x0011 0xFF 0xFF 0x00 >, < 0x0017 0xFF 0xFF 0xFF >, - < 0x002A 0xFF 0xFF 0xFF >, - < 0x4005 0xC0 0xFF 0xFF >; + < 0x002A 0xFF 0xFF 0xFF >; }; ddr_freq_table: ddr-freq-table { @@ -1531,7 +1530,6 @@ qcom_memlat: qcom,memlat { compatible = "qcom,memlat"; - qcom,be-stall-ev = <0x4005>; ddr { compatible = "qcom,memlat-grp"; From e27b15b1517dfa12b6dcb84ee79664e6f63c03f8 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 14 Jun 2024 12:02:31 +0530 Subject: [PATCH 12/66] ARM: dts: msm: Add support for cpufreq cycle counter driver Reuse cpufreq cycle counter register information of parrot for ravelin. Change-Id: Ib17ba9f86da998c49404971f77718a1e9a4d6b03 Signed-off-by: Swetha Chikkaboraiah --- qcom/ravelin.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 7719173a..8b823780 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -351,6 +351,7 @@ #include "ravelin-usb.dtsi" #include "ravelin-coresight.dtsi" #include "ravelin-debug.dtsi" +#include "parrot-walt.dtsi" &reserved_memory { #address-cells = <2>; From 58daad1f6c0b31b4711865bfc990457f4dbcbc48 Mon Sep 17 00:00:00 2001 From: Pradnya Dahiwale Date: Wed, 5 Jun 2024 14:47:10 +0530 Subject: [PATCH 13/66] ARM: dts: msm: dt snabpshot for Monaco SoC Add dt snapshot of cpu level cache from branch msm-5.15.c2 commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute"). Change-Id: Id833a1f0894f29753c0ce08839bf3111b8d57a61 Signed-off-by: Pradnya Dahiwale --- qcom/monaco.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..c7000697 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -54,17 +54,17 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; #cooling-cells = <2>; L2_0: l2-cache { - /* compatible = "arm,arch-cache"; */ - cache-size = <0x80000>; - cache-level = <2>; + compatible = "cache"; + cache-size = <0x80000>; + cache-level = <2>; }; L1_I_0: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_0: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -85,11 +85,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_1: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_1: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -110,11 +110,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_2: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_2: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; @@ -135,11 +135,11 @@ qcom,lmh-dcvs = <&lmh_dcvs0>; L1_I_3: l1-icache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; L1_D_3: l1-dcache { - /* compatible = "arm,arch-cache"; */ + compatible = "cache"; }; }; From 49c9ea7847f2b6e8206cd73c9dae5082d63ade1d Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Thu, 30 May 2024 12:22:19 -0700 Subject: [PATCH 14/66] ARM: dts: msm: Enable scmi_clk protocol to CPUCP on Sun CPUCP exposes certain clocks over SCMI. Enable the clock protocol to handle these. Change-Id: Idfc040e852cb19adae8340f6ceda7f95f52ccb1c Signed-off-by: Mike Tipton --- qcom/sun.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 9e9ccb43..bda4e5e4 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3110,6 +3110,11 @@ #clock-cells = <1>; }; + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + scmi_qcom: protocol@80 { reg = <0x80>; #clock-cells = <1>; From b7766f108e96d3ef3b046a44b5db1e36d03d617b Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Mon, 29 Apr 2024 16:58:27 +0530 Subject: [PATCH 15/66] ARM: dts: msm: enable interconnect devices for Monaco Enable the interconnect devices for cnoc, snoc, bimc, clk_virt, mmnrt_virt and mmrt_virt. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: Iefa87748870578a5472ed08e3692d04a7a81337c Signed-off-by: Raviteja Laggyshetty --- qcom/monaco.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 01a9a5b2..bc5a9e85 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1654,7 +1654,7 @@ }; clk_virt: interconnect { - /* compatible = "qcom,monaco-clk_virt"; */ + compatible = "qcom,monaco-clk_virt"; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, @@ -1662,7 +1662,7 @@ }; mmnrt_virt: interconnect@0 { - /* compatible = "qcom,monaco-mmnrt_virt"; */ + compatible = "qcom,monaco-mmnrt_virt"; #interconnect-cells = <1>; qcom,util-factor = <142>; qcom,keepalive; @@ -1672,7 +1672,7 @@ }; mmrt_virt: interconnect@1 { - /* compatible = "qcom,monaco-mmrt_virt"; */ + compatible = "qcom,monaco-mmrt_virt"; #interconnect-cells = <1>; qcom,util-factor = <142>; qcom,keepalive; @@ -1683,7 +1683,7 @@ system_noc: interconnect@1880000 { reg = <0x01880000 0x5e200>; - /* compatible = "qcom,monaco-system_noc"; */ + compatible = "qcom,monaco-system_noc"; #interconnect-cells = <1>; qcom,keepalive; clock-names = "bus", "bus_a"; @@ -1696,7 +1696,7 @@ config_noc: interconnect@1900000 { reg = <0x01900000 0x1000>; - /* compatible = "qcom,monaco-config_noc"; */ + compatible = "qcom,monaco-config_noc"; #interconnect-cells = <1>; qcom,keepalive; clock-names = "bus", "bus_a"; @@ -1706,7 +1706,7 @@ bimc: interconnect@4480000 { reg = <0x04480000 0x80000>; - /* compatible = "qcom,monaco-bimc"; */ + compatible = "qcom,monaco-bimc"; #interconnect-cells = <1>; qcom,util-factor = <151>; qcom,keepalive; From fcac16f9c78daecca0caa7a985aa0dabcb670570 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 17 Jun 2024 13:25:15 +0800 Subject: [PATCH 16/66] ARM: dts: msm: move scandump_gpu to dynamic memory dump Move scandump_gpu dump entry to dynamic memory dump. Change-Id: I5682b7f335482a84bee0539765f7124a82544161 Signed-off-by: Yuanfang Zhang --- qcom/sun-debug.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/qcom/sun-debug.dtsi b/qcom/sun-debug.dtsi index 1c1a8fb2..0cfada4c 100644 --- a/qcom/sun-debug.dtsi +++ b/qcom/sun-debug.dtsi @@ -734,16 +734,18 @@ qcom,dump-size = <0x40000>; qcom,dump-id = <0x220>; }; - - scandump_gpu { - qcom,dump-size = <0x300000>; - qcom,dump-id = <0x221>; - }; }; dynamic_mem_dump { qcom,dynamic-mem-dump; + scandump_gpu { + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; + }; + cpuss_reg { cpuss_reg { qcom,dump-size = <0xa00000>; From b19eebefbd07c01e50d15259f4efc02a8bdcb8ab Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 13 Jun 2024 17:36:06 +0800 Subject: [PATCH 17/66] dt-bindings: qcom,hv-haptics: add qcom,sw-cmd-freq-detect Add qcom,sw-cmd-freq-detect property to support software command based 2-step LRA resonant frequency detection method. Change-Id: I04ebe79c5f93498bc437605dac8d284e71dad414 Signed-off-by: Fenglin Wu --- bindings/input/qcom,hv-haptics.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/input/qcom,hv-haptics.yaml b/bindings/input/qcom,hv-haptics.yaml index 36a1b19f..70997a88 100644 --- a/bindings/input/qcom,hv-haptics.yaml +++ b/bindings/input/qcom,hv-haptics.yaml @@ -155,6 +155,12 @@ properties: for HAP525_HV haptics module. type: boolean + qcom,sw-cmd-freq-detect: + description: | + Boolean flag indicating that software command based frequency detection + method is used for LRA resonant frequency detection. + type: boolean + patternProperties: ".*hap-swr-slave-reg$": description: | From 0404ac4ac332f036ddb0c7ed11a0544d0bde9959 Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Mon, 17 Jun 2024 14:09:58 +0530 Subject: [PATCH 18/66] ARM: dts: qcom: add device tree for AON Add device tree snapshot for AON from msm-5.15.c2. Snapshot is taken from msm-5.15.c2 kernel commit 95ffcf910eee ("ARM: dts: msm: add aon-rma glink node"). Change-Id: I7f6a2a1c2f5fd04b97f16f5dbace4ce87e88f0b7 Signed-off-by: Koushik Immadisetty --- qcom/slate.dtsi | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) create mode 100644 qcom/slate.dtsi diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi new file mode 100644 index 00000000..40d81ac1 --- /dev/null +++ b/qcom/slate.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&qupv3_se4_spi { /* BLSP4 QUP3*/ + status = "ok"; + qcom,shared_ee; + qcom,slate-spi { + compatible = "qcom,slate-spi"; + reg = <0>; + spi-max-frequency = <40000000>; + interrupt-parent = <&tlmm>; + qcom,irq-gpio = <&tlmm 95 1>; + }; +}; + +&soc { + aon_pas:qcom,rproc-slate { + compatible = "qcom,rproc-slate"; + qcom,firmware-name = "slatefw.mdt"; + /* GPIO inputs from blackghost */ + qcom,slate2ap-status-gpio = <&tlmm 98 0>; + /* GPIO output to blackghost */ + qcom,ap2slate-status-gpio = <&tlmm 97 0>; + }; + + qcom,slate-daemon { + compatible = "qcom,slate-daemon"; + qcom,firmware-name = "slatefw.mdt"; + qcom,rproc-handle = <&aon_pas>; + /* GPIO for external flash */ + qcom,platform-reset-gpio = <&pm5100_gpios 15 0>; + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "rf_clk2"; + status = "ok"; + }; + + glink_slatecom:qcom,glink-slatecom-xprt-slate { + compatible = "qcom,glink-slatecom-xprt"; + label = "slate"; + + qcom,glink-slate-events-bridge { + qcom,glink-channels = "slate-event"; + qcom,intents = <0x0181 1>; + }; + + qcom,glink-slatecom-ctrl { + qcom,glink-channels = "slate-ctrl"; + qcom,intents = <0x0C 1>; + }; + + qcom,glink-slate-ux-ctl { + qcom,glink-channels = "slate-ux-ctl"; + qcom,intents = <0x0C 1>; + }; + + qcom,glink-slate-rma { + qcom,glink-channels = "slate-rma"; + qcom,intents = <0x24 1>; + }; + + qcom,glink-slatecom-qcli { + qcom,glink-channels = "slate-qcli"; + qcom,intents = <0x0C 1>; + status = "ok"; + }; + + qcom,glink-slate-rsb { + qcom,glink-channels = "slate-rsb-ctl"; + qcom,intents = <0x0C 1>; + }; + + qcom,glink-slate-touch { + qcom,glink-channels = "touch-ctrl"; + qcom,intents = <0x0C 1>; + }; + + qcom,glink-slate-dfu { + qcom,glink-channels = "slate-dfu"; + qcom,intents = <0x24 1>; + }; + + qcom,glink-slate-custom-data { + qcom,glink-channels = "slate_custom_data"; + qcom,intents = <0x24 1>; + }; + + qcom,glinkpkt-slate-ssc-hal { + qcom,glink-channels = "ssc_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-sso-hal { + qcom,glink-channels = "sso_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-cam-hal { + qcom,glink-channels = "cam_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-usta { + qcom,glink-channels = "ssc_usta"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-location-ctrl { + qcom,glink-channels = "location_ctrl"; + qcom,intents = <0x1000 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-0 { + qcom,glink-channels = "ssc_test_0"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-1 { + qcom,glink-channels = "ssc_test_1"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-2 { + qcom,glink-channels = "ssc_test_2"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-3 { + qcom,glink-channels = "ssc_test_3"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-4 { + qcom,glink-channels = "ssc_test_4"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-5 { + qcom,glink-channels = "ssc_test_5"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-6 { + qcom,glink-channels = "ssc_test_6"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-7 { + qcom,glink-channels = "ssc_test_7"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-8 { + qcom,glink-channels = "ssc_test_8"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-9 { + qcom,glink-channels = "ssc_test_9"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-10 { + qcom,glink-channels = "ssc_test_10"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-11 { + qcom,glink-channels = "ssc_test_11"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-12 { + qcom,glink-channels = "ssc_test_12"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-13 { + qcom,glink-channels = "ssc_test_13"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-14 { + qcom,glink-channels = "ssc_test_14"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glink-ss-bt-ctrl { + qcom,glink-channels = "ss_bt_ctrl"; + qcom,intents = <0x1000 10>; + }; + + qcom,glink-ss-bt-data { + qcom,glink-channels = "ss_bt_data"; + qcom,intents = <0x1000 10>; + }; + + qcom,glink-ss-bt-le-data { + qcom,glink-channels = "ss_bt_le_data"; + qcom,intents = <0x1000 10>; + }; + + qcom,glink-ss-bt-ssr-data { + qcom,glink-channels = "ss_bt_ssr_data"; + qcom,intents = <0xf2f8 10>; + }; + qcom,glink-ss-bt-obex-data { + qcom,glink-channels = "ss_bt_obex_data"; + qcom,intents = <0x1000 10>; + }; + }; + + qcom,slatecom-rpmsg { + compatible = "qcom,slatecom-rpmsg"; + qcom,glink-channels = "slate-ctrl"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 20>; + }; + + qcom,slate-events-bridge { + compatible = "qcom,slate-events-bridge"; + }; + + qcom,slate-events-bridge-rpmsg { + compatible = "qcom,slate-events-bridge-rpmsg"; + qcom,glink-channels = "slate-event"; + qcom,glinkpkt-edge = "slate"; + }; + + qcom,slate-rsb { + compatible = "qcom,slate-rsb"; + }; + + qcom,slatetouch-rpmsg { + compatible = "qcom,slatetouch-rpmsg"; + qcom,glink-channels = "slate-touch-ctrl"; + qcom,glinkpkt-edge = "slate"; + intents = <0x200 1>; + }; +}; From e726add23ad7b1450d5fedef8756f6673db9bcc7 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Thu, 13 Jun 2024 14:19:05 +0530 Subject: [PATCH 19/66] dt-bindings: pwm-qti-lpg: Add qcom,force-low-pwm-size property Add qcom,force-low-pwm-size property that would indicate the forced use of legacy low PWM sizes (6 or 9 bits) instead of full 8-15 bit PWM sizes. Change-Id: Ic0e2b972bc16871891d81ec20ec0b48d326f6666 Signed-off-by: Shilpa Suresh --- bindings/pwm/qcom,pwm-qti-lpg.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/pwm/qcom,pwm-qti-lpg.yaml b/bindings/pwm/qcom,pwm-qti-lpg.yaml index 53f9904a..e7dd30ab 100644 --- a/bindings/pwm/qcom,pwm-qti-lpg.yaml +++ b/bindings/pwm/qcom,pwm-qti-lpg.yaml @@ -88,6 +88,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array maxItems: 64 + qcom,force-low-pwm-size: + description: | + The flag to indicate the forced use of legacy low PWM sizes + (6 or 9 bits) instead of full 8-15 bit PWM sizes, when the + PWM size is calculated based on the requested PWM period by + the client driver. + type: boolean + required: - compatible - reg From a2fc769fb8c3e33a73ad6451f900bd5aec1b89ce Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Wed, 12 Jun 2024 15:15:03 +0530 Subject: [PATCH 20/66] ARM: dts: msm: Add qcom,force-low-pwm-size prop for parrot pm6450 pwm For backward compatibility for parrot target, add qcom,force-low-pwm-size property to limit setting PWM sizes to 6 and 9 bit modes only, rather than using the full 8 to 15 bit PWM sizes range. Change-Id: Iff15fe61977ad34eed4c0dd75de3f233c08fd681 Signed-off-by: Shilpa Suresh --- qcom/parrot-idp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot-idp.dtsi b/qcom/parrot-idp.dtsi index eca7841f..c88c5770 100644 --- a/qcom/parrot-idp.dtsi +++ b/qcom/parrot-idp.dtsi @@ -31,6 +31,7 @@ &pm6450_pwm_1 { status = "ok"; + qcom,force-low-pwm-size; }; &qupv3_se9_i2c { From acc834e002211adbac53dfd7fb40e52afb49ec8b Mon Sep 17 00:00:00 2001 From: mxing Date: Wed, 24 Apr 2024 14:39:43 +0800 Subject: [PATCH 21/66] ARM: dts: msm: Add SDIO support for monaco This change adds SDIO support for monaco. Change-Id: I1ce969435b01cad2f65de025deea6c545e7adfbf Signed-off-by: mxing --- qcom/monaco-idp-v1-common.dtsi | 28 ++++++++++++ qcom/monaco-pinctrl.dtsi | 84 ++++++++++++++++++++++++++++++++++ qcom/monaco.dtsi | 50 ++++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi index da2cc24c..5566da42 100644 --- a/qcom/monaco-idp-v1-common.dtsi +++ b/qcom/monaco-idp-v1-common.dtsi @@ -24,6 +24,34 @@ qcom,vdd-io-current-level = <0 250000>; }; +&sdhc_3 { + /* device core power supply for sd card*/ + vdd-supply = <&L26A>; + qcom,vdd-voltage-level = <3304000 3304000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply for msm_io*/ + vdd-io-supply = <&L16A>; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-always-on; + qcom,vdd-io-current-level = <200 22000>; + + keep-power-in-suspend; + non-removable; + qcom,core_3_0v_support; + qcom,restore-after-cx-collapse; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc3_clk_on &sdc3_cmd_on &sdc3_data_on>; + pinctrl-1 = <&sdc3_clk_off &sdc3_cmd_off &sdc3_data_off>; + + /* forbid SDR104/SDR50/DDR50 for hi3881 */ + sdhci-caps-mask = <0x7 0x0>; + qcom,devfreq,freq-table = <400000 20000000 25000000 50000000>; + max-frequency = <50000000>; + + status = "disabled"; +}; + &pm5100_sdam_2 { hap_cl_brake: cl_brake@7c { reg = <0x7c 0x1>; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index 870a6d99..78eb2f34 100644 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -1478,6 +1478,90 @@ }; }; + pmx_sdc3_clk { + sdc3_clk_on: sdc3_clk_on { + mux { + pins = "gpio79"; + function = "sdc3_clk"; + }; + + config { + pins = "gpio79"; + drive-strength = <8>; /* 8 MA */ + bias-disable; /* NO pull */ + }; + }; + + sdc3_clk_off: sdc3_clk_off { + mux { + pins = "gpio79"; + function = "sdc3_clk"; + }; + + config { + pins = "gpio79"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc3_cmd { + sdc3_cmd_on: sdc3_cmd_on { + mux { + pins = "gpio78"; + function = "sdc3_cmd"; + }; + + config { + pins = "gpio78"; + bias-pull-up; /* pull up */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + sdc3_cmd_off: sdc3_cmd_off { + mux { + pins = "gpio78"; + function = "sdc3_cmd"; + }; + + config { + pins = "gpio78"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + + pmx_sdc3_data { + sdc3_data_on: sdc3_data_on { + mux { + pins = "gpio74","gpio75","gpio76","gpio77"; + function = "sdc3_data"; + }; + + config { + pins = "gpio74","gpio75","gpio76","gpio77"; + bias-pull-up; /* pull up */ + drive-strength = <8>; /* 8 MA */ + }; + }; + + sdc3_data_off: sdc3_data_off { + mux { + pins = "gpio74","gpio75","gpio76","gpio77"; + function = "sdc3_data"; + }; + + config { + pins = "gpio74","gpio75","gpio76","gpio77"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + }; + pmx_ts_int_active { ts_int_active: ts_int_active { mux { diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..36813c4c 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -26,6 +26,7 @@ aliases { mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc2 = &sdhc_3; /*SDC3 SDIO slot*/ serial0 = &qupv3_se6_2uart; hsuart0 = &qupv3_se5_4uart; i2c1 = &qupv3_se1_i2c; @@ -1824,6 +1825,55 @@ }; }; + sdhc_3: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 3200>, <1600 1600>, + /* 25 MB/s */ + <65360 250000>, <100000 133320>, + /* 50 MB/s */ + <130718 250000>, <133320 133320>, + /* 100 MB/s */ + <261438 250000>, <150000 133320>, + /* 200 MB/s */ + <261438 800000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + + bus-width = <4>; + + iommus = <&apps_smmu 0xA0 0x0>; + qcom,iommu-dma = "bypass"; + + qcom,devfreq,freq-table = <400000 20000000 25000000 50000000>; + + status = "disabled"; + }; + mpm: interrupt-controller@45f01b8 { /* compatible = "qcom,mpm-monaco", "qcom,mpm"; */ interrupts = ; From 1af492361012553eb71a19d850eb5815831df5de Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Jun 2024 10:51:34 +0530 Subject: [PATCH 22/66] dt-bindings: Document optional properties for cluster device Document optional properties. Change-Id: If6ad8199f3d6ac7f35bd3550b997e97bd8612799 Signed-off-by: Maulik Shah --- bindings/arm/msm/qcom,lpm-cluster-dev.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/bindings/arm/msm/qcom,lpm-cluster-dev.yaml b/bindings/arm/msm/qcom,lpm-cluster-dev.yaml index 4bf99b7c..a4f121a6 100644 --- a/bindings/arm/msm/qcom,lpm-cluster-dev.yaml +++ b/bindings/arm/msm/qcom,lpm-cluster-dev.yaml @@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. Low Power Management Cluster Device +maintainers: + - Maulik Shah + description: | The application processor can do a variety of cluster level low power modes. It does so by predicting the low power mode based on latency and residency @@ -21,6 +24,21 @@ properties: power-domains: maxItems: 1 + qcom,pred-prem-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of premature exits cluster device considers for prediction. + + qcom,sample-invalid-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Time after which past samples are invalidated. + + qcom,use-cluster-bias-timer: + type: boolean + description: + Used to determine if bias timer to be setup for cluster + required: - compatible - power-domains From dd6fce7356a2e2b723112a7aff41bcedc3e64b3f Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 18 Jun 2024 10:52:11 +0530 Subject: [PATCH 23/66] ARM: dts: msm: Add optional cluster device properties for sun Add properties like premature count, sample invalid time and whether to use bias timer for cluster device. Change-Id: I487e420ce422766b18d6c86632c521215b0ed484 Signed-off-by: Maulik Shah --- qcom/sun.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 9e9ccb43..35a6f1ee 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1435,16 +1435,23 @@ cluster-device0 { compatible = "qcom,lpm-cluster-dev"; power-domains = <&CLUSTER_PD0>; + qcom,pred-prem-cnt = <2>; + qcom,sample-invalid-time = <40000000>; }; cluster-device1 { compatible = "qcom,lpm-cluster-dev"; power-domains = <&CLUSTER_PD1>; + qcom,pred-prem-cnt = <2>; + qcom,sample-invalid-time = <40000000>; + qcom,use-cluster-bias-timer; }; cluster-device2 { compatible = "qcom,lpm-cluster-dev"; power-domains = <&CLUSTER_PD2>; + qcom,pred-prem-cnt = <2>; + qcom,sample-invalid-time = <40000000>; }; qcom,memshare { From 0cc42eff84359e8d9f21f6dcc746ea9affb22eaf Mon Sep 17 00:00:00 2001 From: Sudeepgoud Patil Date: Mon, 17 Jun 2024 17:05:52 +0530 Subject: [PATCH 24/66] dt-bindings: Add glink slatecom transport binding documentation This commit adds the device tree binding documentation for the GLINK SLATECOM transport(glink_slatecom_xprt). The documentation includes details about the properties, usage and examples of the binding. Change-Id: I12770ac197e1b62ebacf9c0e3445b559b5c1abcf Signed-off-by: Sudeepgoud Patil --- .../soc/qcom/qcom,glink-slatecom-xprt.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 bindings/soc/qcom/qcom,glink-slatecom-xprt.yaml diff --git a/bindings/soc/qcom/qcom,glink-slatecom-xprt.yaml b/bindings/soc/qcom/qcom,glink-slatecom-xprt.yaml new file mode 100644 index 00000000..5d1c752e --- /dev/null +++ b/bindings/soc/qcom/qcom,glink-slatecom-xprt.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,glink-slatecom-xprt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GLINK SLATECOM transport + +maintainers: + - Sudeepgoud Patil + +description: | + This binding describes the Qualcomm Technologies, Inc glink slatecom transport driver, + a slatecom-spi based communication channel for sending data between the various + subsystems in Qualcomm Technologies, Inc platforms. + +properties: + compatible: + const: qcom,glink-slatecom-xprt + description: must be "qcom,glink-slatecom-xprt" + label: + const: slate + description: must be "slate" + +required: + - compatible + - label + +additionalProperties: false + +examples: + - | + qcom,glink-slatecom-xprt-slate { + compatible = "qcom,glink-slatecom-xprt"; + label = "slate"; + }; + + + From 8525c9d775b844a496b350cc29c710b0a2f7a5d8 Mon Sep 17 00:00:00 2001 From: Bikki Srinivasa Rao Date: Tue, 11 Jun 2024 15:32:04 +0530 Subject: [PATCH 25/66] ARM: dts: msm: Enable goodix_ts touch for qrd device Add compatible string for qrd goodix_ts parrot. Change-Id: Ibc8d62f34c386bf9480c82661906a9c5b32b7f67 Signed-off-by: Syed Ahmed Signed-off-by: Bikki Srinivasa Rao --- qcom/parrot-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/parrot-qrd.dtsi b/qcom/parrot-qrd.dtsi index 73866070..657bb210 100644 --- a/qcom/parrot-qrd.dtsi +++ b/qcom/parrot-qrd.dtsi @@ -125,8 +125,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -150,6 +152,8 @@ pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; }; From b6c07f1f9a123f773cc16e18f0ff3caa0d8decf9 Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Mon, 17 Jun 2024 17:07:33 +0530 Subject: [PATCH 26/66] ARM: dts: qcom: Update pmic_glink device compatible string for parrot The downstream pmic_glink driver and compatible string has been renamed to qti_pmic_glink on the qcom-6.6 kernel branch, to avoid conflict with the independent upstream driver. This was handled for the "PMIC_RTR_ADSP_APPS" channel clients (UCSI, Altmode and Battery charger), but got missed for the "PMIC_LOGS_ADSP_APPS" channel clients (battery-debug, charger-ulog and spmi-glink-debug). Fix it. Change-Id: I441aecde368fab411d6df3ae0d8c04b9c3a002f2 Signed-off-by: Shilpa Suresh --- qcom/parrot-pm7250b.dtsi | 2 +- qcom/parrot-pm8350b.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/parrot-pm7250b.dtsi b/qcom/parrot-pm7250b.dtsi index fac8b00d..5f5864bb 100644 --- a/qcom/parrot-pm7250b.dtsi +++ b/qcom/parrot-pm7250b.dtsi @@ -13,7 +13,7 @@ }; qcom,pmic_glink_log { - compatible = "qcom,pmic-glink"; + compatible = "qcom,qti-pmic-glink"; qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; qcom,battery_debug { diff --git a/qcom/parrot-pm8350b.dtsi b/qcom/parrot-pm8350b.dtsi index c685a111..02bdcdee 100644 --- a/qcom/parrot-pm8350b.dtsi +++ b/qcom/parrot-pm8350b.dtsi @@ -22,7 +22,7 @@ }; qcom,pmic_glink_log { - compatible = "qcom,pmic-glink"; + compatible = "qcom,qti-pmic-glink"; qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; qcom,battery_debug { From adcfb108754957df214cafe17ce3de78dbf94b4f Mon Sep 17 00:00:00 2001 From: Amirreza Zarrabi Date: Tue, 18 Jun 2024 02:12:24 -0700 Subject: [PATCH 27/66] ARM: dts: msm: enable memory object extension for Sun OEMVM Add DT entry to enable the memory onject support for si-core. Change-Id: I877fe2e6c9d5f71a2b055428ad942455470b6f9e Signed-off-by: Amirreza Zarrabi --- qcom/sun-oemvm.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 6d78f6cd..2030e5a2 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -304,6 +304,10 @@ compatible = "qcom,smcinvoke"; }; + qcom_mem_object { + compatible = "qcom,mem-object"; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <512>; From 88deeb70fa5f10e6b9a5567868e01b587dcc9a6c Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Fri, 24 May 2024 10:44:05 +0530 Subject: [PATCH 28/66] ARM: dts: msm: Add cmd-db, RSC and PDC devices for kera Add cmd-db, APPS RSC, Display RSC and APSS PDC devices for RPMH communication and wakeup interrupt support. Change-Id: I2b64e3bdd3f609a6c883ffaf7152f85372c177e8 Signed-off-by: Sneh Mankad --- qcom/kera-rumi.dtsi | 4 ++ qcom/kera.dtsi | 89 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 9a0f3db9..3644042e 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -10,3 +10,7 @@ &memtimer { clock-frequency = <500000>; }; + +&disp_rsc { + status = "disabled"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 47451b2e..36397d20 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { model = "Qualcomm Technologies, Inc. Kera"; @@ -275,6 +276,81 @@ }; }; + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + interrupts = , + , + ; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + qcom,tcs-distance = <0x2a0>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x1000>; + reg-names = "drv-0"; + qcom,drv-count = <1>; + interrupts = ; + + disp_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x520>; + qcom,tcs-distance = <0x150>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,kera-pdc", "qcom,pdc"; + reg = <0xb220000 0x10000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, + <10 230 1>, <11 724 1>, <12 716 1>, + <13 727 1>, <14 720 1>, <15 726 1>, + <16 721 1>, <17 262 1>, <18 70 1>, + <19 723 1>, <20 234 1>, <22 725 1>, + <23 231 1>, <24 504 5>, <30 510 8>, + <40 520 6>, <51 531 4>, <58 538 2>, + <61 541 5>, <66 92 1>, <67 547 13>, + <80 240 1>, <81 235 1>, <82 310 2>, + <84 248 1>, <85 241 1>, <86 238 2>, + <88 254 1>, <89 509 1>, <90 563 1>, + <91 259 2>, <93 201 1>, <94 246 1>, + <95 93 1>, <96 611 29>, <125 63 1>, + <126 366 2>, <128 374 1>, <129 377 1>, + <130 428 1>, <131 434 2>, <133 437 1>, + <134 452 2>, <136 458 2>, <138 464 11>, + <149 671 1>, <150 688 1>, <151 714 2>, + <153 722 1>, <154 255 1>, <155 269 2>, + <157 276 1>, <158 287 1>, <159 306 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,kera-tlmm"; reg = <0xf000000 0x1000000>; @@ -283,6 +359,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; }; ipcc_mproc: qcom,ipcc@406000 { @@ -295,4 +372,16 @@ }; }; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; +}; + #include "kera-pinctrl.dtsi" From cefb451115e67f94438b264883f7234500be01cc Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Tue, 18 Jun 2024 16:10:22 +0530 Subject: [PATCH 29/66] ARM: dts: msm: remove of unwanted config Remove unwanted config value for the gpio. Change-Id: Id05eda44034b278cc7e3227a8154876026dedc2b Signed-off-by: Ravulapati Vishnu Vardhan Rao --- qcom/sun-pinctrl.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/sun-pinctrl.dtsi b/qcom/sun-pinctrl.dtsi index 28eeb351..ece6e0b7 100644 --- a/qcom/sun-pinctrl.dtsi +++ b/qcom/sun-pinctrl.dtsi @@ -379,7 +379,6 @@ pins = "gpio127"; drive-strength = <8>; /* 8 mA */ bias-disable; /* NO PULL */ - output-high; }; }; }; @@ -409,7 +408,6 @@ pins = "gpio128"; drive-strength = <8>; /* 8 mA */ bias-disable; /* NO PULL */ - output-high; }; }; }; From f9afc1b4fc26e123dd0cb57cb54005f27fd35dfb Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 4 Jun 2024 15:57:53 +0530 Subject: [PATCH 30/66] ARM: dts: msm: Add USB device nodes for kera Enable USB related properties for USB functionality on kera. Change-Id: Iceb1d404dd7b4f500885064ee0e65cc8a0dc7d7c Signed-off-by: Uttkarsh Aggarwal --- qcom/kera-rumi.dtsi | 28 +++++++++++++++++++++++ qcom/kera-usb.dtsi | 55 +++++++++++++++++++++++++++++++++++++++++++++ qcom/kera.dtsi | 1 + 3 files changed, 84 insertions(+) create mode 100644 qcom/kera-usb.dtsi diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 3644042e..d3592d6b 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -14,3 +14,31 @@ &disp_rsc { status = "disabled"; }; + +&soc { + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000101F0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +}; diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi new file mode 100644 index 00000000..a0a8cc17 --- /dev/null +++ b/qcom/kera-usb.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + interrupts = ; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + }; + }; +}; + diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 878c8077..63587bc6 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -614,3 +614,4 @@ }; #include "kera-pinctrl.dtsi" +#include "kera-usb.dtsi" From 0eaf4bb77ad9a875df59d58391415c1435bd2bdc Mon Sep 17 00:00:00 2001 From: Pradnya Dahiwale Date: Tue, 18 Jun 2024 15:48:20 +0530 Subject: [PATCH 31/66] dt-bindings: Add remoteproc AoN binding documentation This commit adds a device tree binding documentation for the AoN subsystem. The documentation includes details about the properties, usage and examples of the binding. Change-Id: Ic4d4ec8d0ea1fc9b83cc0369fc0df06f6631f329 Signed-off-by: Pradnya Dahiwale --- bindings/remoteproc/qcom,slate.yaml | 45 +++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 bindings/remoteproc/qcom,slate.yaml diff --git a/bindings/remoteproc/qcom,slate.yaml b/bindings/remoteproc/qcom,slate.yaml new file mode 100644 index 00000000..f0361170 --- /dev/null +++ b/bindings/remoteproc/qcom,slate.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,slate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SLATE Peripheral Image Loader + +maintainers: + - Pradnya Dahiwale + +description: + This document defines the binding for a component that loads and boots + firmware on the Qualcomm Technologies, Inc. SLATE core. + +properties: + compatible: + const: qcom,rproc-slate + + qcom,firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the AoN core + + qcom,slate2ap-status-gpio: + description: IRQ used by SLATE to inturrupt MSM. + + qcom,ap2slate-status-gpio: + description: IRQ used by MSM to interrupt SLATE. + +required: + - compatible + +additionalProperties: false + +examples: + - | + aon_pas:qcom,rproc-slate { + compatible = "qcom,rproc-slate"; + qcom,firmware-name = "slatefw.mdt"; + /* GPIO inputs from blackghost */ + qcom,slate2ap-status-gpio = <&tlmm 98 0>; + /* GPIO output to blackghost */ + qcom,ap2slate-status-gpio = <&tlmm 97 0>; + }; + From 977a69fea51fbc85ab486dfc93914b5d40b98ca9 Mon Sep 17 00:00:00 2001 From: Akshay Gola Date: Tue, 18 Jun 2024 14:09:27 +0530 Subject: [PATCH 32/66] ARM: dts: msm: Add glink channel documentation Add glink channel documentation used for communication between monaco and slate. Change-Id: Ie092dfb7da3402a2b821c9cbe0bfa35d2d7af309 Signed-off-by: Akshay Gola --- bindings/soc/qcom/qcom,slate_touch_rpmsg.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 bindings/soc/qcom/qcom,slate_touch_rpmsg.yaml diff --git a/bindings/soc/qcom/qcom,slate_touch_rpmsg.yaml b/bindings/soc/qcom/qcom,slate_touch_rpmsg.yaml new file mode 100644 index 00000000..7abbee5e --- /dev/null +++ b/bindings/soc/qcom/qcom,slate_touch_rpmsg.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,slate_touch_rpmsg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: slatetouch-rpmsg GLINK communication + +maintainers: + - Akshay Gola + +description: | + slatetouch-rpmsg is used to communicate with Slate over Glink + to configure the touch events slatetouch-rpmsg send commands over glink to + send configure, enable/disable touch to Slate + +properties: + compatible: + const: "qcom,slatetouch-rpmsg" + description: must be "qcom,slatetouch-rpmsg" + +required: + - compatible + +additionalProperties: false + +examples: + - | + qcom,slatetouch-rpmsg { + compatible = "qcom,slatetouch-rpmsg"; + }; From d10a36da96d001a682822a8c799d4935c4f4a53d Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Wed, 19 Jun 2024 18:17:23 +0530 Subject: [PATCH 33/66] ARM: dts: msm: add initial memory map for tuna Add initial memory map for tuna, inline with v1. Change-Id: I3699495806141ace22fd236fb75d9fe985d775be Signed-off-by: Bibek Kumar Patro --- qcom/tuna-reserved-memory.dtsi | 234 +++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 18 +++ 2 files changed, 252 insertions(+) create mode 100644 qcom/tuna-reserved-memory.dtsi diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi new file mode 100644 index 00000000..8c9df41b --- /dev/null +++ b/qcom/tuna-reserved-memory.dtsi @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0xe00000>; + }; + + cpusys_vm_mem: cpusys_vm_region@80e00000 { + no-map; + reg = <0x0 0x80e00000 0x0 0x400000>; + }; + + cpucp_pdp_mem: cpucp_region@81200000 { + no-map; + reg = <0x0 0x81200000 0x0 0x200000>; + }; + + /* + * hyp_tags_mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + xbl_dtlog_mem: xbl_dtlog_region@81a00000 { + no-map; + reg = <0x0 0x81a00000 0x0 0x40000>; + }; + + aop_image_mem: aop_image_region@81c00000 { + no-map; + reg = <0x0 0x81c00000 0x0 0x60000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; + + aop_config_mem: aop_config_region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x20000>; + }; + + tme_crash_dump_mem: tme_crash_dump_region@81ca0000 { + no-map; + reg = <0x0 0x81ca0000 0x0 0x40000>; + }; + + tme_log_mem: tme_log_region@81ce0000 { + no-map; + reg = <0x0 0x81ce0000 0x0 0x4000>; + }; + + uefi_log_mem: uefi_log_region@81ce4000 { + no-map; + reg = <0x0 0x81ce4000 0x0 0x10000>; + }; + + smem_mem: smem_region@81d00000 { + no-map; + reg = <0x0 0x81d00000 0x0 0x200000>; + }; + + pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 { + no-map; + reg = <0x0 0x81f00000 0x0 0x100000>; + }; + + cpucp_scandump_mem: cpucp_scandump_region@82000000 { + no-map; + reg = <0x0 0x82000000 0x0 0x380000>; + }; + + adsp_mhi_mem: adsp_mhi_region@82380000 { + no-map; + reg = <0x0 0x82380000 0x0 0x20000>; + }; + + soccp_sdi_mem: soccp_sdi_region@823a0000 { + no-map; + reg = <0x0 0x823a0000 0x0 0x40000>; + }; + + pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 { + no-map; + reg = <0x0 0x823e0000 0x0 0x80000>; + }; + + pvm_fw_mem: pvm_fw_region@824a0000 { + no-map; + reg = <0x0 0x824a0000 0x0 0x100000>; + }; + + hyp_mem_database_mem: hyp_mem_database_region@825a0000 { + no-map; + reg = <0x0 0x825a0000 0x0 0x60000>; + }; + + global_sync_mem: global_sync_region@82600000 { + no-map; + reg = <0x0 0x82600000 0x0 0x100000>; + }; + + tz_stat_mem: tz_stat_region@82700000 { + no-map; + reg = <0x0 0x82700000 0x0 0x100000>; + }; + + dsm_partition_1_mem: dsm_partition_1_region@84a00000 { + no-map; + reg = <0x0 0x84a00000 0x0 0x4900000>; + }; + + dsm_partition_2_mem: dsm_partition_2_region@89300000 { + no-map; + reg = <0x0 0x89300000 0x0 0xa80000>; + }; + + mpss_mem: mpss_region@89e00000 { + no-map; + reg = <0x0 0x89e00000 0x0 0x11200000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 { + no-map; + reg = <0x0 0x9b000000 0x0 0x80000>; + }; + + ipa_fw_mem: ipa_fw_region@9b080000 { + no-map; + reg = <0x0 0x9b080000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@9b090000 { + no-map; + reg = <0x0 0x9b090000 0x0 0xa000>; + }; + + gpu_microcode_mem: gpu_microcode_region@9b09a000 { + no-map; + reg = <0x0 0x9b09a000 0x0 0x2000>; + }; + + camera_mem: camera_region@9b300000 { + no-map; + reg = <0x0 0x9b300000 0x0 0x800000>; + }; + + camera_2_mem: camera_2_region@9bb00000 { + no-map; + reg = <0x0 0x9bb00000 0x0 0x800000>; + }; + + video_mem: video_region@9c300000 { + no-map; + reg = <0x0 0x9c300000 0x0 0x800000>; + }; + + cvp_mem: cvp_region@9cb00000 { + no-map; + reg = <0x0 0x9cb00000 0x0 0x700000>; + }; + + cdsp_mem: cdsp_region@9d200000 { + no-map; + reg = <0x0 0x9d200000 0x0 0x2000000>; + }; + + q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9f200000 { + no-map; + reg = <0x0 0x9f200000 0x0 0x80000>; + }; + + q6_adsp_dtb_mem: q6_adsp_dtb_region@9f280000 { + no-map; + reg = <0x0 0x9f280000 0x0 0x80000>; + }; + + adspslpi_mem: adspslpi_region@9f300000 { + no-map; + reg = <0x0 0x9f300000 0x0 0x4080000>; + }; + + soccp_mem: soccp_region@a3380000 { + no-map; + reg = <0x0 0xa3380000 0x0 0x180000>; + }; + + wpss_mem: wpss_region@a3500000 { + no-map; + reg = <0x0 0xa3500000 0x0 0x1900000>; + }; + + wlan_msa_mem: wlan_msa_region@a6400000 { + no-map; + reg = <0x0 0xa6400000 0x0 0xc00000>; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + xbl_ramdump_mem: xbl_ramdump_region@b8000000 { + no-map; + reg = <0x0 0xb8000000 0x0 0x1c0000>; + }; + + /* merged tz_reserved, xbl_sc, and qtee regions */ + tz_merged_mem: tz_merged_region@d8000000 { + no-map; + reg = <0x0 0xd8000000 0x0 0x600000>; + }; + + /* + * ta/tags mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + llcc_lpi_mem: llcc_lpi_region@ff800000 { + no-map; + reg = <0x0 0xff800000 0x0 0x400000>; + }; + +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index e2d37771..3060024a 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -208,6 +208,24 @@ soc: soc { }; }; +#include "tuna-reserved-memory.dtsi" + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; +}; + &soc { #address-cells = <1>; #size-cells = <1>; From 006a1c7e1328e99401735efb24135571ab9df06d Mon Sep 17 00:00:00 2001 From: Saranya R Date: Fri, 14 Jun 2024 12:26:52 +0530 Subject: [PATCH 34/66] ARM: dts: msm: Add support for debug info for ravelin Reserve debug info region of 4KB for ravelin. Change-Id: I835a579bf334e8865a0135f9c591c2bc5ffb792e Signed-off-by: Saranya R --- qcom/ravelin.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 03f7f28e..3284c3e0 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -373,6 +373,12 @@ no-map; }; + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + va_md_mem: va_md_mem_region { compatible = "shared-dma-pool"; alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; @@ -1930,6 +1936,11 @@ compatible = "qcom,logbuf-vendor-hooks"; }; + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + mini_dump_node { compatible = "qcom,minidump"; status = "ok"; From 97ed2663261c014b289c3303a8ddf1656152e28d Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 17 May 2024 12:22:13 +0530 Subject: [PATCH 35/66] ARM: dts: msm: Add support for VIDEO and EVA clock controllers on TUNA Add support for VIDEO and EVA clock controllers and move corresponding gdsc's from dummy to real on Tuna platform. Change-Id: Ib29a0af9979b461879504749cad0aa95a9d47136 Signed-off-by: Anaadi Mishra --- qcom/tuna.dtsi | 44 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index e2d37771..85334931 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -542,8 +542,19 @@ }; evacc: clock-controller@abf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "evacc_clocks"; + compatible = "qcom,tuna-evacc", "syscon"; + reg = <0xabf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_EVA_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -588,8 +599,19 @@ }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,tuna-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -639,12 +661,15 @@ }; &eva_cc_mvs0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_EVA_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &eva_cc_mvs0c_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_EVA_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; status = "ok"; }; @@ -695,12 +720,15 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &video_cc_mvs0c_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; status = "ok"; }; From 9b63aead5573b2607f044ea0cd4460d53850e89f Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Mon, 6 May 2024 14:07:26 +0530 Subject: [PATCH 36/66] ARM: dts: qcom: Update thermal hal trip config for sun Update thermal hal trip threshold for all thermal hal sensors for sun. Change-Id: I3fa4effcdbece88c45c7f38fb014a09310012906 Signed-off-by: Manaf Meethalavalappu Pallikunhi --- qcom/sun-thermal.dtsi | 62 ++++++++++----------- qcom/sun-tp.dtsi | 124 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+), 31 deletions(-) diff --git a/qcom/sun-thermal.dtsi b/qcom/sun-thermal.dtsi index 3ad8b018..c1c4d9c7 100644 --- a/qcom/sun-thermal.dtsi +++ b/qcom/sun-thermal.dtsi @@ -328,7 +328,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -377,7 +377,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -426,7 +426,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -475,7 +475,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -524,7 +524,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -573,7 +573,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -622,7 +622,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -671,7 +671,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -720,7 +720,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -769,7 +769,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -818,7 +818,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -867,7 +867,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -973,7 +973,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1022,7 +1022,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1071,7 +1071,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1120,7 +1120,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1207,7 +1207,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1232,7 +1232,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1257,7 +1257,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1282,7 +1282,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1307,7 +1307,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1332,7 +1332,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1357,7 +1357,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1433,7 +1433,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1471,7 +1471,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1509,7 +1509,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1547,7 +1547,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1585,7 +1585,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1623,7 +1623,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1661,7 +1661,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; @@ -1699,7 +1699,7 @@ }; thermal-hal-config { - temperature = <135000>; + temperature = <95000>; hysteresis = <5000>; type = "passive"; }; diff --git a/qcom/sun-tp.dtsi b/qcom/sun-tp.dtsi index 327e4d0d..77bff8ca 100644 --- a/qcom/sun-tp.dtsi +++ b/qcom/sun-tp.dtsi @@ -20,6 +20,10 @@ cpu-0-0-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu0-emerg0-cfg { temperature = <118000>; }; @@ -36,6 +40,10 @@ cpu-0-0-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu0-emerg1-cfg { temperature = <118000>; }; @@ -52,6 +60,10 @@ cpu-0-1-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu1-emerg0-cfg { temperature = <118000>; }; @@ -68,6 +80,10 @@ cpu-0-1-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu1-emerg1-cfg { temperature = <118000>; }; @@ -84,6 +100,10 @@ cpu-0-2-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu2-emerg0-cfg { temperature = <118000>; }; @@ -100,6 +120,10 @@ cpu-0-2-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu2-emerg1-cfg { temperature = <118000>; }; @@ -116,6 +140,10 @@ cpu-0-3-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu3-emerg0-cfg { temperature = <118000>; }; @@ -132,6 +160,10 @@ cpu-0-3-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu3-emerg1-cfg { temperature = <118000>; }; @@ -148,6 +180,10 @@ cpu-0-4-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu4-emerg0-cfg { temperature = <118000>; }; @@ -164,6 +200,10 @@ cpu-0-4-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu4-emerg1-cfg { temperature = <118000>; }; @@ -180,6 +220,10 @@ cpu-0-5-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu5-emerg0-cfg { temperature = <118000>; }; @@ -196,6 +240,10 @@ cpu-0-5-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu5-emerg1-cfg { temperature = <118000>; }; @@ -236,6 +284,10 @@ cpu-1-0-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu6-emerg0-cfg { temperature = <118000>; }; @@ -252,6 +304,10 @@ cpu-1-0-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu6-emerg1-cfg { temperature = <118000>; }; @@ -268,6 +324,10 @@ cpu-1-1-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu7-emerg0-cfg { temperature = <118000>; }; @@ -284,6 +344,10 @@ cpu-1-1-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + cpu7-emerg1-cfg { temperature = <118000>; }; @@ -316,6 +380,10 @@ nsphvx-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -324,6 +392,10 @@ nsphvx-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -332,6 +404,10 @@ nsphvx-2 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -340,6 +416,10 @@ nsphmx-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -348,6 +428,10 @@ nsphmx-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -356,6 +440,10 @@ nsphmx-2 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -364,6 +452,10 @@ nsphmx-3 { trips { + thermal-hal-config { + temperature = <105000>; + }; + reset-mon-cfg { temperature = <125000>; }; @@ -392,6 +484,10 @@ gpuss-0 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -404,6 +500,10 @@ gpuss-1 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -416,6 +516,10 @@ gpuss-2 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -428,6 +532,10 @@ gpuss-3 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -440,6 +548,10 @@ gpuss-4 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -452,6 +564,10 @@ gpuss-5 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -464,6 +580,10 @@ gpuss-6 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; @@ -476,6 +596,10 @@ gpuss-7 { trips { + thermal-hal-config { + temperature = <105000>; + }; + tj_cfg { temperature = <105000>; }; From 0c150be3528a4a8dcbe59a2400e8680458d918a7 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Thu, 23 May 2024 19:44:32 +0530 Subject: [PATCH 37/66] dt-bindings: power: supply: Add bindings for smb5 and smblite Add device tree bindings for qpnp-smb5 and qpnp-smblite charger drivers. Change-Id: Ib4a067f4813826a60d6ca63b1220071286e06bca Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Umang Chheda --- bindings/power/supply/qcom/qpnp-smb5.yaml | 696 +++++++++++++++++++ bindings/power/supply/qcom/qpnp-smblite.yaml | 506 ++++++++++++++ 2 files changed, 1202 insertions(+) create mode 100644 bindings/power/supply/qcom/qpnp-smb5.yaml create mode 100644 bindings/power/supply/qcom/qpnp-smblite.yaml diff --git a/bindings/power/supply/qcom/qpnp-smb5.yaml b/bindings/power/supply/qcom/qpnp-smb5.yaml new file mode 100644 index 00000000..d9ee9afc --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-smb5.yaml @@ -0,0 +1,696 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/qpnp-smb5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QPNP-SMB5 Charger + +maintainers: + - Kamal Wadhwa + +description: | + SMB5 Charger is an efficient programmable battery charger capable of charging a + high-capacity lithium-ion battery over micro-USB or USB Type-C ultrafast with + Quick Charge 2.0, Quick Charge 3.0, and USB Power Delivery support. Wireless + charging features full A4WP Rezence 1.2, WPC 1.2, and PMA support. + + Required Node Structure: + SMB5 Charger must be described in two levels of devices nodes. + +properties: + compatible: + enum: + - qcom,pm8150-smb5 + - qcom,pm7250b-smb5 + - qcom,pm6150-smb5 + - qcom,pmi632-smb5 + - qcom,qpnp-smb5 + + "#io-channel-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,sec-charger-config: + description: | + Specify how the secondary chargers are configured. + 0 - No secondary charger. + 1 - Charge Pump SMB1390. + 2 - SMB1355 parallel charger. + 3 - Both Charge Pump and SMB1355. + If the value is not present, 0 is used as default + $ref: /schemas/types.yaml#/definitions/uint32 + + io-channels: + description: From common IIO bindings. Used to specify the ADC channel to get the required data. + + io-channel-names: + description: | + From common IIO binding. Use to specify the name of IIO channel to be obtained. + + qcom,batteryless-platform: + description: | + Boolean flag which indicates that the platform does not have a + battery, and therefore charging should be disabled. In + addition battery properties will be faked such that the device + assumes normal operation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,charger-temp-max: + description: | + Specifies the charger temp REG_H_THRESHOLD for PM8150B in deciDegC. + If the value is not present, use the setting read from the device. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,smb-temp-max: + description: | + Specifies the charger temp REG_H_THRESHOLD for SMB1355 in deciDegC. + If the value is not present, use the setting read from the device. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fcc-max-ua: + description: | + Specifies the maximum fast charge current in micro-amps. + If the value is not present, 1Amp is used as default. + default: 1000000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fv-max-uv: + description: | + Specifies the maximum float voltage in micro-volts. + If the value is not present, 4.35V is used as default. + default: 4350000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,usb-icl-ua: + description: | + Specifies the USB input current limit in micro-amps. + If the value is not present, 1.5Amps is used as default. + default: 1500000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,usb-ocl-ua: + description: | + Specifies the OTG output current limit in micro-amps. + If the value is not present, 1.5Amps is used as default + default: 1500000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dc-icl-ua: + description: | + Specifies the DC input current limit in micro-amps. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,boost-threshold-ua: + description: | + Specifies the boost current threshold in micro-amps. + If the value is not present, 100mA is used as default. + default: 100000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,thermal-mitigation: + description: | + Array of fast charge current limit values for + different system thermal mitigation levels. + This should be a flat array that denotes the + maximum charge current in mA for each thermal + level. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,float-option: + description: | + Configures how the charger behaves when a float charger is + detected by APSD. + 1 - Treat as a DCP. + 2 - Treat as a SDP. + 3 - Disable charging. + 4 - Suspend USB input. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hvdcp-disable: + description: | + Specifies if hvdcp charging is to be enabled or not. + If this property is not specified hvdcp will be enabled. + If this property is specified, hvdcp 2.0 detection will still + happen but the adapter won't be asked to switch to a higher + voltage point. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,chg-inhibit-threshold-mv: + description: | + Charge inhibit threshold in milli-volts. Charging will be + inhibited when the battery voltage is within this threshold + from Vfloat at charger insertion. If this is not specified + then charge inhibit will be disabled by default. + Allowed values are: 50, 100, 200, 300. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-src: + description: | + Specify either the ADC or analog comparators to be used in order + to set threshold values for charge termination current. + 0 - Unspecified + 1 - Select ADC comparator + 2 - Select ANALOG comparator + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-current-ma: + description: | + When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired upper threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-base-current-ma: + description: | + When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired lower threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,auto-recharge-soc: + description: | + Specifies the SOC threshold at which the charger will + restart charging after termination. The value specified + ranges from 0 - 100. The feature is enabled if this + property is specified with a valid SOC value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,auto-recharge-vbat-mv: + description: | + Specifies the battery voltage threshold at which the charger + will restart charging after termination. The value specified + is in milli-volts. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,suspend-input-on-debug-batt: + description: | + Boolean flag which when present enables input suspend for + debug battery. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,fake-chg-status-on-debug-batt: + description: | + Boolean flag which when present shows charging status as + unknown for debug battery. This needs to be specified only if + the device needs to be kept powered on always with + "svc power stayon true". + $ref: /schemas/types.yaml#/definitions/flag + + qcom,min-freq-khz: + description: | + Specifies the minimum charger buck/boost switching frequency + in KHz. It overrides the min frequency defined for the charger + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,max-freq-khz: + description: | + Specifies the maximum charger buck/boost switching frequency in + KHz. It overrides the max frequency defined for the charger. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,otg-deglitch-time-ms: + description: | + Specifies the deglitch interval for OTG detection. + If the value is not present, 50 msec is used as default. + default: 50 + + qcom,step-charging-enable: + description: | + Boolean flag which when present enables step-charging. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,typec-legacy-rp-icl: + description: | + Boolean property to enable setting ICL based on Rp for + Type-C non-compliant legacy cables. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,wd-bark-time-secs: + description: | + WD bark-timeout in seconds. The possible values are + 16, 32, 64, 128. If not defined it defaults to 64. + default: 64 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sw-jeita-enable: + description: | + Boolean flag which when present enables sw compensation for + jeita. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,flash-derating-soc: + description: | + SOC threshold in percentage below which hardware will start + derating flash. This is only applicable to certain PMICs like + PMI632 which has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,flash-disable-soc: + description: | + SOC threshold in percentage below which hardware will disable + flash. This is only applicable to certain PMICs like PMI632 + which has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,headroom-mode: + description: | + Specifies flash hardware headroom management policy. The + possible values are: + <0>: Fixed mode, constant 5V at flash input. + <1>: Adaptive mode allows charger output voltage to be + dynamically controlled by the flash module based on the + required flash headroom. + This is only applicable to certain PMICs like PMI632 which + has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fcc-stepping-enable: + description: | + Boolean flag which when present enables stepwise change in FCC. + The default stepping rate is 100mA/sec. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,disable-suspend-on-collapse: + description: | + Boolean flag which when present disables suspend on collapse + feature of charger hardware. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,uusb-moisture-protection-enable: + description: | + Boolean flag which when present enables mositure protection + feature for uUSB connector type. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,hvdcp-autonomous-enable: + description: | + Boolean flag which when present enables hardware-controlled + operation of HVDCP. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,usb-pd-disable: + description: | + Boolean flag which when present disables USB-PD operation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,lpd-disable: + description: | + Boolean flag which when present disables liquid presence + detection. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,hw-die-temp-mitigation: + description: | + Boolean flag which when present enables h/w based thermal + mitigation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,hw-connector-mitigation: + description: | + Boolean flag which when present enables h/w based + connector temperature mitigation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,hw-skin-temp-mitigation: + description: | + Boolean flag which when present enables h/w based skin + temperature mitigation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,en-skin-therm-mitigation: + description: | + Boolean flag which when present enables skin + thermal mitigation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,connector-internal-pull-kohm: + description: | + Specifies internal pull-up configuration to be applied to + connector THERM. The only valid values are (0/30/100/400). + If not specified 100K is used as default pull-up. + default: 100 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,smb-internal-pull-kohm: + description: | + Specifies internal pull-up configuration to be applied to + connector THERM, only valid values are (0/30/100/400). + If not specified 100K is used as default pull-up. + default: 100 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,wd-snarl-time-config: + description: | + WDOG snarl timeout configuration value. The possible values are + 0 to 7, where 0 = 62.5ms, 1 = 125ms, 2 = 250ms, 3 = 500ms, + 4 = 1s, 5 = 2s, 6 = 4s and 7 = 8s. If not defined, wdog-snarl + irq is disabled by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,adc-based-aicl: + description: | + Boolean flag which when present enables ADC based AICL. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,wls-current-max-ua: + description: | + Upper limit of charging current supplied by the wireless charger. + If left unspecified, the HW min value of 1.5 A is applied by + default. + default: 1500000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fcc-step-delay-ms: + description: | + Specifies the delay between each step of FCC stepper algorithm. + If left unspecified, the default value is 1 Sec. + default: 1000 + + qcom,fcc-step-size-ua: + description: | + Specifies the step size of each step of FCC stepper algorithm. + If left unspecified, the default value is 100mA. + default: 100000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hvdcp2-max-icl-ua: + description: | + Specifies the maximum input current limit that can be configured + for HVDCP2 adapter. + If left unspecified, the default value is 3000mA. + default: 3000000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hvdcp3-max-icl-ua: + description: | + Specifies the maximum input current limit that can be configured + for HVDCP3 adapter. + If left unspecified, the default value is 3000mA. + default: 3000000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hvdcp3-standalone-config: + description: | + Boolean flag which when present indicates that the charging is + only done by the main charger (standalone, no CP) with a QC 3.0 + adapter. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,disable-fcc-restriction: + description: | + Boolean flag which when present disables FCC restriction. + $ref: /schemas/types.yaml#/definitions/flag + +additionalProperties: false + +required: + - compatible + +patternProperties: + "^qcom,chgr@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + maxItems: 1 + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,otg@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,bat-if@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,usb-chgpth@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,dc-chgpth@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,chgr-misc@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,schgm-flash@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + additionalProperties: false + + required: + - reg + - interrupts + - interrupt-names + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pm8150b_charger { + compatible = "qcom,qpnp-smb5"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = <0x2 0x10 0x0 0>, + <0x2 0x10 0x1 0>, + <0x2 0x10 0x2 0>, + <0x2 0x10 0x3 0>, + <0x2 0x10 0x4 0>; + + interrupt-names = "chg-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-request"; + }; + + qcom,otg@1100 { + reg = <0x1100>; + interrupts = <0x2 0x11 0x0 0>, + <0x2 0x11 0x1 0>, + <0x2 0x11 0x2 0>, + <0x2 0x11 0x3 0>; + + interrupt-names = "otg-fail", + "otg-overcurrent", + "otg-oc-dis-sw-sts", + "testmode-change-detect"; + }; + + qcom,bat-if@1200 { + reg = <0x1200>; + interrupts = <0x2 0x12 0x0 0>, + <0x2 0x12 0x1 0>, + <0x2 0x12 0x2 0>, + <0x2 0x12 0x3 0>, + <0x2 0x12 0x4 0>, + <0x2 0x12 0x5 0>; + + interrupt-names = "bat-temp", + "bat-ocp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300>; + interrupts = <0x2 0x13 0x0 0>, + <0x2 0x13 0x1 0>, + <0x2 0x13 0x2 0>, + <0x2 0x13 0x3 0>, + <0x2 0x13 0x4 0>, + <0x2 0x13 0x5 0>, + <0x2 0x13 0x6 0>, + <0x2 0x13 0x7 0>; + + interrupt-names = "usbin-collapse", + "usbin-lt-3p6v", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-src-change", + "usbin-icl-change", + "type-c-change"; + }; + + qcom,dc-chgpth@1400 { + reg = <0x1400>; + interrupts = <0x2 0x14 0x0 0>, + <0x2 0x14 0x1 0>, + <0x2 0x14 0x2 0>, + <0x2 0x14 0x3 0>, + <0x2 0x14 0x4 0>, + <0x2 0x14 0x5 0>, + <0x2 0x14 0x6 0>; + + interrupt-names = "dcin-collapse", + "dcin-lt-3p6v", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "div2-en-dg", + "dcin-icl-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x2 0x16 0x0 0>, + <0x2 0x16 0x1 0>, + <0x2 0x16 0x2 0>, + <0x2 0x16 0x3 0>, + <0x2 0x16 0x4 0>, + <0x2 0x16 0x5 0>, + <0x2 0x16 0x6 0>, + <0x2 0x16 0x7 0>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "high-duty-cycle", + "input-current-limiting", + "temperature-change", + "switcher-power-ok"; + }; + + qcom,schgm-flash@a600 { + reg = <0xa600>; + interrupts = <0x2 0xa6 0x0 0>, + <0x2 0xa6 0x1 0>, + <0x2 0xa6 0x2 0>, + <0x2 0xa6 0x3 0>, + <0x2 0xa6 0x4 0>, + <0x2 0xa6 0x5 0>, + <0x2 0xa6 0x6 0>, + <0x2 0xa6 0x7 0>; + + interrupt-names = "flash-en", + "torch-req", + "flash-state-change", + "vout-up", + "vout-down", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + }; +... diff --git a/bindings/power/supply/qcom/qpnp-smblite.yaml b/bindings/power/supply/qcom/qpnp-smblite.yaml new file mode 100644 index 00000000..57dd4201 --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-smblite.yaml @@ -0,0 +1,506 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/qpnp-smblite.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SMBLITE Charger. + +maintainers: + - Kamal Wadhwa + +description: | + SMBLITE Charger is an efficient programmable battery charger capable of charging a + lithium-ion battery over micro-USB or USB Type-C. + + Required Node Structure: + SMBLITE Charger must be described in two levels of devices nodes. + +properties: + compatible: + enum: + - qcom,qpnp-smblite + - qcom,qpnp-pm5100-smblite + + qcom,pmic-revid: + description: | + Should specify the phandle of PMI's revid module. This is used to + identify the PMI subtype. + $ref: /schemas/types.yaml#/definitions/uint32 + + "#io-channel-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + io-channels: + description: Phandle of IIO channels required. + + io-channel-names: + description: | + For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt + + qcom,batteryless-platform: + description: | + Boolean flag which indicates that the platform does not have a + battery, and therefore charging should be disabled. In + addition battery properties will be faked such that the device + assumes normal operation. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,fcc-max-ua: + description: | + Specifies the maximum fast charge current in micro-amps in + battery profile.If the value is not present, 1Amp is used as default. + default: 1000000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fv-max-uv: + description: | + Specifies the maximum float voltage in micro-volts in + battery profile.If the value is not present, 4.35V is used as default. + default: 4350000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,usb-icl-ua: + description: | + Specifies the USB input current limit in micro-amps. + If the value is not present, 1.5Amps is used as default. + default: 1500000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,thermal-mitigation: + description: | + Array of fast charge current limit values for + different system thermal mitigation levels. + This should be a flat array that denotes the + maximum charge current in mA for each thermal + level. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,chg-inhibit-threshold-mv: + description: | + Charge inhibit threshold in milli-volts. Charging will be + inhibited when the battery voltage is within this threshold + from Vfloat at charger insertion. If this is not specified + then charge inhibit will be disabled by default. + Allowed values are: 50, 100, 200, 300. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-src: + description: | + Specify either the ADC or analog comparators to be used in order + to set threshold values for charge termination current. + 0 - Unspecified + 1 - Select ADC comparator + 2 - Select ANALOG comparator + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-current-ma: + description: | + When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired upper threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,chg-term-base-current-ma: + description: | + When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired lower threshold. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,auto-recharge-soc: + description: | + Specifies the SOC threshold at which the charger will + restart charging after termination. The value specified + ranges from 0 - 100. The feature is enabled if this + property is specified with a valid SOC value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,auto-recharge-vbat-mv: + description: | + Specifies the battery voltage threshold at which the charger + will restart charging after termination. The value specified + is in milli-volts. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,suspend-input-on-debug-batt: + description: | + Boolean flag which when present enables input suspend for + debug battery. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,fake-chg-status-on-debug-batt: + description: | + Boolean flag which when present shows charging status as + unknown for debug battery. This needs to be specified only if + the device needs to be kept powered on always with + "svc power stayon true". + $ref: /schemas/types.yaml#/definitions/flag + + qcom,typec-legacy-rp-icl: + description: | + Boolean property to enable setting ICL based on Rp for + Type-C non-compliant legacy cables. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,wd-bark-time-secs: + description: | + WD bark-timeout in seconds. The possible values are + 16, 32, 64, 128. If not defined it defaults to 64. + default: 64 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,battery-data: + description: | + Specifies the phandle of the node which contains the battery + profiles supported on the device. + + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,flash-derating-soc: + description: | + SOC threshold in percentage below which hardware will start + derating flash. This is only applicable to certain PMICs like + PMI632 which has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,flash-disable-soc: + description: | + SOC threshold in percentage below which hardware will disable + flash. This is only applicable to certain PMICs like PMI632 + which has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,headroom-mode: + description: | + Specifies flash hardware headroom management policy. + The possible values are: + <0>: Fixed mode, constant 5V at flash input. + <1>: Adaptive mode allows charger output voltage to be + dynamically controlled by the flash module based on the + required flash headroom. + This is only applicable to certain PMICs like PMI632 which + has SCHGM_FLASH peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvmem-cell-names: + description: | + The nvmem cell device name of the SDAM register used to store + the charger debug mask. It must be "charger_debug_mask". + $ref: /schemas/types.yaml#/definitions/string + + nvmem-cells: + description: | + Phandle of the nvmem cell device used to store the charger debug + mask. Please refer to nvmem bindings as described in + bindings/nvmem/nvmem.txt. + + qcom,fcc-stepping-enable: + description: | + Boolean flag which when present enables stepwise change in FCC. + The default stepping rate is 100mA/sec. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,disable-suspend-on-collapse: + description: | + Boolean flag which when present disables suspend on collapse + feature of charger hardware. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,fcc-step-delay-ms: + description: | + Specifies the delay between each step of FCC stepper algorithm. + If left unspecified, the default value is 1 Sec. + default: 1000 + + qcom,fcc-step-size-ua: + description: | + Specifies the step size of each step of FCC stepper algorithm. + If left unspecified, the default value is 100mA. + default: 100000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,fc-step-start-ua: + description: | + Specifies the initial current of FCC stepper algorithm. + If left unspecified, the default value is 500mA. + default: 500000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,concurrency-mode-enable: + description: | + Boolean flag to control charger concurrency mode. Its supported + only on PM5100, By default this feature is disabled. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,remote-fg: + description: | + Boolean flag to determine if FG is running on different processor. + Its supported only on PM5100, By default this feature is disabled. + $ref: /schemas/types.yaml#/definitions/flag + + qcom,float-option: + description: | + Configures how the charger behaves when a float charger is + detected by APSD. + 1 - Treat as a DCP. + 2 - Treat as a SDP. + 3 - Disable charging. + 4 - Suspend USB input. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,uusb-ss-mode-extcon-enable: + description: | + Boolean flag to support board designs with Micro-AB 3.0 USB port. + If this is enabled, on USB plugin event SS mode extcon notification + is sent (instead of an HS mode). This DT property should be defined + only if the board is not expected to support Micro-B type USB cable + on the Micro-AB 3.0 port, as the Micro-B cable cannot support SS mode. + By default this feature is disabled. + $ref: /schemas/types.yaml#/definitions/flag + +additionalProperties: false + +required: + - compatible + +patternProperties: + "^qcom,chgr@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,dcdc@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,batif@[0-9a-f].*$": + type: object + description: regulator client voting interface node(s). + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,usb@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,typec@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + + "^qcom,misc@[0-9a-f].*$": + type: object + + properties: + reg: + description: Address and size of the peripheral's register block. + + interrupts: + description: Peripheral interrupt specifier. + + interrupt-names: + description: | + Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + + required: + - reg + - interrupts + - interrupt-names + +examples: + - | + #include + pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,dcdc@1100 { + reg = <0x1100>; + interrupts = + <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-fault", + "skip-mode", + "input-current-limiting", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; + }; +... From b6d95239152517aa60f9a48befd572199aff5b06 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Tue, 28 May 2024 14:29:04 +0530 Subject: [PATCH 38/66] dt-bindings: power: supply: Add DT bindings for QBG Add device tree bindings for QBG driver. Change-Id: Ibef732b3fbefc4e52348277a0c2e0577a437fd87 Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Umang Chheda --- bindings/power/supply/qcom/qcom-qbg.yaml | 125 +++++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 bindings/power/supply/qcom/qcom-qbg.yaml diff --git a/bindings/power/supply/qcom/qcom-qbg.yaml b/bindings/power/supply/qcom/qcom-qbg.yaml new file mode 100644 index 00000000..13ce9e2c --- /dev/null +++ b/bindings/power/supply/qcom/qcom-qbg.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/qcom/qcom-qbg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Battery Gauge (QBG) + +maintainers: + - Kamal Wadhwa + +description: | + Qualcomm Technologies, Inc. Battery Gauge (QBG) uses the periodic samples of + battery voltage and current to determine the battery state-of-charge (SOC) + and supports other battery management features. + +properties: + compatible: + const: qcom,qbg + + reg: + description: Base address of QBG MAIN peripheral. + maxItems: 1 + + interrupts: + description: Specifies the interrupts for nvmem devices used by QBG. + maxItems: 1 + + interrupt-names: + description: Specifies the interrupt names for nvmem devices used by QBG. + items: + - const: qbg-sdam + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,num-data-sdams: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of SDAMs used for storing QBG FIFO data. + + qcom,sdam-base: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Base address of QBG SDAM peripheral. + + qcom,vbat-cutoff-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The battery voltage threshold (in mV) at which the battery + power cuts off. The SOC is forced to 0 when battery voltage reaches + this value. + default: 3100 + + qcom,ibat-cutoff-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The battery current threshold (in mA) at which the battery + power cuts off. The SOC is forced to 0 when battery current reaches + this value. + default: 150 + + qcom,vph-min-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Minimum sustainable system power (in mV). + default: 2700 + + qcom,iterm-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The battery current (in mA) at which the QBG algorithm + converges the SOC to 100% during charging and can be used to terminate + charging. + default: 100 + + qcom,rconn-mohm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Resistance of the battery connector in mOhms. + default: 0 + + qcom,vbatt-empty-threshold-mv: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Vbatt empty threshold in mv at which QBG generates low Vbatt + interrupt. + default: 0 + + nvmem-cell-names: + items: + - const: qbg_debug_mask_low + - const: qbg_debug_mask_high + - const: skip_esr_state + + nvmem-cells: + description: | + Use nvmem cell device to indicate SDAM register. + qbg_debug_mask_low/qbg_debug_mask_high used to store the qbg debug mask + qbg_debug_mask_low/qbg_debug_mask_high not used then will not write or + read qbg debug mask. + skip_esr_state used to get GPS de-modulating status. + skip_esr_state not used will not get GPS de-modulating status and + will not enter esr state. + + maxItems: 3 + +required: + - compatible + - reg + - interrupt-names + - interrupts + - qcom,num-data-sdams + - qcom,sdam-base + +additionalProperties: False + +examples: + - | + #include + qcom,pm5100@0 { + #address-cells = <1>; + #size-cells = <0>; + + qbg@4f00 { + compatible = "qcom,qbg"; + reg = <0x4f00>; + interrupt-names = "qbg-sdam"; + interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>; + qcom,num-data-sdams = <6>; + qcom,sdam-base = <0x7600>; + }; + }; +... From f129a43983e9a5a6a6f82daefee333b291630560 Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Mon, 24 Jun 2024 11:58:50 +0530 Subject: [PATCH 39/66] ARM: dts: msm: Ignore dependencies on children by PM framework on parrot Added new dtsi flag 'qcom,suspend-ignore-children', to ignore dependencies on children by runtime PM framework, this helps to exit quickly from msm_geni_serial_runtime_suspend and save power. Change-Id: Ib048c96952871e39286b3a4ce660e39d7cfa5465 Signed-off-by: Prasanna S --- qcom/parrot-qupv3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi index ad42a88c..024a5083 100644 --- a/qcom/parrot-qupv3.dtsi +++ b/qcom/parrot-qupv3.dtsi @@ -584,6 +584,7 @@ pinctrl-3 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>, <&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>; qcom,wakeup-byte = <0xFD>; + qcom,suspend-ignore-children; status = "disabled"; }; }; From 67de48cb3809c45ed1a4415c461fc7d456a2d74c Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 17 Jun 2024 18:43:06 +0800 Subject: [PATCH 40/66] ARM: dts: msm: add CPUCP debug clocks for related components Add CPCP debug clocks for CPUCP related components on sun. Change-Id: I4fa4f8deed3473b7c7ec94f32f568cebf2241a76 Signed-off-by: Yuanfang Zhang --- qcom/sun-coresight.dtsi | 212 +++++++++++++++++++++++++++------------- 1 file changed, 144 insertions(+), 68 deletions(-) diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi index b2f8f0c5..6f0233e8 100644 --- a/qcom/sun-coresight.dtsi +++ b/qcom/sun-coresight.dtsi @@ -1762,8 +1762,10 @@ coresight-name = "coresight-tpdm-llm-lmh0"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1783,8 +1785,10 @@ coresight-name = "coresight-tpdm-llm-lmh1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1804,8 +1808,10 @@ coresight-name = "coresight-tpdm-ext-dsb0"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1825,8 +1831,10 @@ coresight-name = "coresight-tpdm-ext-dsb1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1846,8 +1854,10 @@ coresight-name = "coresight-tpdm-ext-dsb2"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1867,8 +1877,10 @@ coresight-name = "coresight-tpdm-ext-dsb3"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1888,8 +1900,10 @@ coresight-name = "coresight-tpdm-ext-dsb4"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1909,8 +1923,10 @@ coresight-name = "coresight-tpdm-ext_cmb0"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1930,8 +1946,10 @@ coresight-name = "coresight-tpdm-ext_cmb1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1951,8 +1969,10 @@ coresight-name = "coresight-tpdm-ext_cmb2"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1972,8 +1992,10 @@ coresight-name = "coresight-tpdm-ext_cmb3"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -1993,8 +2015,10 @@ coresight-name = "coresight-tpdm-int-cmb"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; out-ports { port { @@ -2028,8 +2052,10 @@ <10 64>, <11 64>; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; in-ports { #address-cells = <1>; @@ -2222,8 +2248,10 @@ qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2328,8 +2356,11 @@ coresight-name = "coresight-replicator-etr1_ncc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2434,8 +2465,11 @@ coresight-name = "coresight-replicator-etr2_ncc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2540,8 +2574,11 @@ coresight-name = "coresight-replicator-etr3_ncc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2646,8 +2683,11 @@ coresight-name = "coresight-replicator-etr4_ncc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2752,8 +2792,11 @@ coresight-name = "coresight-replicator-etr5_ncc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2787,8 +2830,10 @@ coresight-name = "coresight-funnel-ncc0_lv1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2879,8 +2924,10 @@ coresight-name = "coresight-tmc-etf-uc0"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2911,8 +2958,11 @@ coresight-name = "coresight-replicator-uc0"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2946,8 +2996,10 @@ coresight-name = "coresight-funnel-ncc0_lv2"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -2989,8 +3041,10 @@ coresight-name = "coresight-tmc-etf_ncc0"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD0>; in-ports { @@ -3091,8 +3145,11 @@ coresight-name = "coresight-replicator-etr0_ncc1"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3197,8 +3254,10 @@ coresight-name = "coresight-replicator-etr1_ncc1"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3232,8 +3291,10 @@ coresight-name = "coresight-funnel-ncc1_lv1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3292,8 +3353,10 @@ coresight-name = "coresight-tmc-etf-uc1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3324,8 +3387,11 @@ coresight-name = "coresight-replicator-uc1"; qcom,replicator-loses-context; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3359,8 +3425,10 @@ coresight-name = "coresight-funnel-ncc1_lv2"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3402,8 +3470,10 @@ coresight-name = "coresight-tmc-etf_ncc1"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; power-domains = <&CLUSTER_PD1>; in-ports { @@ -3433,8 +3503,10 @@ coresight-name = "coresight-funnel-apss"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; in-ports { #address-cells = <1>; @@ -5552,8 +5624,10 @@ coresight-name = "coresight-cti-apss_cti"; qcom,extended_cti; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; }; cti@12195000 { @@ -5564,8 +5638,10 @@ coresight-name = "coresight-cti-apss_dl"; qcom,extended_cti; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "dynamic_clk"; }; cti@10a05000 { From 5670369edcee315cfcbe7a8804322d97bd5aeda0 Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Mon, 24 Jun 2024 15:49:20 +0530 Subject: [PATCH 41/66] ARM: dts: qcom: Add AON device tree to monaco Include AON device tree file to monaco. Change-Id: Idcf6ea6be47fc25f528daf0b412c051ce6317599 Signed-off-by: Koushik Immadisetty --- qcom/monaco-idp-v1.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index dbeb9032..a6d13d73 100644 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "slate.dtsi" &pm5100_charger { qcom,remote-fg; From 43df192f51bb310561204063dcb07b733151a33a Mon Sep 17 00:00:00 2001 From: Koushik Immadisetty Date: Mon, 24 Jun 2024 19:02:42 +0530 Subject: [PATCH 42/66] ARM: dts: msm: add aon-custom-data glink node Add aon-custom-data glink channel to download misc data firmware to aon. Change-Id: Id88488ed290d37cb3a5082c3f05125aee60ff78b Signed-off-by: Koushik Immadisetty --- qcom/monaco.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 6f631075..4c15563a 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1560,6 +1560,13 @@ qcom,glinkpkt-ch-name = "slate-dfu"; qcom,glinkpkt-dev-name = "glink_pkt_slate_dfu"; }; + + qcom,glinkpkt-slate-custom-data { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "slate_custom_data"; + qcom,glinkpkt-dev-name = "glink_pkt_slate_custom_data"; + }; + qcom,glinkpkt-ss-bt-ctrl { qcom,glinkpkt-edge = "slate"; qcom,glinkpkt-ch-name = "ss_bt_ctrl"; From 8e4ec07539dc4a3349cbdc16fdebfd529a5d30e0 Mon Sep 17 00:00:00 2001 From: kamasali Satyanarayan Date: Wed, 17 Apr 2024 12:41:12 +0530 Subject: [PATCH 43/66] ARM: dts: msm: Remove coherent and voltage-level property in Ravelin Ravelin target doesn't support IO coherency. So, remove the coherent property from storage nodes. Don't vote for voltage for regulators shared between eMMC and UFS to be in consistent with UFS design where regulator-min-microvolt and regulator-max-microvolt properties are removed from regulator device tree files for UFS regulators and to avoid below regulator API failures. [3.198613] pm6450_l24: unsupportable voltage range: 2960000-0uV [4.236846] sdhci_msm_vreg_set_voltage: regulator_set_voltage(vdd)failed. min_uV=2960000,max_uV=2960000,ret=-22. Change-Id: I780218b0903887e36589704af3e790a710932dd7 Signed-off-by: kamasali Satyanarayan --- qcom/ravelin-atp.dtsi | 1 - qcom/ravelin-idp.dtsi | 1 - qcom/ravelin-qrd.dtsi | 1 - qcom/ravelin-rumi.dtsi | 1 - qcom/ravelin.dtsi | 23 ++++++++++------------- 5 files changed, 10 insertions(+), 17 deletions(-) diff --git a/qcom/ravelin-atp.dtsi b/qcom/ravelin-atp.dtsi index f1aa4a4f..67401de2 100644 --- a/qcom/ravelin-atp.dtsi +++ b/qcom/ravelin-atp.dtsi @@ -56,7 +56,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi index 5de7dd7b..568b5aa0 100644 --- a/qcom/ravelin-idp.dtsi +++ b/qcom/ravelin-idp.dtsi @@ -105,7 +105,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-qrd.dtsi b/qcom/ravelin-qrd.dtsi index cf9f8ecd..bbb43de5 100644 --- a/qcom/ravelin-qrd.dtsi +++ b/qcom/ravelin-qrd.dtsi @@ -56,7 +56,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; /* diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi index 8b32a2fc..28cae426 100644 --- a/qcom/ravelin-rumi.dtsi +++ b/qcom/ravelin-rumi.dtsi @@ -156,7 +156,6 @@ &sdhc_2 { status = "ok"; vdd-supply = <&L24B>; - qcom,vdd-voltage-level = <2960000 2960000>; qcom,vdd-current-level = <0 800000>; vdd-io-supply = <&L28B>; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 03f7f28e..d5d8158b 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -1736,6 +1736,11 @@ reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, <0x007C8000 0x8000>, <0x007D0000 0x9000>; reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + iommus = <&apps_smmu 0x560 0x0>; + qcom,iommu-dma = "fastmap"; + + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; interrupts = , ; @@ -1765,6 +1770,11 @@ qcom,ice-clk-rates = <300000000 100000000>; + interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; + /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x000F642C 0x0 0x01 0x2C010800 0x80040868>; @@ -1773,18 +1783,6 @@ resets = <&gcc GCC_SDCC1_BCR>; reset-names = "core_reset"; - iommus = <&apps_smmu 0x560 0x0>; - dma-coherent; - qcom,iommu-dma = "fastmap"; - - qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; - qcom,iommu-geometry = <0x40000000 0x10000000>; - - interconnects = <&aggre2_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDC1>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - operating-points-v2 = <&sdhc1_opp_table>; - qos0 { mask = <0x03>; vote = <44>; @@ -1837,7 +1835,6 @@ 0x2C010800 0x80040868>; iommus = <&apps_smmu 0x140 0x0>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; From 85c0e79e7be5ab56a4afa9901b3018a2c183781b Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 14:26:50 +0800 Subject: [PATCH 44/66] ARM: dts: msm: Remove jtag_mm node on monaco Remove jtag_mm DT node as this feature is not enabled on monaco. Change-Id: I3fde6c254dbbdf9ced550fc53ba59a6e27866db0 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco.dtsi | 44 -------------------------------------------- 1 file changed, 44 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 63f5bec8..47991537 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1592,50 +1592,6 @@ }; - jtag_mm0: jtagmm@9040000 { - /* compatible = "qcom,jtagv8-mm"; */ - reg = <0x9040000 0x1000>; - reg-names = "etm-base"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "core_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU0>; - }; - - jtag_mm1: jtagmm@9140000 { - /* compatible = "qcom,jtagv8-mm"; */ - reg = <0x9140000 0x1000>; - reg-names = "etm-base"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "core_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU1>; - }; - - jtag_mm2: jtagmm@9240000 { - /* compatible = "qcom,jtagv8-mm"; */ - reg = <0x9240000 0x1000>; - reg-names = "etm-base"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "core_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU2>; - }; - - jtag_mm3: jtagmm@9340000 { - /* compatible = "qcom,jtagv8-mm"; */ - reg = <0x9340000 0x1000>; - reg-names = "etm-base"; - - clocks = <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "core_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU3>; - }; - dcc: dcc_v2@16FF000 { compatible = "qcom,dcc-v2"; reg = <0x16FF000 0x1000>, From b9e673f6bbd03f98fa3af2561d6618eb5f814a90 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 14:35:47 +0800 Subject: [PATCH 45/66] ARM: dts: msm: Remove hwevent node on monaco Remove hwevent DT node as hwevent is a legacy feature which is not used on monaco. Change-Id: I8236e94039309beb5c6c5e057f485e57cdb67851 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 1fc8403e..942c18e8 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -4,15 +4,6 @@ */ &soc { - hwevent { - /* compatible = "qcom,coresight-hwevent"; */ - - coresight-name = "coresight-hwevent"; - coresight-csr = <&csr>; - clocks = <&rpmcc RPM_SMD_QDSS_CLK>; - clock-names = "apb_pclk"; - }; - apss_tgu: tgu@9900000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b999>; From ffbf6d9d8dce6762a705551a0c54ab25520f5a24 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 14:39:01 +0800 Subject: [PATCH 46/66] ARM: dts: msm: Set STM traceid as static id on monaco Set STM traceid as static id on monaco. Change-Id: I141bcf8afe0eeb9e009a918ee9b5344a427e1386 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 942c18e8..5cb835e2 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -60,6 +60,7 @@ reg-names = "stm-base", "stm-stimulus-base"; coresight-name = "coresight-stm"; + atid = <16>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; From 0cc0fea8bec2185db20f84d2b609a97e515ebaad Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 14:43:44 +0800 Subject: [PATCH 47/66] ARM: dts: msm: Adapt coresight-dummy "compatible" in DT node to kernel-6.6 Adapt coresight-dummy "compatible" in DT node to kernel-6.6. Change-Id: Iefb6d3521ebca78034cc1c82670b62a60781413c Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 5cb835e2..85bbd395 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -116,9 +116,10 @@ }; modem_rfxe: modem_rfxe { - /* compatible = "qcom,coresight-dummy"; */ + compatible = "arm,coresight-dummy-source"; + coresight-name = "coresight-modem-rfxe"; - qcom,dummy-source; + out-ports { port { modem_rxfe_out_funnel_in1: endpoint { @@ -145,10 +146,9 @@ }; snoc: snoc { - /* compatible = "qcom,coresight-dummy"; */ + compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-snoc"; - qcom,dummy-source; out-ports { port { @@ -161,10 +161,10 @@ }; tpdm_lpass: tpdm@8a26000 { - /* compatible = "qcom,coresight-dummy"; */ + compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-tpdm-lpass"; - qcom,dummy-source; + out-ports { port { tpdm_lpass_out_funnel_lpass: endpoint { @@ -439,9 +439,8 @@ }; tpdm_wcss: tpdm@899c000 { - /* compatible = "qcom,coresight-dummy"; */ + compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-tpdm-wcss"; - qcom,dummy-source; out-ports { port { From e661d21688e9dd160c89469788b691c955b6b176 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 15:19:46 +0800 Subject: [PATCH 48/66] ARM: dts: msm: Set static traceid for coresight-dummy on monaco Set static traceid for coresight-dummy-source on monaco. Change-Id: Iff574a8f13b42c31240eb8f958f1b830cab4a4f0 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 85bbd395..2800154f 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -119,7 +119,7 @@ compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-modem-rfxe"; - + atid = <50>; out-ports { port { modem_rxfe_out_funnel_in1: endpoint { @@ -149,6 +149,7 @@ compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-snoc"; + atid = <125>; out-ports { port { @@ -164,7 +165,7 @@ compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-tpdm-lpass"; - + atid = <26>; out-ports { port { tpdm_lpass_out_funnel_lpass: endpoint { @@ -441,6 +442,7 @@ tpdm_wcss: tpdm@899c000 { compatible = "arm,coresight-dummy-source"; coresight-name = "coresight-tpdm-wcss"; + atid = <67>; out-ports { port { From bb7c60c9dbbc6a729856564e08813c364a77e209 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 15:24:01 +0800 Subject: [PATCH 49/66] ARM: dts: msm: Set static traceid for coresight-remote-etm on monaco Set static traceid for coresight-remote-etm on monaco. Change-Id: Id2c423639bde6a896982f289d9688668ffaad2fb Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 2800154f..13fe8d74 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -134,6 +134,7 @@ compatible = "qcom,coresight-remote-etm"; coresight-name = "coresight-audio-etm0"; + atid = <40>; qcom,inst-id = <5>; out-ports { port { @@ -484,6 +485,7 @@ compatible = "qcom,coresight-remote-etm"; coresight-name = "coresight-modem-etm0"; + atid = <36>; qcom,inst-id = <2>; out-ports { From 7371da08155cdedec823230f947a5ef774325ee7 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 15:32:12 +0800 Subject: [PATCH 50/66] ARM: dts: msm: Add audio-qmi dev node for audio_etm0 on monaco On kernel-6.6, QMI feature used by coresight needs to be abstracted as a device. Add audio-qmi dev node for audio_etm0 to support QMI feature. Change-Id: Ie66ef820b6cc7cdaff2cc516753ece87de4f9607 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 13fe8d74..2bf941e0 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -135,14 +135,39 @@ coresight-name = "coresight-audio-etm0"; atid = <40>; - qcom,inst-id = <5>; + out-ports { - port { + port@0 { + reg = <0>; audio_etm0_out_funnel_lpass: endpoint { remote-endpoint = <&funnel_lpass_in_audio_etm0>; }; }; + + port@1 { + reg = <1>; + audio_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_audio_etm0>; + }; + }; + }; + }; + + audio-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-auido"; + qcom,inst-id = <5>; + + in-ports { + port { + qmi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_qmi>; + }; + }; }; }; From dc8994ff511aaf321c69170665b5bfffecf07630 Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 15:38:49 +0800 Subject: [PATCH 51/66] ARM: dts: msm: Add modem-qmi dev node for modem_etm0 on monaco On kernel-6.6, QMI feature used by coresight needs to be abstracted as a device. Add modem-qmi dev node for modem_etm0 to support QMI feature. Change-Id: I2b56be596208f88353e5cf1a89751f7760c89851 Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 2bf941e0..9bf758a1 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -511,15 +511,39 @@ coresight-name = "coresight-modem-etm0"; atid = <36>; - qcom,inst-id = <2>; out-ports { - port { + port@0 { + reg = <0>; modem_etm0_out_funnel_in1: endpoint { remote-endpoint = <&funnel_in1_in_modem_etm0>; }; }; + + port@1 { + reg = <1>; + modem_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_modem_etm0>; + }; + }; + }; + }; + + modem-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-modem"; + qcom,inst-id = <2>; + + in-ports { + port { + qmi_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_qmi>; + }; + }; }; }; From d671d1270decea77e327679bc9c4be43dabd8e0e Mon Sep 17 00:00:00 2001 From: Xiaoqi Zhuang Date: Tue, 25 Jun 2024 15:40:59 +0800 Subject: [PATCH 52/66] ARM: dts: msm: Modify tpda dev name to adapt kernel-6.6 on monaco Modify tpda dev name to adapt kernel-6.6 on monaco. Change-Id: Ia314bb681817ab6f4c66e10adb3be4c01fbe7b6f Signed-off-by: Xiaoqi Zhuang --- qcom/monaco-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index 9bf758a1..afb072f1 100644 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -957,13 +957,13 @@ }; }; - tpda: tpda@8004000 { + tpda_dl: tpda@8004000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb969>; reg = <0x8004000 0x1000>; reg-names = "tpda-base"; - coresight-name = "coresight-tpda"; + coresight-name = "coresight-tpda-dl"; qcom,tpda-atid = <65>; qcom,dsb-elem-size = <0 32>, From b260a7e48920fcf67dfd71a8bc099aaf4882bd17 Mon Sep 17 00:00:00 2001 From: Amir Vajid Date: Tue, 25 Jun 2024 11:36:33 -0700 Subject: [PATCH 53/66] ARM: dts: qcom: Remove gold bwmon low power cpu for sun Remove low power cpu property as it is no longer needed to enable the feature. Change-Id: Idc8f21b44b36ed73a5dc1c761b6195134c4cb1bf Signed-off-by: Amir Vajid --- qcom/sun.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 3c7a90f2..6e2bc13c 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3408,7 +3408,6 @@ qcom,count-unit = <0x10000>; qcom,target-dev = <&qcom_llcc_dcvs_hw>; qcom,second-vote = <&qcom_llcc_ddr_vote>; - qcom,low-power-cpu = <0>; }; bwmon_llcc_prime: qcom,bwmon-llcc-prime@240B7300 { From b9ee7a6859387ca7ca9b22d0a4bf13579328b1c3 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Wed, 26 Jun 2024 23:07:39 +0530 Subject: [PATCH 54/66] ARM: dts: msm: Add support for new parrot board id Add initial device tree support for new parrot board id. This is a snapshot of dtsi files as of KP.1.0 'commit ("ARM: dts: msm: Add support for new WCN Card for Parrot")'. Modified as per compilation and bootup. Change-Id: Ic9b5c7dc8c900c9e7e8e2bbd4d56f8b8e92ed1ad Signed-off-by: Swetha Chikkaboraiah --- qcom/Makefile | 7 ++++++- .../parrot-idp-wcn6755-amoled-rcm-overlay.dts | 19 ++++++++++++++++++ qcom/parrot-idp-wcn6755-nopmi-overlay.dts | 20 +++++++++++++++++++ qcom/parrot-idp-wcn6755-overlay.dts | 19 ++++++++++++++++++ qcom/parrot-idp-wcn6755-pm8350b-overlay.dts | 19 ++++++++++++++++++ qcom/parrot-qrd-wcn6755-overlay.dts | 19 ++++++++++++++++++ qcom/platform_map.bzl | 5 +++++ 7 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 qcom/parrot-idp-wcn6755-amoled-rcm-overlay.dts create mode 100644 qcom/parrot-idp-wcn6755-nopmi-overlay.dts create mode 100644 qcom/parrot-idp-wcn6755-overlay.dts create mode 100644 qcom/parrot-idp-wcn6755-pm8350b-overlay.dts create mode 100644 qcom/parrot-qrd-wcn6755-overlay.dts diff --git a/qcom/Makefile b/qcom/Makefile index ebe62f22..50bec119 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -107,7 +107,12 @@ PARROT_BOARDS += \ parrot-qrd-overlay.dtbo \ parrot-qrd-wcn6750-overlay.dtbo \ parrot-qrd-nopmi-overlay.dtbo \ - parrot-qrd-pm8350b-overlay.dtbo + parrot-qrd-pm8350b-overlay.dtbo \ + parrot-idp-wcn6755-overlay.dtbo \ + parrot-idp-wcn6755-amoled-rcm-overlay.dtbo \ + parrot-qrd-wcn6755-overlay.dtbo \ + parrot-idp-wcn6755-pm8350b-overlay.dtbo \ + parrot-idp-wcn6755-nopmi-overlay.dtbo PARROT_4GB_BOARDS += \ parrot-idp-4gb-overlay.dtbo \ diff --git a/qcom/parrot-idp-wcn6755-amoled-rcm-overlay.dts b/qcom/parrot-idp-wcn6755-amoled-rcm-overlay.dts new file mode 100644 index 00000000..78d88fc5 --- /dev/null +++ b/qcom/parrot-idp-wcn6755-amoled-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-idp-wcn6750-amoled-rcm.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>, + <663 0x10000>; + qcom,board-id = <34 6>; +}; diff --git a/qcom/parrot-idp-wcn6755-nopmi-overlay.dts b/qcom/parrot-idp-wcn6755-nopmi-overlay.dts new file mode 100644 index 00000000..057ceb2e --- /dev/null +++ b/qcom/parrot-idp-wcn6755-nopmi-overlay.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>, + <663 0x10000>; + qcom,board-id = <34 5>; + qcom,pmic-id-size = <9>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; +}; diff --git a/qcom/parrot-idp-wcn6755-overlay.dts b/qcom/parrot-idp-wcn6755-overlay.dts new file mode 100644 index 00000000..b3482aa8 --- /dev/null +++ b/qcom/parrot-idp-wcn6755-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-idp.dtsi" +#include "parrot-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>, + <663 0x10000>; + qcom,board-id = <34 5>; +}; diff --git a/qcom/parrot-idp-wcn6755-pm8350b-overlay.dts b/qcom/parrot-idp-wcn6755-pm8350b-overlay.dts new file mode 100644 index 00000000..ed0389eb --- /dev/null +++ b/qcom/parrot-idp-wcn6755-pm8350b-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-idp.dtsi" +#include "parrot-idp-pm8350b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot IDP + WCN6755"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>, + <663 0x10000>; + qcom,board-id = <34 5>; +}; diff --git a/qcom/parrot-qrd-wcn6755-overlay.dts b/qcom/parrot-qrd-wcn6755-overlay.dts new file mode 100644 index 00000000..fba1b173 --- /dev/null +++ b/qcom/parrot-qrd-wcn6755-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "parrot-qrd-wcn6750.dtsi" +#include "parrot-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6755 QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>, + <663 0x10000>; + qcom,board-id = <0x1000B 2>; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index f70d7b36..deb66a79 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -218,6 +218,11 @@ _platform_map = { {"name": "parrot-idp-wcn6750-amoled-4gb-overlay.dtbo"}, {"name": "parrot-qrd-4gb-overlay.dtbo"}, {"name": "parrot-qrd-wcn6750-4gb-overlay.dtbo"}, + {"name": "parrot-idp-wcn6755-amoled-rcm-overlay.dtbo"}, + {"name": "parrot-idp-wcn6755-overlay.dtbo"}, + {"name": "parrot-qrd-wcn6755-overlay.dtbo"}, + {"name": "parrot-idp-wcn6755-pm8350b-overlay.dtbo"}, + {"name": "parrot-idp-wcn6755-nopmi-overlay.dtbo"}, {"name": "ravelin-rumi-overlay.dtbo"}, {"name": "ravelin-atp-overlay.dtbo"}, {"name": "ravelin-idp-overlay.dtbo"}, From 771b0b212bc96017dadf2e81b3858f4ad191e1be Mon Sep 17 00:00:00 2001 From: Shivangi Kesharwani Date: Mon, 24 Jun 2024 18:29:52 +0530 Subject: [PATCH 55/66] ARM: dts: msm: monaco: Add qseecom compatible Add dt support for qseecom for Monaco SOC. Signed-off-by: Shivangi Kesharwani --- qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 63f5bec8..5ec09f0a 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -577,7 +577,7 @@ }; qcom_qseecom: qseecom@61800000 { - /* compatible = "qcom,qseecom"; */ + compatible = "qcom,qseecom"; reg = <0x61800000 0x2100000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; From 68f23d29a8b0894a97b29b561d8f01db0157d0ad Mon Sep 17 00:00:00 2001 From: Shivangi Kesharwani Date: Thu, 27 Jun 2024 16:01:51 +0530 Subject: [PATCH 56/66] ARM: dts: msm: monaco: Add qrng compatible Add dt support for qrng for Monaco SOC. Signed-off-by: Shivangi Kesharwani --- qcom/monaco.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 63f5bec8..a4a8b338 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -622,6 +622,16 @@ hyplog-size-offset = <0x414>; }; + qcom_rng: qrng@4453000 { + compatible = "qcom,msm-rng"; + reg = <0x4453000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM>; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + }; + qcom_cedev: qcedev@1b20000 { compatible = "qcom,qcedev"; reg = <0x1b20000 0x20000>, From 888f53106b2f61252c67ebe05cdc5e781138f598 Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Thu, 27 Jun 2024 12:45:53 +0530 Subject: [PATCH 57/66] ARM: dts: msm: shutdown as pinctrl state is missing for UART node in parrot As part of initial commit '57abd8093413f0969d6c14d38028486e0d303e74 (ARM: dts: msm: Add QUPv3 and GPI DT nodes on Parrot")', pinctrl state for "shutdown" is missing because of which we are not configuring the pinctrl state when shutdown pinctrl state is being called. Add "shutdown" pinctrl state in parrot for uart node. Change-Id: I9d04f6c649652918db0198069c0fd2d19221590b Signed-off-by: Prasanna S --- qcom/parrot-qupv3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi index 024a5083..8514544f 100644 --- a/qcom/parrot-qupv3.dtsi +++ b/qcom/parrot-qupv3.dtsi @@ -574,7 +574,7 @@ <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, <&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>, <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; - pinctrl-names = "default", "active", "sleep"; + pinctrl-names = "default", "active", "sleep", "shutdown"; pinctrl-0 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>, <&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>; pinctrl-1 = <&qupv3_se11_cts>, <&qupv3_se11_rts>, From 023ab0142173bedd5a37622d535d21b514ec1a9c Mon Sep 17 00:00:00 2001 From: Yu Tian Date: Fri, 21 Jun 2024 00:17:52 -0700 Subject: [PATCH 58/66] ARM: dts: msm: sun: Enlarge WCNSS and ADSP IOMMU range to 2G Enlarge WCNSS and ADSP MMU group range from 640MB to 2GB. Change-Id: I86dbe3c6d82561383b050c0cccfebf07bf74eed6 CRs-Fixed: 3853708 Signed-off-by: Yu Tian --- qcom/sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index aa25676f..f34d12b7 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3568,7 +3568,7 @@ cnss_audio_iommu_group0: cnss_audio_iommu_group0 { qcom,iommu-msi-size = <0x1000>; - qcom,iommu-geometry = <0x88000000 0x28010000>; + qcom,iommu-geometry = <0x18000000 0x98010000>; qcom,iommu-dma = "fastmap"; qcom,iommu-pagetable = "coherent"; qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; From 15c51505c590004552d66638cdfd1d7c05d4c749 Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Fri, 28 Jun 2024 13:21:16 +0530 Subject: [PATCH 59/66] ARM: dts: msm: Remove qcom,msm_fastrpc from parrot.dtsi Remove the qcom,msm_fastrpc nodes as these are moved to dsp-devicetree. Change-Id: Ia1faa5215e1b7130bbecc92ad16d7d1af689902a Signed-off-by: Akhil Manikoth Kallankandy --- qcom/parrot.dtsi | 161 ----------------------------------------------- 1 file changed, 161 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 0b1c2cca..5e161606 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2243,12 +2243,6 @@ 0x4400 2>; }; - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; - }; - qcom,msm_cdsprm_rpmsg { compatible = "qcom,msm-cdsprm-rpmsg"; qcom,glink-channels = "cdsprmglink-apps-dsp"; @@ -2582,162 +2576,7 @@ qcom,pipe-attr-ee; }; - msm_fastrpc: qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-compute"; - qcom,adsp-remoteheap-vmid = <22 37>; - qcom,fastrpc-adsp-audio-pdr; - qcom,fastrpc-adsp-sensors-pdr; - qcom,rpc-latency-us = <235>; - qcom,fastrpc-gids = <2908>; - qcom,qos-cores = <0 1 2 3>; - qcom,msm_fastrpc_compute_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1401 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1402 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb3 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1403 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb4 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1404 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb5 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1405 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb6 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1406 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb7 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1407 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb8 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x1408 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb9 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - qcom,secure-context-bank; - iommus = <&apps_smmu 0x1409 0x0400>; - qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb10 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1803 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb11 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1804 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb12 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&apps_smmu 0x1805 0x0>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - shared-cb = <5>; - }; - - qcom,msm_fastrpc_compute_cb13 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x140B 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb14 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x140C 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb15 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x140D 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb16 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&apps_smmu 0x140E 0x0400>; - qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; - qcom,iommu-faults = "stall-disable", "HUPCF"; - dma-coherent; - }; - }; thermal_zones: thermal-zones { }; From aa4439896f8fc45bcf51b3d1354b6d5970f02c83 Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Fri, 28 Jun 2024 13:20:25 +0530 Subject: [PATCH 60/66] ARM: dts: msm: Labeling CDSP node adding label for cdsp node to use in dsp-kernel. Change-Id: I080091772791ff6f145743496b5ad9b0e3cabc57 Signed-off-by: Akhil Manikoth Kallankandy --- qcom/parrot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 0b1c2cca..bbcb5145 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2222,7 +2222,7 @@ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; - glink-edge { + remoteproc_cdsp_glink: glink-edge { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP From 74db79dab6036ca2f0d9cf78b9ba9cca239ad004 Mon Sep 17 00:00:00 2001 From: Nageswara reddy Karnati Date: Thu, 27 Jun 2024 06:26:24 -0700 Subject: [PATCH 61/66] ARM: dts: msm: add ufs wrapped key support to parrot Add support for ice wrapped keys to the UFS DTSI entry on parrot targets. Change-Id: I7c0393a99995a331c807432212f8f2258c189947 Signed-off-by: Nageswara reddy Karnati --- qcom/parrot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 0b1c2cca..e1e0933e 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -1876,14 +1876,14 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x8000>, - <0x1d90000 0x9000>; - reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + <0x1d88000 0x18000>; + reg-names = "ufs_mem", "ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice-use-hwkm; lanes-per-direction = <2>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ clock-names = From 2ff9f4d6a37da7f5820d6db55074302611a294df Mon Sep 17 00:00:00 2001 From: Akhil Manikoth Kallankandy Date: Fri, 28 Jun 2024 13:19:25 +0530 Subject: [PATCH 62/66] ARM: dts: msm: Update parrot glink node Fix for pmic glink node for parrot without this change glink channel registration fails for the ADSP communication. Change-Id: Ib8a79ca286a884ea679cc34829823cdeca8f5751 Signed-off-by: Akhil Manikoth Kallankandy --- qcom/parrot.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 0b1c2cca..8fd9dcd6 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2167,6 +2167,7 @@ qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; @@ -2174,10 +2175,15 @@ qcom,no-wake-svc = <0x190>; }; - qcom,msm_fastrpc_rpmsg { - compatible = "qcom,msm-fastrpc-rpmsg"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - qcom,intents = <0x64 64>; + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; }; }; }; From 263d3731ee2e178b9079c75b29c749259a3c573f Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Mon, 13 May 2024 10:03:06 +0530 Subject: [PATCH 63/66] ARM: dts: msm: Add smem nodes for tuna Add smem nodes for tuna SoC. Change-Id: If87321e31c1ddddef4370657029dc82e0778a021 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna-reserved-memory.dtsi | 4 +++- qcom/tuna.dtsi | 11 +++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi index 8c9df41b..b990fbcb 100644 --- a/qcom/tuna-reserved-memory.dtsi +++ b/qcom/tuna-reserved-memory.dtsi @@ -66,8 +66,10 @@ }; smem_mem: smem_region@81d00000 { - no-map; + compatible = "qcom,smem"; reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; }; pdp_ns_shared_mem: pdp_ns_shared_region@81f00000 { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 59675080..eaaff929 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -473,6 +473,17 @@ wakeup-parent = <&pdc>; }; + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + ipcc_mproc: qcom,ipcc@406000 { compatible = "qcom,ipcc"; reg = <0x406000 0x1000>; From fba395ddc1ac246eee5cc89be1fbea7fc73fc11f Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 13 Mar 2024 15:58:11 +0530 Subject: [PATCH 64/66] bindings: Add bindings for FSA4480 This device is required for enabling USB-C analog support. Change-Id: I2f7749a9562ef91f2c472bfeb8dfb1df145e1677 Signed-off-by: Soumya Managoli --- bindings/soc/qcom/qcom,fsa4480-i2c.yaml | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 bindings/soc/qcom/qcom,fsa4480-i2c.yaml diff --git a/bindings/soc/qcom/qcom,fsa4480-i2c.yaml b/bindings/soc/qcom/qcom,fsa4480-i2c.yaml new file mode 100644 index 00000000..8ddbad08 --- /dev/null +++ b/bindings/soc/qcom/qcom,fsa4480-i2c.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,fsa4480-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fairchild FSA4480 Device + +maintainers: + - Soumya Managoli + +description: | + This device is used for switching orientation of USB-C analog + and for display. It uses I2C communication to set the registers + to configure the switches inside the FSA4480 chip to change + orientation and also to set SBU1/SBU2 connections of USB-C. + +properties: + compatible: + const: qcom,fsa4480-i2c + + reg: + description: | + I2C device address of the device + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + }; +... From bf0cfc08d498a18b2928533f2d3429818b820012 Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Tue, 21 May 2024 12:08:43 +0530 Subject: [PATCH 65/66] ARM: dts: msm: update repeater override sequence on sun HDK Update HS trasmit amplitude and Tx pre-emphasis for sun HDK platform. Change-Id: I7f7c03ec19dc004d88ca00d53491f06f62ffb3ba Signed-off-by: Pratham Pratap --- qcom/sunp-hdk.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index b06d28f4..26edca46 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -90,3 +90,12 @@ status = "ok"; }; }; + +&pmih010x_eusb2_repeater { + qcom,param-override-seq = + /* */ + /* Adjust HS trasmit amplitude */ + <0xc 0x51 + /* Tx pre-emphasis tuning */ + 0x5 0x57>; +}; From a374335029a599abbb6756866936f7244b2549e4 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Tue, 2 Jul 2024 17:17:12 +0530 Subject: [PATCH 66/66] ARM: dts: msm: Adjust HS transmit amplitude for more coverage Currently, it seems the HS transmit programmed isn't enough to pass electrical compliance tests for all devices. Therefore increasing it to 0xf (recommended by HW team) in order to meet the passing marks. Change-Id: I6609d6012e8ec6489c33af0a75873314a5b10e67 Signed-off-by: Udipto Goswami --- qcom/sunp-hdk.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sunp-hdk.dtsi b/qcom/sunp-hdk.dtsi index 26edca46..d7fa4e61 100644 --- a/qcom/sunp-hdk.dtsi +++ b/qcom/sunp-hdk.dtsi @@ -95,7 +95,7 @@ qcom,param-override-seq = /* */ /* Adjust HS trasmit amplitude */ - <0xc 0x51 + <0xf 0x51 /* Tx pre-emphasis tuning */ 0x5 0x57>; };