ARM: dts: msm: Add initial device trees for Sun SoC

Add initial device trees to support Sun SoC and it's
platforms.

Change-Id: I885a56e29438675e3d7aa449f5e25f00cb28b02a
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>

qcom/Makefile

@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# add-overlay defines the target with following naming convention:
+# <base>-<board>-dtbs = base.dtb board.dtbo
+#
+# Combined dtb target is also generated using the fdt_overlay tool.
+# dtb-y += <base>-<board>.dtb
+
+add-overlays = $(foreach o,$1,$(foreach b,$2,$(eval $(basename $b)-$(basename $o)-dtbs = $b $o) $(basename $b)-$(basename $o).dtb))
+
+# sun-dtb-y is list of DTBs to install when doing non-overlay build
+# sun-overlays-dtb-y is list of DTBs and DTBOs to install when doing overlay-supported build
+# see DTB_TYPES from scripts/Makefile.dtbinst and install_dtbs from build.config.msm.common
+#
+
+ifneq ($(CONFIG_ARCH_QTI_VM), y)
+
+SUN_BASE_DTB += sun.dtb
+
+SUN_BOARDS += \
+		 sun-mtp-overlay.dtbo \
+		 sun-cdp-overlay.dtbo \
+		 sun-qrd-overlay.dtbo
+
+NOAPQ_SUN_BOARDS += \
+		 sun-rumi-overlay.dtbo
+
+sun-dtb-$(CONFIG_ARCH_SUN) += \
+	$(call add-overlays, $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS),$(SUN_BASE_DTB))\
+	$(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB))
+sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB)
+dtb-y += $(sun-dtb-y)
+endif
+
+always-y        := $(dtb-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb *.dtbo

qcom/platform_map.bzl

@@ -0,0 +1,47 @@
+_platform_map = {
+    "sun": {
+        "dtb_list": [
+            # keep sorted
+            {"name": "sun.dtb"},
+        ],
+        "dtbo_list": [
+            # keep sorted
+            {"name": "sun-cdp-overlay.dtbo"},
+            {"name": "sun-mtp-overlay.dtbo"},
+            {"name": "sun-qrd-overlay.dtbo"},
+            {"name": "sun-rumi-overlay.dtbo"},
+        ],
+    },
+}
+
+def _get_dtb_lists(target, dt_overlay_supported):
+    if not target in _platform_map:
+        fail("{} not in device tree platform map!".format(target))
+
+    ret = {
+        "dtb_list": [],
+        "dtbo_list": [],
+    }
+
+    for dtb_node in [target] + _platform_map[target].get("binary_compatible_with", []):
+        ret["dtb_list"].extend(_platform_map[dtb_node].get("dtb_list", []))
+        if dt_overlay_supported:
+            ret["dtbo_list"].extend(_platform_map[dtb_node].get("dtbo_list", []))
+        else:
+            # Translate the dtbo list into dtbs we can append to main dtb_list
+            for dtb in _platform_map[dtb_node].get("dtb_list", []):
+                dtb_base = dtb["name"].replace(".dtb", "")
+                for dtbo in _platform_map[dtb_node].get("dtbo_list", []):
+                    if not dtbo.get("apq", True) and dtb.get("apq", False):
+                        continue
+
+                    dtbo_base = dtbo["name"].replace(".dtbo", "")
+                    ret["dtb_list"].append({"name": "{}-{}.dtb".format(dtb_base, dtbo_base)})
+
+    return ret
+
+def get_dtb_list(target, dt_overlay_supported=True):
+    return [dtb["name"] for dtb in _get_dtb_lists(target, dt_overlay_supported).get("dtb_list", [])]
+
+def get_dtbo_list(target, dt_overlay_supported=True):
+    return [dtb["name"] for dtb in _get_dtb_lists(target, dt_overlay_supported).get("dtbo_list", [])]

qcom/sun-cdp-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-cdp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>;
+	qcom,board-id = <1 0>;
+};

qcom/sun-cdp.dtsi

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+

qcom/sun-mtp-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-mtp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>;
+	qcom,board-id = <8 0>;
+};

qcom/sun-mtp.dtsi

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+

qcom/sun-qrd-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-qrd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,qrd";
+	qcom,msm-id = <618 0x10000>;
+	qcom,board-id = <11 0>;
+};

qcom/sun-qrd.dtsi

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+

qcom/sun-rumi-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/memreserve/ 0x90000000 0x100;
+
+#include "sun.dtsi"
+#include "sun-rumi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RUMI";
+	compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi";
+	qcom,board-id = <15 0>;
+};

qcom/sun-rumi.dtsi

@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&reserved_memory {
+	spintable: spintable_region@e3940000 {
+		no-map;
+		reg = <0x0 0xe3940000 0x0 0x100000>;
+	};
+};
+
+&arch_timer {
+	clock-frequency = <192000>;
+};
+
+&memtimer {
+	clock-frequency = <192000>;
+};

qcom/sun.dts

@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sun.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun SoC";
+	compatible = "qcom,sun";
+	qcom,board-id = <0 0>;
+};

qcom/sun.dtsi

@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun";
+	compatible = "qcom,sun";
+	qcom,msm-id = <618 0x10000>;
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+
+	chosen: chosen {
+		bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
+	};
+
+	aliases { };
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU4: cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU5: cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU6: cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			};
+		};
+
+		CPU7: cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_6>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+
+				core4 {
+					cpu = <&CPU4>;
+				};
+
+				core5 {
+					cpu = <&CPU5>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU6>;
+				};
+
+				core1 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	reserved_memory: reserved-memory { };
+
+	soc: soc { };
+};
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@16000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x40000>;
+		reg = <0x16000000 0x10000>,	/* GICD */
+		      <0x16080000 0x200000>;	/* GICR * 8 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	memtimer: timer@16800000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x16800000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@16801000 {
+			frame-number = <0>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x16801000 0x1000>,
+			      <0x16802000 0x1000>;
+		};
+
+		frame@16803000 {
+			frame-number = <1>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x16803000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@16805000 {
+			frame-number = <2>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x16805000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@16807000 {
+			frame-number = <3>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x16807000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@16809000 {
+			frame-number = <4>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x16809000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1680b000 {
+			frame-number = <5>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1680b000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@1680d000 {
+			frame-number = <6>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0x1680d000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <19200000>;
+	};
+};
+