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Merge "ARM: dts: msm: sun: Add remoteproc node"

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qctecmdr
2023-10-10 10:25:56 -07:00
committed by Gerrit - the friendly Code Review server
parent af7449fe39 0cb93bbbaa
commit c163efff9f
3 changed files with 473 additions and 17 deletions
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85
bindings/qdsp/msm-fastrpc.yaml
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@@ -4,30 +4,95 @@
$id: "http://devicetree.org/schemas/qdsp/msm-fastrpc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ADSP remote heap region
title: Qualcomm Technologies, Inc. FastRPC Driver
description:
Defines the ADSP remote heap region. Device used for CMA allocations
and mappings for both secure and non-secure usecases.
The MSM FastRPC driver implements an IPC (Inter-Processor Communication)
mechanism that allows for clients to transparently make remote method
invocations across DSP and APPS boundaries. This enables developers
to offload tasks to the DSP and free up the application processor for
other tasks.qcom,adsprpc-mem node defines the ADSP remote heap region.
Device is used for CMA allocations and mappings for both secure and
non-secure usecases.
maintainers:
- Anirudh Raghavendra <quic_araghave@quicinc.com>
properties:
compatible :
const: qcom,adsprpc-mem
oneOf:
- items:
- "qcom,msm-fastrpc-adsp"
- "qcom,msm-fastrpc-compute"
optional:
- qcom,rpc-latency-us : FastRPC QoS latency vote
- qcom,adsp-remoteheap-vmid : FastRPC remote heap VMID list
- qcom,secure-context-bank : Bool indicating secure FastRPC context bank.
- qcom,fastrpc-legacy-remote-heap : Bool indicating hypervisor is not supported.
- qcom,fastrpc-adsp-audio-pdr : Flag to enable ADSP Audio PDR
- qcom,secure-domains : FastRPC secure domain configuration
- qcom,fastrpc-adsp-sensors-pdr : Flag to enable Sensors PDR
child-node:
description:
Child nodes representing the compute context banks
properties:
required:
- compatible
- memory-region
- restrict-access
- compatible : Must be "qcom,msm-fastrpc-compute-cb"
- label : Label describing the channel this context bank belongs to
- iommus : A list of phandle and IOMMU specifier pairs that describe the
IOMMU master interfaces of the device
- dma-coherent : A flag marking a context bank as I/O coherent
- shared-cb : A value indicating how many fastrpc sessions can share a
context bank
additionalProperties: false
child-node:
description:
Child node for rpmsg instead of glink for IPC
properties:
required:
- compatible : Must be "qcom,msm-fastrpc-rpmsg"
examples:
- |
child-node:
description:
Child node representing the Remote Heap region
properties:
required:
- compatible : Must be "qcom,msm-adsprpc-mem-region"
- memory-region : CMA region which is owned by this device
- restrict-access : Blocking vote for hyp_assign_phys function call
Example:
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,fastrpc-rpmsg;
qcom,rpc-latency-us = <235>;
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-sensors-pdr;
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
intents = <0x64 64>;
};
qcom,msm_fastrpc_compute_cb_1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
iommus = <&apps_smmu 0x1401 0x0>;
dma-coherent;
};
qcom,msm_fastrpc_compute_cb_2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "sdsprpc-smd";
iommus = <&apps_smmu 0x1402 0x0>;
shared-cb = <5>;
};
qcom,adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
};

148
bindings/soc/qcom/cdsprm.yaml Normal file
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@@ -0,0 +1,148 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/soc/qcom/cdsprm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. CDSP Request Manager driver
description:
CDSP Request Manager driver implements an rpmsg interface with
CDSP subsystem to serve L3 frequency and CPU QoS requests from CDSP.
It also interacts with NPU, Camera modules for Cx iPeak mitigations and
thermal module via CDSP/HVX cooling devices for thermal mitigation of
CDSP core. It sends VTCM partitioning information on supported chipsets
to CDSP.
maintainers:
- Gokul krishna Krishnakumar<quic_gokukris@quicinc.com>
properties:
required:
compatible:
const: qcom,msm-cdsprm-rpmsg
qcom,glink-channels: Glink channel for communication with CDSP
qcom,intents: A list of <size of each intent, number of intents>
child-node:
description:
A sub-device node to define CDSPM RM, Cx iPeak mitigation
driver, CDSP core thermal cooling device and CDSP VTCM partitioning
properties:
required:
compatible:
const: qcom,msm-cdsprm-rm
qcom,qos-latency-us: pm_qos latency vote to be applied on CDSP request in
micro seconds
qcom,qos-maxhold-ms: Maximum hold time for pm_qos latency vote from CDSP
in milli seconds
optional:
qcom,compute-cx-limit-en: To enable CX ipeak limit management for compute
subsystem
qcom,compute-priority-mode: when Cx iPeak mitigation is enabled,
this field sets desired compute priority mode
for AIX and HVX concurrency cases based on
following values, where in HVX and NPU cores,
if required, are throttled in concurrency based
on the selected priority mode
1 : HVX_MAX - Allows HVX to run at maximum possible
frequency during concurrency with NPU
2 : AIX_MAX - Allows NPU to run at maximum possible
frequency during concurrency with HVX
3 : HVX_OVER_AIX - Allows HVX to run at a higher
frequency than NPU during concurrency
4 : AIX_OVER_HVX - Allows NPU to run at a higher
frequency than HVX during concurrency
qcom,vtcm-paritions: Number of VTCM partitions (maximum 16)
qcom,vtcm-partition-info: Specifies the partitions, their sizes and
flags. Most importantly flags can be used to
set some partitions as privileged,
i.e. only available to privileged clients.
Currently VTCM_FLAG_PRIMARY(0x1), VTCM_FLAG_SECONDARY (0x2)and
VTCM_FLAG_PRIVILEGED(0x4) are the supported flags per partition
(only one per partition).
Size of each partition should be a multiple of 256KB.
Given 256KB is the minimum VTCM allocation size,
256K, 1M, 4M are supported page sizes.
Specifying a 3MB partition will allow maximum of 1MB page (3x).
Similarly, a 512KB partition will be of 256KB pages (2x).
PRIMARY and SECONDARY partitions are available to all the clients while
the PRIMARY partition is used by default. Partition selection is
controlled by the vtcm-partition-map information.
There must be only one PRIMARY partition.
Partitions must be defined with a linear partition index
starting with 0 till (Number of VTCM partitions - 1).
VTCM memory will be partitioned in the order provided
(0 being the first partition).
qcom,vtcm-partition-map: Maps application type identifiers to
partitions. Clients use application type IDs to
request non-default partitions.
Application identifier is specified as a value [0 – 31]
in the device tree. The default application identifier
will be 0. Application identifier must be unique for each
partition map. Any unassigned application identifier
in the set of [0 – 31] will be mapped to the PRIMARY partition
and will return failure if there is no
qcom,resmgr-pdkill-enable: To enable resource manager PD kill mechanism. When enabled,
the resource manager (managing VTCM, HMX resources) can kill an
unsigned process holding any of the resources being
requested by a privileged process if the release requests sent by
the resource manager are not acted upon.
cooling-cells: Number of cooling cells for CDSP cooling device based on
CDSP Q6 core clock throttling
child-node:
description:
A sub-device node to define HVX based thermal cooling device
properties:
required:
compatible:
const: qcom,msm-hvx-rm
cooling-cells: Number of cooling cells for CDSP cooling device based on
HVX hardware throttling
child-node:
description:
A sub-device node to define CDSP L3 target device for L3 clock voting
properties:
required:
compatible:
const: qcom,cdsp-l3
qcom,target-dev: The DT device that corresponds to the CDSP L3
devfreq-simple-dev
examples:
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x14 64>;
qcom,cdsp-l3 {
compatible = "qcom,cdsp-l3";
qcom,target-dev = <&cdsp-cdsp-l3-lat>;
};
qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <100>;
qcom,qos-maxhold-ms = <20>;
qcom,compute-cx-limit-en;
qcom,compute-priority-mode = <2>;
#cooling-cells = <2>;
qcom,vtcm-paritions = <4>;
qcom,vtcm-partition-info = < 0 2048 0x1 >,
< 1 1024 0x2 >,
< 2 512 0x4 >,
< 3 512 0x4 >;
qcom,vtcm-partition-map = < 0 0 >,
< 1 0 >,
< 2 1 >,
< 30 2 >,
< 31 3 >;
};
msm_hvx_rm: qcom,msm_hvx_rm {
compatible = "qcom,msm-hvx-rm";
#cooling-cells = <2>;
};
};

243
qcom/sun.dtsi
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@@ -18,6 +18,7 @@
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
/ {
@@ -1489,6 +1490,248 @@
restrict-access;
};
adsp_pas: remoteproc-adsp@03000000 {
compatible = "qcom,sun-adsp-pas";
reg = <0x03000000 0x10000>;
status = "ok";
cx-supply = <&VDD_LPI_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
mx-supply = <&VDD_LPI_MX_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
reg-names = "cx", "mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
firmware-name = "adsp.mdt", "adsp_dtb.mdt";
memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;
/* Inputs from ssc */
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack";
/* Outputs to turing */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink_edge: glink-edge {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,net-id = <2>;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
qcom,no-wake-svc = <0x190>;
};
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
};
};
modem_pas: remoteproc-mss@04080000 {
compatible = "qcom,sun-modem-pas";
reg = <0x4080000 0x10000>;
status = "ok";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-supply = <&VDD_MODEM_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
reg-names = "cx", "mx";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
memory-region = <&mpss_mem &q6_mpss_dtb_mem &dsm_partition_1_mem &dsm_partition_2_mem>;
firmware-name = "modem.mdt", "modem_dtb.mdt";
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
};
};
cdsp_pas: remoteproc-cdsp@32300000 {
compatible = "qcom,sun-cdsp-pas";
reg = <0x32300000 0x10000>;
status = "ok";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-supply = <&VDD_MXC_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
nsp-supply = <&VDD_NSP1_LEVEL>;
nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx","mx","nsp";
firmware-name = "cdsp.mdt", "cdsp_dtb.mdt";
memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "cdsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-cores = <0 1>;
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
};
};
thermal_zones: thermal-zones {
};
};