ARM: dts: msm: Initial EVA device tree
Initial draft with required markings. Change-Id: I36651f21d1770c61d83128f5283c5eaffe3679d6 Signed-off-by: Jingjing Guo <quic_jig@quicinc.com> Signed-off-by: George Shen <quic_sqiao@quicinc.com>
This commit is contained in:
George Shen
20
Kbuild
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20
Kbuild
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@@ -0,0 +1,20 @@
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ifneq ($(CONFIG_ARCH_QTI_VM), y)
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ifeq ($(CONFIG_ARCH_SUN), y)
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dtbo-y += sun-eva.dtbo
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endif
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ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
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dtbo-y += pineapple-eva.dtbo
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endif
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ifeq ($(CONFIG_ARCH_KALAMA), y)
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dtbo-y += trustedvm-kalama-eva-mtp.dtbo \
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trustedvm-kalama-eva-qrd.dtbo
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endif
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
Makefile
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9
Makefile
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@@ -0,0 +1,9 @@
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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107
bindings/msm-eva-bus.yaml
Normal file
107
bindings/msm-eva-bus.yaml
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@@ -0,0 +1,107 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP BUS
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description: |
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Second level nodes - Buses
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-cvp,bus
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label:
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description: an arbitrary name
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qcom,bus-master:
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description:
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an integer descriptor of the bus master. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of
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acceptable masters
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qcom,bus-slave:
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description:
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an integer descriptor of the bus slave. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of
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acceptable slaves
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qcom,bus-governor:
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description:
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governor to use when scaling bus, generally any commonly
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found devfreq governor might be used. In addition to those governors,
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the custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also
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acceptable values.
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In the absence of this property the "performance" governor is used.
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qcom,bus-rage-kbps:
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description:
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an array of two items (<min max>) that indicate the
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minimum and maximum acceptable votes for the bus.
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In the absence of this property <0 INT_MAX> is used.
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qcom,ubwc-10bit:
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description:
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UBWC 10 bit content has different bus requirements,
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this tag will be used to pick the appropriate bus as per the session
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profile as shown below in example.
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required:
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- compatible
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- label
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- qcom,bus-master
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- qcom,bus-slave
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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108
bindings/msm-eva-cb.yaml
Normal file
108
bindings/msm-eva-cb.yaml
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@@ -0,0 +1,108 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-cb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP CB
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description: |
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Second level nodes - Context Banks
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-cvp,context-bank
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iommus:
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description:
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A phandle parsed by smmu driver. Number of entries will vary
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label:
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description:
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string describing iommu domain usage.
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buffer-types:
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description:
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bitmap of buffer types that can be mapped into the current IOMMU domain.
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Buffer types are defined as the following
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input = 0x1
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output = 0x2
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output2 = 0x4
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extradata input = 0x8
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extradata output = 0x10
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extradata output2 = 0x20
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internal scratch = 0x40
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internal scratch1 = 0x80
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internal scratch2 = 0x100
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internal persist = 0x200
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internal persist1 = 0x400
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internal cmd queue = 0x800
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virtual-addr-pool:
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description:
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offset and length of virtual address pool.
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qcom,fw-context-bank:
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description:
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bool indicating firmware context bank.
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qcom,secure-context-bank:
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description:
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bool indicating secure context bank.
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required:
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- compatible
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- iommus
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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79
bindings/msm-eva-heap.yaml
Normal file
79
bindings/msm-eva-heap.yaml
Normal file
@@ -0,0 +1,79 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-heap.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP HEAP
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description: |
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Second level nodes - Memory Heaps
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-vidc,mem-cdsp
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memory-region:
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description:
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phandle to the memory heap/region.
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required:
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- compatible
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- memory-region
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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||||
};
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};
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125
bindings/msm-eva.yaml
Normal file
125
bindings/msm-eva.yaml
Normal file
@@ -0,0 +1,125 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/msm-eva.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
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||||
title: Qualcomm Technologies, Inc. MSM CVP
|
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|
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description: |
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Root level node - cvp
|
||||
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properties:
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# A dictionary of DT properties for this binding schema
|
||||
compatible:
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||||
oneOf:
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||||
- items:
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||||
- enum:
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- qcom,msm-cvp
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||||
- qcom,sun-cvp
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||||
- qcom,pineapple-cvp
|
||||
- qcom,kalama-cvp
|
||||
- qcom,waipio-cvp
|
||||
- qcom,lahaina-cvp
|
||||
- qcom,kona-cvp
|
||||
|
||||
reg:
|
||||
description:
|
||||
offset and length of the CSR register set for the device.
|
||||
interrupts:
|
||||
description:
|
||||
should contain the cvp interrupt.
|
||||
qcom,reg-presets:
|
||||
description:
|
||||
list of offset-value pairs for registers to be written.
|
||||
The offsets are from the base offset specified in 'reg'. This is mainly
|
||||
used for QoS, VBIF, etc. presets for video.
|
||||
qcom,qdss-presets:
|
||||
description:
|
||||
list of physical address and memory allocation size pairs.
|
||||
when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware
|
||||
messages will be written to QDSS memory.
|
||||
‘*-supply’:
|
||||
description:
|
||||
A phandle pointing to the appropriate regulator. Number of
|
||||
regulators vary across targets.
|
||||
clock-names:
|
||||
description:
|
||||
an array of clocks that the driver is supposed to be
|
||||
manipulating. The clocks names here correspond to the clock names
|
||||
used in clk_get(<name>).
|
||||
qcom,clock-configs:
|
||||
description:
|
||||
an array of bitmaps of clocks' configurations. The index of the
|
||||
bitmap corresponds to the clock at the same index in qcom,clock-names.
|
||||
The bitmaps describes the actions that the device needs to take
|
||||
regarding the clock (i.e. scale it based on load).
|
||||
The bitmap is defined as scalable = 0x1
|
||||
(if the driver should vary the clock's frequency based on load)
|
||||
qcom,allowed-clock-rates:
|
||||
description:
|
||||
an array of supported clock rates by the chipset.
|
||||
qcom,use-non-secure-pil:
|
||||
description:
|
||||
A bool indicating which type of pil to use to load the fw.
|
||||
qcom,fw-bias:
|
||||
description:
|
||||
The address at which cvp fw is loaded (manually).
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
msm_cvp: qcom,cvp@ab00000 {
|
||||
compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
|
||||
status = "ok";
|
||||
reg = <0xab00000 0x100000>;
|
||||
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/* FIXME: LLCC Info */
|
||||
/* cache-slice-names = "vidsc0", "vidsc1"; */
|
||||
/* cache-slices = <&llcc 2>, <&llcc 3>; */
|
||||
|
||||
/* Supply */
|
||||
cvp-supply = <&mvs1_gdsc>;
|
||||
|
||||
/* Clocks */
|
||||
clock-names = "gcc_video_axi0",
|
||||
"gcc_video_axi1", "cvp_clk";
|
||||
clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
|
||||
<&clock_gcc GCC_VIDEO_AXI1_CLK>,
|
||||
<&clock_videocc VIDEO_CC_MVS1_CLK>;
|
||||
qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
|
||||
"cvp_clk";
|
||||
|
||||
qcom,clock-configs = <0x0 0x0 0x1>;
|
||||
qcom,allowed-clock-rates = <403000000 520000000
|
||||
549000000 666000000 800000000>;
|
||||
|
||||
/* Buses */
|
||||
bus_cnoc {
|
||||
compatible = "qcom,msm-cvp,bus";
|
||||
label = "cnoc";
|
||||
qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
|
||||
qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
|
||||
qcom,bus-governor = "performance";
|
||||
qcom,bus-range-kbps = <1000 1000>;
|
||||
};
|
||||
|
||||
/* MMUs */
|
||||
non_secure_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_hlos";
|
||||
iommus = <&apps_smmu 0x2120 0x400>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
buffer-types = <0xfff>;
|
||||
virtual-addr-pool = <0x4b000000 0xe0000000>;
|
||||
};
|
||||
|
||||
/* Memory Heaps */
|
||||
qcom,msm-cvp,mem_cdsp {
|
||||
compatible = "qcom,msm-cvp,mem-cdsp";
|
||||
memory-region = <&cdsp_mem>;
|
||||
};
|
||||
};
|
||||
22
pineapple-eva.dts
Normal file
22
pineapple-eva.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
#include "pineapple-eva.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. pineapple v1,v2 SoC";
|
||||
compatible = "qcom,pineapple";
|
||||
qcom,msm-id = <557 0x10000>, <557 0x20000>;
|
||||
qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>;
|
||||
};
|
||||
140
pineapple-eva.dtsi
Normal file
140
pineapple-eva.dtsi
Normal file
@@ -0,0 +1,140 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
msm_cvp: qcom,cvp@ab00000 {
|
||||
compatible = "qcom,msm-cvp", "qcom,pineapple-cvp";
|
||||
status = "ok";
|
||||
reg = <0xab00000 0x100000>;
|
||||
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/* LLCC Cache */
|
||||
cache-slice-names = "cvp";
|
||||
|
||||
/* Supply */
|
||||
cvp-supply = <&video_cc_mvs1c_gdsc>;
|
||||
cvp-core-supply = <&video_cc_mvs1_gdsc>;
|
||||
|
||||
/* Clocks */
|
||||
clock-names = "gcc_video_axi1", "sleep_clk", "cvp_clk", "core_clk",
|
||||
"video_cc_mvs1_clk_src";
|
||||
clock-ids = <GCC_VIDEO_AXI1_CLK VIDEO_CC_SLEEP_CLK VIDEO_CC_MVS1C_CLK
|
||||
VIDEO_CC_MVS1_CLK VIDEO_CC_MVS1_CLK_SRC>;
|
||||
clocks = <&gcc GCC_VIDEO_AXI1_CLK>,
|
||||
<&videocc VIDEO_CC_SLEEP_CLK>,
|
||||
<&videocc VIDEO_CC_MVS1C_CLK>,
|
||||
<&videocc VIDEO_CC_MVS1_CLK>,
|
||||
<&videocc VIDEO_CC_MVS1_CLK_SRC>;
|
||||
qcom,proxy-clock-names = "gcc_video_axi1", "sleep_clk",
|
||||
"cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
|
||||
|
||||
qcom,clock-configs = <0x0 0x0 0x0 0x0 0x1>;
|
||||
qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>;
|
||||
|
||||
resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
|
||||
<&videocc VIDEO_CC_XO_CLK_ARES>,
|
||||
<&videocc VIDEO_CC_MVS1C_CLK_ARES>;
|
||||
reset-names = "cvp_axi_reset", "cvp_xo_reset","cvp_core_reset";
|
||||
reset-power-status = <0x0 0x1 0x0>;
|
||||
|
||||
qcom,reg-presets = <0xB0088 0x0>;
|
||||
qcom,ipcc-reg = <0x400000 0x100000>;
|
||||
qcom,gcc-reg = <0x110000 0x40000>;
|
||||
|
||||
pas-id = <26>;
|
||||
memory-region = <&cvp_mem>;
|
||||
|
||||
/* UC region mapping */
|
||||
ipclite_mappings = <0xFE500000 0x100000 0x82600000>;
|
||||
/* DEVICE mapping */
|
||||
aon_timer_mappings = <0xFFA00000 0x1000 0xc220000>;
|
||||
/* DEVICE mapping */
|
||||
hwmutex_mappings = <0xFFB00000 0x2000 0x1f4a000>;
|
||||
/* DEVICE mapping */
|
||||
aon_mappings = <0xFF80F000 0x1000 0x0ABE0000>;
|
||||
|
||||
/* CVP Firmware ELF image name */
|
||||
cvp,firmware-name = "evass";
|
||||
|
||||
/* Buses */
|
||||
cvp_cnoc {
|
||||
compatible = "qcom,msm-cvp,bus";
|
||||
qcom,bus-governor = "performance";
|
||||
qcom,bus-range-kbps = <1000 1000>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>;
|
||||
interconnect-names = "eva-cfg";
|
||||
};
|
||||
|
||||
cvp_bus_ddr {
|
||||
compatible = "qcom,msm-cvp,bus";
|
||||
qcom,bus-governor = "performance";
|
||||
qcom,bus-range-kbps = <1000 6533000>;
|
||||
interconnects = <&mmss_noc MASTER_VIDEO_PROC &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "eva-ddr";
|
||||
};
|
||||
|
||||
/* MMUs */
|
||||
/* Camera cb is used to get secure camera buffer IPA */
|
||||
cvp_camera_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_camera";
|
||||
buffer-types = <0xfff>;
|
||||
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_EVA_CB>;
|
||||
};
|
||||
|
||||
non_secure_cb_group: cvp_non_secure_cb_group {
|
||||
qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
};
|
||||
|
||||
cvp_non_secure_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_hlos";
|
||||
iommus =
|
||||
<&apps_smmu 0x1920 0x0000>;
|
||||
buffer-types = <0xfff>;
|
||||
dma-coherent;
|
||||
qcom,iommu-group = <&non_secure_cb_group>;
|
||||
};
|
||||
|
||||
|
||||
cvp_secure_nonpixel_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_sec_nonpixel";
|
||||
iommus =
|
||||
<&apps_smmu 0x1924 0x0000>;
|
||||
buffer-types = <0x741>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
|
||||
qcom,iommu-vmid = <0xB>;
|
||||
};
|
||||
|
||||
cvp_secure_pixel_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_sec_pixel";
|
||||
iommus =
|
||||
<&apps_smmu 0x1923 0x0000>;
|
||||
buffer-types = <0x106>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
|
||||
qcom,iommu-vmid = <0xA>;
|
||||
};
|
||||
|
||||
cvp_dsp_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_dsp";
|
||||
iommus =
|
||||
<&apps_smmu 0x1920 0x0000>;
|
||||
buffer-types = <0xfff>;
|
||||
qcom,iommu-group = <&non_secure_cb_group>;
|
||||
};
|
||||
|
||||
/* Memory Heaps */
|
||||
qcom,msm-cvp,mem_cdsp {
|
||||
compatible = "qcom,msm-cvp,mem-cdsp";
|
||||
memory-region = <&cdsp_eva_mem>;
|
||||
};
|
||||
};
|
||||
};
|
||||
23
sun-eva-v2.dts
Normal file
23
sun-eva-v2.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,evacc-sun.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
#include "sun-eva.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun v2 SoC";
|
||||
compatible = "qcom,sun";
|
||||
qcom,msm-id = <618 0x20000>, <639 0x20000>;
|
||||
qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>;
|
||||
};
|
||||
11
sun-eva-v2.dtsi
Normal file
11
sun-eva-v2.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-eva.dtsi"
|
||||
|
||||
&msm_cvp {
|
||||
qcom,allowed-clock-rates = <350000000 400000000 450000000 500000000 550000000>;
|
||||
};
|
||||
|
||||
23
sun-eva.dts
Normal file
23
sun-eva.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,evacc-sun.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
#include "sun-eva.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. sun v1 SoC";
|
||||
compatible = "qcom,sun";
|
||||
qcom,msm-id = <618 0x10000>, <639 0x10000>;
|
||||
qcom,board-id = <0 0>, <15 0>, <8 0>, <11 0>, <1 0>;
|
||||
};
|
||||
150
sun-eva.dtsi
Normal file
150
sun-eva.dtsi
Normal file
@@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
msm_cvp: qcom,cvp@ab00000 {
|
||||
compatible = "qcom,msm-cvp", "qcom,sun-cvp";
|
||||
status = "ok";
|
||||
reg = <0xab00000 0x100000>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/* LLCC Cache */
|
||||
cache-slice-names = "cvp";
|
||||
|
||||
/* Supply */
|
||||
cvp-supply = <&eva_cc_mvs0c_gdsc>;
|
||||
cvp-core-supply = <&eva_cc_mvs0_gdsc>;
|
||||
|
||||
/* Clocks */
|
||||
clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", "cvp_freerun_clk", "core_freerun_clk",
|
||||
"cvp_clk", "core_clk","eva_cc_mvs0_clk_src";
|
||||
clock-ids = <GCC_EVA_AXI0C_CLK GCC_EVA_AXI0_CLK EVA_CC_SLEEP_CLK EVA_CC_MVS0C_FREERUN_CLK EVA_CC_MVS0_FREERUN_CLK EVA_CC_MVS0C_CLK
|
||||
EVA_CC_MVS0_CLK EVA_CC_MVS0_CLK_SRC>;
|
||||
clocks = <&gcc GCC_EVA_AXI0C_CLK>,
|
||||
<&gcc GCC_EVA_AXI0_CLK>,
|
||||
<&evacc EVA_CC_SLEEP_CLK>,
|
||||
<&evacc EVA_CC_MVS0C_FREERUN_CLK>,
|
||||
<&evacc EVA_CC_MVS0_FREERUN_CLK>,
|
||||
<&evacc EVA_CC_MVS0C_CLK>,
|
||||
<&evacc EVA_CC_MVS0_CLK>,
|
||||
<&evacc EVA_CC_MVS0_CLK_SRC>;
|
||||
qcom,proxy-clock-names = "cvp_axi_clock", "core_axi_clock", "sleep_clk", "cvp_freerun_clk", "core_freerun_clk",
|
||||
"cvp_clk", "core_clk", "eva_cc_mvs0_clk_src";
|
||||
|
||||
qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1>;
|
||||
qcom,allowed-clock-rates = <350000000 400000000 450000000 500000000 550000000>;
|
||||
|
||||
/*To be added - GCC_EVA CLK_ARES and GCC_EVA_AXI0C_CLK_ARES*/
|
||||
resets = <&evacc EVA_CC_MVS0C_CLK_ARES>;
|
||||
reset-names = "cvp_core_reset";
|
||||
reset-power-status = <0x0>;
|
||||
|
||||
qcom,reg-presets = <0xB0088 0x0>;
|
||||
qcom,ipcc-reg = <0x400000 0x100000>;
|
||||
qcom,gcc-reg = <0x110000 0x90000>;
|
||||
|
||||
pas-id = <26>;
|
||||
memory-region = <&cvp_mem>;
|
||||
|
||||
/* UC region mapping */
|
||||
ipclite_mappings = <0xFE500000 0x100000 0x82600000>;
|
||||
/* DEVICE mapping */
|
||||
aon_timer_mappings = <0xFFA00000 0x1000 0xc220000>;
|
||||
/* DEVICE mapping */
|
||||
hwmutex_mappings = <0xFFB00000 0x2000 0x1f4a000>;
|
||||
/* DEVICE mapping */
|
||||
aon_mappings = <0xFF80F000 0x1000 0x0ABE0000>;
|
||||
|
||||
/* CVP Firmware ELF image name */
|
||||
cvp,firmware-name = "evass";
|
||||
|
||||
/* Buses */
|
||||
cvp_cnoc {
|
||||
compatible = "qcom,msm-cvp,bus";
|
||||
qcom,bus-governor = "performance";
|
||||
qcom,bus-range-kbps = <1000 1000>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_EVA_CFG>;
|
||||
interconnect-names = "eva-cfg";
|
||||
};
|
||||
|
||||
cvp_bus_ddr {
|
||||
compatible = "qcom,msm-cvp,bus";
|
||||
qcom,bus-governor = "performance";
|
||||
qcom,bus-range-kbps = <1000 6533000>;
|
||||
interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "eva-ddr";
|
||||
};
|
||||
|
||||
/* MMUs */
|
||||
/* Camera cb is used to get secure camera buffer IPA */
|
||||
cvp_camera_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_camera";
|
||||
buffer-types = <0xfff>;
|
||||
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_EVA_CB>;
|
||||
};
|
||||
|
||||
non_secure_cb_group: cvp_non_secure_cb_group {
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
};
|
||||
|
||||
cvp_iommu_region_partition: cvp_iommu_region_partition {
|
||||
/* These IOVA regions are unique per context bank */
|
||||
iommu-addresses = <&cvp_non_secure_cb 0x0 0x4b000000>, <&cvp_non_secure_cb 0xdb000000 0x25000000>,
|
||||
<&cvp_dsp_cb 0x0 0x4b000000>, <&cvp_dsp_cb 0xdb000000 0x25000000>,
|
||||
<&cvp_secure_nonpixel_cb 0x0 0x01000000>, <&cvp_secure_nonpixel_cb 0x26800000 0xd9800000>,
|
||||
<&cvp_secure_pixel_cb 0x0 0x26800000>, <&cvp_secure_pixel_cb 0x4b000000 0xb5000000>;
|
||||
};
|
||||
|
||||
cvp_non_secure_cb: cvp_non_secure_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_hlos";
|
||||
iommus =
|
||||
<&apps_smmu 0x1920 0x0020>;
|
||||
buffer-types = <0xfff>;
|
||||
dma-coherent;
|
||||
qcom,iommu-group = <&non_secure_cb_group>;
|
||||
memory-region = <&cvp_iommu_region_partition>;
|
||||
};
|
||||
|
||||
|
||||
cvp_secure_nonpixel_cb: cvp_secure_nonpixel_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_sec_nonpixel";
|
||||
iommus =
|
||||
<&apps_smmu 0x1924 0x0020>;
|
||||
buffer-types = <0x741>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
memory-region = <&cvp_iommu_region_partition>;
|
||||
qcom,iommu-vmid = <0xB>;
|
||||
};
|
||||
|
||||
cvp_secure_pixel_cb: cvp_secure_pixel_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_sec_pixel";
|
||||
iommus =
|
||||
<&apps_smmu 0x1923 0x0000>;
|
||||
buffer-types = <0x106>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
memory-region = <&cvp_iommu_region_partition>;
|
||||
qcom,iommu-vmid = <0xA>;
|
||||
};
|
||||
|
||||
cvp_dsp_cb: cvp_dsp_cb {
|
||||
compatible = "qcom,msm-cvp,context-bank";
|
||||
label = "cvp_dsp";
|
||||
iommus =
|
||||
<&apps_smmu 0x1920 0x0020>;
|
||||
buffer-types = <0xfff>;
|
||||
qcom,iommu-group = <&non_secure_cb_group>;
|
||||
memory-region = <&cvp_iommu_region_partition>;
|
||||
};
|
||||
/* Memory Heaps */
|
||||
qcom,msm-cvp,mem_cdsp {
|
||||
compatible = "qcom,msm-cvp,mem-cdsp";
|
||||
memory-region = <&cdsp_eva_mem>;
|
||||
};
|
||||
};
|
||||
};
|
||||
21
trustedvm-kalama-eva-mtp.dts
Normal file
21
trustedvm-kalama-eva-mtp.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include "trustedvm-kalama-eva.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP";
|
||||
compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>;
|
||||
qcom,board-id = <0x10008 0>;
|
||||
};
|
||||
21
trustedvm-kalama-eva-qrd.dts
Normal file
21
trustedvm-kalama-eva-qrd.dts
Normal file
@@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/interconnect/qcom,kalama.h>
|
||||
#include <dt-bindings/clock/qcom,videocc-kalama.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kalama.h>
|
||||
#include "trustedvm-kalama-eva.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama QRD";
|
||||
compatible = "qcom,kalama-qrd", "qcom,kalama", "qcom,qrd";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>;
|
||||
qcom,board-id = <0x1000B 0>;
|
||||
};
|
||||
11
trustedvm-kalama-eva.dtsi
Normal file
11
trustedvm-kalama-eva.dtsi
Normal file
@@ -0,0 +1,11 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
msm_cvp: qcom,cvp@ab00000 {
|
||||
compatible = "qcom,msm-cvp", "qcom,kalama-cvp-tvm";
|
||||
status = "ok";
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user