ARM: dts: msm: Initial EVA device tree
Initial draft with required markings. Change-Id: I36651f21d1770c61d83128f5283c5eaffe3679d6 Signed-off-by: Jingjing Guo <quic_jig@quicinc.com> Signed-off-by: George Shen <quic_sqiao@quicinc.com>
This commit is contained in:
George Shen
107
bindings/msm-eva-bus.yaml
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107
bindings/msm-eva-bus.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP BUS
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description: |
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Second level nodes - Buses
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-cvp,bus
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label:
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description: an arbitrary name
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qcom,bus-master:
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description:
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an integer descriptor of the bus master. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of
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acceptable masters
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qcom,bus-slave:
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description:
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an integer descriptor of the bus slave. Refer to arch/arm/\
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boot/dts/include/dt-bindings/msm/msm-bus-ids.h for list of
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acceptable slaves
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qcom,bus-governor:
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description:
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governor to use when scaling bus, generally any commonly
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found devfreq governor might be used. In addition to those governors,
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the custom Venus governors, "msm-vidc-ddr" or "msm-vidc-llcc" are also
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acceptable values.
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In the absence of this property the "performance" governor is used.
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qcom,bus-rage-kbps:
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description:
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an array of two items (<min max>) that indicate the
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minimum and maximum acceptable votes for the bus.
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In the absence of this property <0 INT_MAX> is used.
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qcom,ubwc-10bit:
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description:
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UBWC 10 bit content has different bus requirements,
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this tag will be used to pick the appropriate bus as per the session
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profile as shown below in example.
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required:
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- compatible
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- label
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- qcom,bus-master
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- qcom,bus-slave
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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108
bindings/msm-eva-cb.yaml
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108
bindings/msm-eva-cb.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-cb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP CB
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description: |
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Second level nodes - Context Banks
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-cvp,context-bank
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iommus:
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description:
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A phandle parsed by smmu driver. Number of entries will vary
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label:
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description:
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string describing iommu domain usage.
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buffer-types:
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description:
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bitmap of buffer types that can be mapped into the current IOMMU domain.
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Buffer types are defined as the following
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input = 0x1
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output = 0x2
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output2 = 0x4
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extradata input = 0x8
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extradata output = 0x10
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extradata output2 = 0x20
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internal scratch = 0x40
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internal scratch1 = 0x80
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internal scratch2 = 0x100
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internal persist = 0x200
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internal persist1 = 0x400
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internal cmd queue = 0x800
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virtual-addr-pool:
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description:
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offset and length of virtual address pool.
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qcom,fw-context-bank:
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description:
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bool indicating firmware context bank.
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qcom,secure-context-bank:
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description:
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bool indicating secure context bank.
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required:
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- compatible
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- iommus
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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79
bindings/msm-eva-heap.yaml
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79
bindings/msm-eva-heap.yaml
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@@ -0,0 +1,79 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva-heap.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP HEAP
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description: |
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Second level nodes - Memory Heaps
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-vidc,mem-cdsp
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memory-region:
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description:
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phandle to the memory heap/region.
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required:
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- compatible
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- memory-region
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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125
bindings/msm-eva.yaml
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125
bindings/msm-eva.yaml
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@@ -0,0 +1,125 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/msm-eva.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. MSM CVP
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description: |
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Root level node - cvp
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properties:
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# A dictionary of DT properties for this binding schema
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm-cvp
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- qcom,sun-cvp
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- qcom,pineapple-cvp
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- qcom,kalama-cvp
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- qcom,waipio-cvp
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- qcom,lahaina-cvp
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- qcom,kona-cvp
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reg:
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description:
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offset and length of the CSR register set for the device.
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interrupts:
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description:
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should contain the cvp interrupt.
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qcom,reg-presets:
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description:
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list of offset-value pairs for registers to be written.
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The offsets are from the base offset specified in 'reg'. This is mainly
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used for QoS, VBIF, etc. presets for video.
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qcom,qdss-presets:
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description:
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list of physical address and memory allocation size pairs.
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when fw_debug_mode is set as HFI_DEBUG_MODE_QDSS, all firmware
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messages will be written to QDSS memory.
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‘*-supply’:
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description:
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A phandle pointing to the appropriate regulator. Number of
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regulators vary across targets.
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clock-names:
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description:
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an array of clocks that the driver is supposed to be
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manipulating. The clocks names here correspond to the clock names
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used in clk_get(<name>).
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qcom,clock-configs:
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description:
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an array of bitmaps of clocks' configurations. The index of the
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bitmap corresponds to the clock at the same index in qcom,clock-names.
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The bitmaps describes the actions that the device needs to take
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regarding the clock (i.e. scale it based on load).
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The bitmap is defined as scalable = 0x1
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(if the driver should vary the clock's frequency based on load)
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qcom,allowed-clock-rates:
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description:
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an array of supported clock rates by the chipset.
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qcom,use-non-secure-pil:
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description:
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A bool indicating which type of pil to use to load the fw.
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qcom,fw-bias:
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description:
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The address at which cvp fw is loaded (manually).
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required:
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- compatible
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examples:
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- |
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msm_cvp: qcom,cvp@ab00000 {
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compatible = "qcom,msm-cvp", "qcom,Lahaina-cvp";
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status = "ok";
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reg = <0xab00000 0x100000>;
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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/* FIXME: LLCC Info */
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/* cache-slice-names = "vidsc0", "vidsc1"; */
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/* cache-slices = <&llcc 2>, <&llcc 3>; */
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/* Supply */
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cvp-supply = <&mvs1_gdsc>;
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/* Clocks */
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clock-names = "gcc_video_axi0",
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"gcc_video_axi1", "cvp_clk";
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clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
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<&clock_gcc GCC_VIDEO_AXI1_CLK>,
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<&clock_videocc VIDEO_CC_MVS1_CLK>;
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qcom,proxy-clock-names = "gcc_video_axi0", "gcc_video_axi1",
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"cvp_clk";
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qcom,clock-configs = <0x0 0x0 0x1>;
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qcom,allowed-clock-rates = <403000000 520000000
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549000000 666000000 800000000>;
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/* Buses */
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bus_cnoc {
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compatible = "qcom,msm-cvp,bus";
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label = "cnoc";
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qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
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qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
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qcom,bus-governor = "performance";
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qcom,bus-range-kbps = <1000 1000>;
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};
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/* MMUs */
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non_secure_cb {
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compatible = "qcom,msm-cvp,context-bank";
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label = "cvp_hlos";
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iommus = <&apps_smmu 0x2120 0x400>;
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qcom,iommu-dma = "disabled";
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buffer-types = <0xfff>;
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virtual-addr-pool = <0x4b000000 0xe0000000>;
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};
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/* Memory Heaps */
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qcom,msm-cvp,mem_cdsp {
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compatible = "qcom,msm-cvp,mem-cdsp";
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memory-region = <&cdsp_mem>;
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};
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};
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