ARM: dts: msm: Mark GCC clock node as GenPD provider
Mark GCC clock node as GenPD provider and disable the PCIE GDSC regulator nodes. Change-Id: I98fc6709592c393259da77443d4b6e580e61a0b8 Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
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@@ -1731,6 +1731,7 @@
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"ufs_phy_tx_symbol_0_clk",
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"ufs_phy_tx_symbol_0_clk",
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"usb3_phy_wrapper_gcc_usb30_pipe_clk";
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"usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <1>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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#reset-cells = <1>;
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};
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};
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@@ -1958,6 +1959,7 @@
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qcom,no-status-check-on-disable;
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qcom,no-status-check-on-disable;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
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qcom,support-cfg-gdscr;
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qcom,support-cfg-gdscr;
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status = "disabled";
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};
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};
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gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
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gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
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@@ -1969,6 +1971,7 @@
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qcom,no-status-check-on-disable;
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qcom,no-status-check-on-disable;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
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qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
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qcom,support-cfg-gdscr;
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qcom,support-cfg-gdscr;
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status = "disabled";
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};
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};
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gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
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gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
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