From 65cfdc0dfc7e4f19ad6293b01d758905515d3312 Mon Sep 17 00:00:00 2001 From: Balaji Vekatesh Kalkonda Date: Tue, 12 Nov 2024 14:46:13 +0530 Subject: [PATCH 01/67] ARM: dts: msm: Enable touch for ravelin vm Add focaltech touch support to ravelin vm. Change-Id: Ie3c1399541929f6b0a3059ee41689b3f5ddc4a7d Signed-off-by: Balaji Vekatesh Kalkonda --- qcom/ravelin-idp.dtsi | 15 ++++++++------- qcom/ravelin-pinctrl.dtsi | 2 +- qcom/ravelin-vm-idp.dtsi | 17 ++++++++++------- qcom/ravelin-vm.dtsi | 4 ++-- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/qcom/ravelin-idp.dtsi b/qcom/ravelin-idp.dtsi index 0c8d1e32..458213b8 100644 --- a/qcom/ravelin-idp.dtsi +++ b/qcom/ravelin-idp.dtsi @@ -72,19 +72,20 @@ focaltech,max-touch-number = <10>; focaltech,ic-type = <0x8726081C>; focaltech,touch-type = "primary"; + focaltech,qts_en; pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release"; pinctrl-0 = <&ts_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; pinctrl-2 = <&ts_release>; - focaltech,trusted-touch-mode = "vm_mode"; - focaltech,touch-environment = "pvm"; - focaltech,trusted-touch-type = "primary"; - focaltech,trusted-touch-spi-irq = <566>; - focaltech,trusted-touch-io-bases = <0x984000 0x910000>; - focaltech,trusted-touch-io-sizes = <0x1000 0x4000>; - focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <566>; + qts,trusted-touch-io-bases = <0x984000 0x910000>; + qts,trusted-touch-io-sizes = <0x1000 0x4000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0x2008>; }; }; diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi index c999ebb9..e0aed3ad 100644 --- a/qcom/ravelin-pinctrl.dtsi +++ b/qcom/ravelin-pinctrl.dtsi @@ -1407,7 +1407,7 @@ tuivm { qcom,label = <0x08>; qcom,vmid = <45>; - tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0>; + tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0 &tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0x2008>; }; }; }; diff --git a/qcom/ravelin-vm-idp.dtsi b/qcom/ravelin-vm-idp.dtsi index fd0e6de3..99f4df4d 100644 --- a/qcom/ravelin-vm-idp.dtsi +++ b/qcom/ravelin-vm-idp.dtsi @@ -9,6 +9,7 @@ &qupv3_se1_i2c { status = "ok"; focaltech@38 { + compatible = "focaltech,fts_ts"; reg = <0x38>; focaltech,display-coords = <0 0 1080 2408>; focaltech,max-touch-number = <5>; @@ -16,13 +17,15 @@ focaltech,reset-gpio-base = <0xF10C000>; focaltech,intr-gpio-base = <0xF10D000>; - focaltech,trusted-touch-mode = "vm_mode"; - focaltech,touch-environment = "tvm"; - focaltech,trusted-touch-type = "primary"; - focaltech,trusted-touch-spi-irq = <566>; - focaltech,trusted-touch-io-bases = <0x984000 0x910000>; - focaltech,trusted-touch-io-sizes = <0x1000 0x4000>; - focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + focaltech,touch-type = "primary"; + focaltech,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <566>; + qts,trusted-touch-io-bases = <0x984000 0x910000>; + qts,trusted-touch-io-sizes = <0x1000 0x4000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0x2008>; }; }; diff --git a/qcom/ravelin-vm.dtsi b/qcom/ravelin-vm.dtsi index 9fb48b09..abfbde71 100644 --- a/qcom/ravelin-vm.dtsi +++ b/qcom/ravelin-vm.dtsi @@ -45,11 +45,11 @@ tlmm: pinctrl@f000000 { compatible = "qcom,ravelin-vm-tlmm"; - gpios = /bits/ 16 <92 93>; + gpios = /bits/ 16 <92 93 10 11 12 13>; }; tlmm-vm-mem-access { - tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0>; + tlmm-vm-gpio-list = <&tlmm 92 0 &tlmm 93 0 &tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0x2008>; }; apps-smmu@15000000 { From ff00dbbf4d71aabfe6c5fa8d55090036a17deab2 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Wed, 27 Nov 2024 14:37:20 +0530 Subject: [PATCH 02/67] ARM: dts: msm: add trusted touch properties for kera Add trusted touch properties for tuna on CDP, MTP platforms. Change-Id: I93d85e4b21387835cffc08ebfd7376cb1d98f95d Signed-off-by: Rajeev Nandan --- qcom/kera-vm-cdp.dtsi | 23 +++++++++++++++++++++++ qcom/kera-vm-mtp.dtsi | 23 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/qcom/kera-vm-cdp.dtsi b/qcom/kera-vm-cdp.dtsi index 1510613d..10bb9113 100644 --- a/qcom/kera-vm-cdp.dtsi +++ b/qcom/kera-vm-cdp.dtsi @@ -5,3 +5,26 @@ &soc { }; + +&qupv3_se8_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/kera-vm-mtp.dtsi b/qcom/kera-vm-mtp.dtsi index 1510613d..10bb9113 100644 --- a/qcom/kera-vm-mtp.dtsi +++ b/qcom/kera-vm-mtp.dtsi @@ -5,3 +5,26 @@ &soc { }; + +&qupv3_se8_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; From 2f8a55af97a5bc3a7c65014ec6c4f5df276db891 Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Wed, 27 Nov 2024 16:21:25 +0530 Subject: [PATCH 03/67] ARM: dts: msm: Add IMS channel GLINK nodes for tuna Add Glink Pkt nodes for Ims_dc_sub1 and Ims_dc_sub2 channels for Tuna. Add the nodes and corresponding channel devices to enable GLINK communication from userspace. Change-Id: I8473c5c505bd75b2d2abfd5c8a601cd86121d1f7 Signed-off-by: Sarannya S --- qcom/tuna.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 2573e634..880ddb8c 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1201,6 +1201,20 @@ qcom,glinkpkt-ch-name = "bt_cp_ctrl"; qcom,glinkpkt-dev-name = "bt_cp_ctrl"; }; + + qcom,glinkpkt-ims-sub-1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "Ims_dc_sub1"; + qcom,glinkpkt-dev-name = "ims_dc_sub1"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-ims-sub-2 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "Ims_dc_sub2"; + qcom,glinkpkt-dev-name = "ims_dc_sub2"; + qcom,glinkpkt-enable-ch-close; + }; }; sys-pm-vx@c320000 { From 54ba72a96787127bbb8d6f1918f6c57a2ed30ea8 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Tue, 3 Dec 2024 18:11:21 +0530 Subject: [PATCH 04/67] ARM: dts: msm: Update bootargs for kera pre-sil Update bootargs to make it compatible with pre-sil. Change-Id: Ifed16d126603556a1a4e11e4ce4a630d8a50c978 Signed-off-by: Wasim Nazir --- qcom/kera-rumi.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 4a1f5de8..e3de2e0e 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -6,6 +6,10 @@ #include #include +&chosen { + bootargs = "printk.devkmsg=on loglevel=8 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 irqaffinity=0-2 firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware ftrace_dump_on_oops slub_debug=- cpufreq.default_governor=performance"; +}; + &arch_timer { clock-frequency = <500000>; }; From 55b5f1bfb0e721325494a42c81dd1f0692e0e8b2 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Wed, 4 Dec 2024 12:08:12 +0530 Subject: [PATCH 05/67] ARM: dts: msm: Add GLINK PKT loopback node for tuna GLINK PKT provides a userspace interface to RPMSG GLINK through character device nodes. Add the loopback node and corresponding channel device to enable GLINK communication from userspace to communicate with loopback test server. Change-Id: I2ba608d21b3898f77857035fb214bcb8e49bb596 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index f1ecb6ae..d95b1c99 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1167,6 +1167,42 @@ qcom,glinkpkt-dev-name = "at_mdm0"; }; + qcom,glinkpkt-ctrl-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp"; + }; + + qcom,glinkpkt-data-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp"; + }; + + qcom,glinkpkt-ctrl-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_lpass"; + }; + + qcom,glinkpkt-data-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_lpass"; + }; + + qcom,glinkpkt-ctrl-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_mpss"; + }; + + qcom,glinkpkt-data-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_mpss"; + }; + qcom,glinkpkt-apr-apps2 { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "apr_apps2"; From 50c69b12a5c08426281cf1416df55513692c91d6 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 18 Nov 2024 15:03:49 +0530 Subject: [PATCH 06/67] ARM: dts: msm: Add power domain and interconnect for kgsl-smmu Replace regulators with per-device genpd power domain and add interconnect for kgsl-smmu on kera. Change-Id: Ifcb5f866a49383b502ca9c39148fc20de46ac588 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-kera.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi index c3fe3578..68542a90 100644 --- a/qcom/msm-arm-smmu-kera.dtsi +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -17,8 +17,13 @@ ranges; dma-coherent; - qcom,regulator-names = "vdd"; - vdd-supply = <&gpu_cc_cx_gdsc>; + /* + * When gdsc is enabled, and cpu enters cpuidle, DDR + * bandwidth vote must be present to prevent DDR + * shutdown. + */ + power-domains = <&gpucc GPU_CC_CX_SMMU_GDSC>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = From 10436a9ccec759447cfacc00b60f96e6bcd815ad Mon Sep 17 00:00:00 2001 From: Prakash Yadachi Date: Thu, 28 Nov 2024 14:29:23 +0530 Subject: [PATCH 07/67] ARM: dts: msm: Update static gpii mask for ravelin-vm Currently, the static gpii mask for gpi_dma0 is incorrectly set to 0x20, which is resulting in i2c read failure. To prevent this i2c read failure, the static gpii mask value for gpi_dma0 needs to be updated to 0x40. 'Fixes: 5d97d9eda4527 ("ARM: dts: msm: Add memory and clock support for vm ravelin")'. Change-Id: I4f1785b1f1544e436e511af2622ccf365f3cbcfe Signed-off-by: Prakash Yadachi --- qcom/ravelin-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/ravelin-vm.dtsi b/qcom/ravelin-vm.dtsi index 28d80bae..75f91a59 100644 --- a/qcom/ravelin-vm.dtsi +++ b/qcom/ravelin-vm.dtsi @@ -103,7 +103,7 @@ , ; qcom,max-num-gpii = <12>; - qcom,static-gpii-mask = <0x20>; + qcom,static-gpii-mask = <0x40>; qcom,gpii-mask = <0x0>; qcom,ev-factor = <2>; qcom,gpi-ee-offset = <0x10000>; From 2edfcbba9ba430feda78a3fc7b6e07cd2b2ad5a7 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Sat, 16 Nov 2024 19:05:46 +0530 Subject: [PATCH 08/67] ARM: dts: msm: Disable mem-offline node Temporarily disable mem-offline node in tuna to resolve bootup crash due to page allocation from movable zone. The bad page state was reported for Movable zone [ 84.281664][ T1622] BUG: Bad page state in process Jit thread pool pfn:a22bfe [ 84.291750][ T1622] page:fffffffe268aff80 refcount:-1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0xa22bfe [ 84.301978][ T1622] flags: 0x4000000000000000(zone=2|kasantag=0x0) [ 84.312225][ T1622] page_type: 0xffffffff() [ 84.342884][ T1622] page dumped because: nonzero _refcount [ 84.385712][ T1622] page last allocated via order 0, migratetype Unmovable, gfp_mask 0x140dc2(GFP_HIGHUSER|GFP_COMP|GFP_ZERO),pid1462, tgid 1434 (binder:1434_1), ts 73871020589, free_ts 82485610563 This fixes the bootup crash by TAO preventing page allocation from movable zone but will land in QCOM branches through LTS. Once landed revert back this temporary change. Change-Id: Ibde1fab99236e3d44356ba412d53eac8da4cee03 Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 905c3a88..217f3077 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -82,6 +82,7 @@ offline-sizes = <0x2 0xc0000000 0x1 0x0>; granule = <512>; qcom,qmp = <&aoss_qmp>; + status = "disabled"; }; firmware: firmware { From 3393b24703ed38bddb83750e3ca32d093234978f Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Mon, 2 Dec 2024 18:20:21 +0530 Subject: [PATCH 09/67] ARM: dts: msm: Add eUSB2 repeater nodes for kera Add the eUSB2 repeater node and references for PM7550BA and PMIV010x. pm7550ba -> ATP and MTP. pmib010x -> QRD and CDP. Change-Id: If971486537915c1f3b8e13a66d294e1fef2596cd Signed-off-by: Uttkarsh Aggarwal --- qcom/kera-pm7550ba.dtsi | 10 ++++++++++ qcom/kera-pmiv0102.dtsi | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/qcom/kera-pm7550ba.dtsi b/qcom/kera-pm7550ba.dtsi index acd6f6ef..2c05b1c3 100644 --- a/qcom/kera-pm7550ba.dtsi +++ b/qcom/kera-pm7550ba.dtsi @@ -65,3 +65,13 @@ }; }; +&pm7550ba_eusb2_repeater { + vdd18-supply = <&L7B>; + vdd3-supply = <&L17B>; + status = "ok"; +}; + +&eusb2_phy0 { + dummy-supply = <&pm7550ba_eusb2_repeater>; + usb-repeater = <&pm7550ba_eusb2_repeater>; +}; diff --git a/qcom/kera-pmiv0102.dtsi b/qcom/kera-pmiv0102.dtsi index f933587c..9d63b135 100644 --- a/qcom/kera-pmiv0102.dtsi +++ b/qcom/kera-pmiv0102.dtsi @@ -12,3 +12,14 @@ &pmiv010x_amoled_ecm { status = "ok"; }; + +&pmiv010x_eusb2_repeater { + vdd18-supply = <&L7B>; + vdd3-supply = <&L17B>; + status = "ok"; +}; + +&eusb2_phy0 { + dummy-supply = <&pmiv010x_eusb2_repeater>; + usb-repeater = <&pmiv010x_eusb2_repeater>; +}; From 43b24ab52e11bf39e466de4cc8834b7801261214 Mon Sep 17 00:00:00 2001 From: songchai Date: Thu, 5 Dec 2024 13:53:41 +0800 Subject: [PATCH 10/67] ARM: dts: msm: enable tpdm-eva and funnel-eva for tuna enable tpdm-eva and funnel-eva for tuna. Change-Id: Ia9e1e703087bbcf70a3f7097541cfa6a3b18647e Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index a43b3421..74a9a90c 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -402,7 +402,6 @@ coresight-name = "coresight-tpdm-eva"; - status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -426,7 +425,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; in-ports { #address-cells = <1>; From b70023c975fbabe8d0fa78129bcb8d1953b025ea Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 5 Dec 2024 14:34:06 +0530 Subject: [PATCH 11/67] ARM: dts: msm: Update ref_clk_src for kera UFS 2.x platforms Update ref_clk_src to source 19.2MHz clock to UFS 2.x Platforms. Change-Id: I0f8a2307bc700a4eac2caa5e9ff5d0bfaac1b163 Signed-off-by: Manish Pandey --- qcom/kera_ufs2.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi index 1ed18475..320ed23f 100644 --- a/qcom/kera_ufs2.dtsi +++ b/qcom/kera_ufs2.dtsi @@ -2,6 +2,9 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include +#include &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-niobe"; @@ -21,6 +24,20 @@ vdda-qref-supply = <&L2B>; vdda-qref-max-microamp = <1890>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + status = "ok"; }; From 11f3cec519f9f7a455d5150893dabeaea964b845 Mon Sep 17 00:00:00 2001 From: Shivangi Kesharwani Date: Thu, 5 Dec 2024 03:13:55 -0800 Subject: [PATCH 12/67] ARM: dts: msm: added secure indicator UID Added secure indicator UID in dts to provide access. Signed-off-by: Shivangi Kesharwani --- qcom/waipio-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index 80e2cdda..36ec422f 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -87,7 +87,7 @@ vendor = "QTI"; image-name = "qcom,trustedvm"; qcom,pasid = <0x0 0x1c>; - qcom,qtee-config-info = "p=7C,8F,97,159,199,7F1;"; + qcom,qtee-config-info = "p=7C,8F,97,C8,159,199,7F1;"; qcom,secdomain-ids = <45>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/trusted-ui"; From 7856b5430d45d7314e5d3167cde8368908b3b942 Mon Sep 17 00:00:00 2001 From: kundan kumar Date: Thu, 7 Nov 2024 16:06:24 +0530 Subject: [PATCH 13/67] ARM: dts: qcom: Add smcinvoke, qcedev and qrng nodes for sdxkova Test: build compilation device bootup. Change-Id: Ib9e3b1dea78507a28d74be0c8e51643a7cfa9e6a Signed-off-by: kundan kumar --- qcom/sdxkova.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index bf3ad21f..fc542c6e 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1245,6 +1245,10 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; }; + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + }; #include "sdxkova-regulators.dtsi" @@ -1577,6 +1581,41 @@ }; }; +qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x28000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0020 0x0>, + <&apps_smmu 0x0021 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0021 0x0>; + dma-coherent; + }; + }; + + qcom_rng: qrng@10c3000 { + compatible = "qcom,msm-rng"; + reg = <0x10c3000 0x1000>; + qcom,no-qrng-config; + qcom,no-clock-support; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,aoss-qmp"; reg = <0x0 0xc310000 0x0 0x1000>; From cd6546be23bffc909bbc014c38e2f7dd3dc2c9d2 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Thu, 5 Dec 2024 18:07:58 +0530 Subject: [PATCH 14/67] ARM: dts: msm: Add moselle based QRD platform in kera Add support for QRD platform which uses moselle attach with UFS2 in kera. Change-Id: Idc6b8cf4418bda35e5d3b047e980370625ab00b6 Signed-off-by: Wasim Nazir --- qcom/Makefile | 1 + qcom/kera-qrd-qca6750-ufs2-overlay.dts | 17 +++++++++++++++++ qcom/kera-qrd-qca6750-ufs2.dtsi | 7 +++++++ qcom/platform_map.bzl | 1 + 4 files changed, 26 insertions(+) create mode 100644 qcom/kera-qrd-qca6750-ufs2-overlay.dts create mode 100644 qcom/kera-qrd-qca6750-ufs2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 51ca4378..ed06ed4a 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -92,6 +92,7 @@ KERA_BOARDS += \ kera-qrd-wcn7750-ufs4-overlay.dtbo \ kera-qrd-wcn7750-ufs2-overlay.dtbo \ kera-qrd-wcn7750-ufs3-overlay.dtbo \ + kera-qrd-qca6750-ufs2-overlay.dtbo \ kera-rcm-qca6750-ufs4-overlay.dtbo \ kera-rcm-qca6750-ufs2-overlay.dtbo \ kera-rcm-qca6750-ufs3-overlay.dtbo \ diff --git a/qcom/kera-qrd-qca6750-ufs2-overlay.dts b/qcom/kera-qrd-qca6750-ufs2-overlay.dts new file mode 100644 index 00000000..d0e3b143 --- /dev/null +++ b/qcom/kera-qrd-qca6750-ufs2-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-qrd-qca6750-ufs2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD + QCA6750 + UFS2"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x3000B 1>; +}; diff --git a/qcom/kera-qrd-qca6750-ufs2.dtsi b/qcom/kera-qrd-qca6750-ufs2.dtsi new file mode 100644 index 00000000..5743706b --- /dev/null +++ b/qcom/kera-qrd-qca6750-ufs2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-qrd.dtsi" +#include "kera_ufs2.dtsi" diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 57b2524b..e795bebb 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -126,6 +126,7 @@ _platform_map = { {"name": "kera-qrd-wcn7750-ufs4-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs2-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs3-overlay.dtbo"}, + {"name": "kera-qrd-qca6750-ufs2-overlay.dtbo"}, {"name": "kera-rcm-qca6750-ufs4-overlay.dtbo"}, {"name": "kera-rcm-qca6750-ufs2-overlay.dtbo"}, {"name": "kera-rcm-qca6750-ufs3-overlay.dtbo"}, From 8e0160fbab8a8777bfae8e5205271863260a9cf0 Mon Sep 17 00:00:00 2001 From: songchai Date: Fri, 6 Dec 2024 14:16:58 +0800 Subject: [PATCH 15/67] ARM: dts: msm: enable apss tpdms for tuna Enable apss tpdms for tuna. Change-Id: Ia6401867e89c4af3a066bd036df26297b64e5bcc Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index 00778ee5..64ad37c5 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -1672,7 +1672,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1694,7 +1693,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1716,7 +1714,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1738,7 +1735,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1760,7 +1756,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1782,7 +1777,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1804,7 +1798,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1826,7 +1819,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { From b1fbece837dc5ee095808f2d21135126bb81b3a1 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 6 Dec 2024 15:29:57 +0530 Subject: [PATCH 16/67] ARM: dts: qcom: Remove no-amc tag for disp_bcm_voter no-amc tag is intended to be used for camera voter and using it with display voter will lead to display underruns as AMC votes will not get committed. Change-Id: I94df2e368d15d6266109cd83e473bb0b5dab4e08 Signed-off-by: Raviteja Laggyshetty --- qcom/parrot.dtsi | 1 - qcom/ravelin.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 8588eed8..c0f541fa 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -558,7 +558,6 @@ disp_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; - qcom,no-amc; }; }; }; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 74364536..da1dece9 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -570,7 +570,6 @@ disp_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; - qcom,no-amc; }; }; }; From 335667315ed0a8b4821efc5fd11b719b5bb4126b Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Mon, 9 Dec 2024 14:01:59 +0800 Subject: [PATCH 17/67] ARM: dts: msm: Correct coresight components for kera Correct coresight components for kera. Change-Id: I9ea4ace1ee65a011769094a9511857ea160c934a Signed-off-by: Yingchao Deng --- qcom/kera-coresight.dtsi | 186 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 173 insertions(+), 13 deletions(-) diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi index 0a23fa78..62f2958f 100644 --- a/qcom/kera-coresight.dtsi +++ b/qcom/kera-coresight.dtsi @@ -1029,7 +1029,7 @@ }; }; - funnel_vide0: funnel@10832000 { + funnel_video: funnel@10832000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb908>; reg = <0x10832000 0x1000>; @@ -1341,6 +1341,14 @@ <&tpdm_wpss_cmb_out_funnel_wpss>; }; }; + + port@2 { + reg = <2>; + funnel_wpss_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_funnel_wpss>; + }; + }; }; out-ports { @@ -1361,6 +1369,15 @@ source = <&tpdm_wpss_cmb>; }; }; + + port@2 { + reg = <2>; + funnel_wpss_out_funnel_dlct: endpoint { + remote-endpoint = + <&funnel_dlct_in_funnel_wpss>; + source = <&wpss_etm>; + }; + }; }; }; @@ -1374,7 +1391,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -1387,19 +1403,9 @@ }; tpdm_turing_llm: tpdm@10981000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb968>; - reg = <0x10981000 0x1000>; - reg-names = "tpdm-base"; - + compatible = "qcom,coresight-static-tpdm"; coresight-name = "coresight-tpdm-turing-llm"; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; - status = "disabled"; - - atid = <78>; - out-ports { port { tpdm_turing_llm_out_funnel_turing: endpoint { @@ -1440,6 +1446,14 @@ <&tpdm_turing_llm_out_funnel_turing>; }; }; + + port@4 { + reg = <4>; + funnel_turing_in_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_out_funnel_turing>; + }; + }; }; out-ports { @@ -1464,6 +1478,15 @@ }; }; + port@2 { + reg = <2>; + funnel_turing_out_funnel_dlct: endpoint { + remote-endpoint = + <&funnel_dlct_in_funnel_turing>; + source = <&turing_etm0>; + }; + }; + }; }; @@ -2262,6 +2285,128 @@ }; }; + turing-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-turing"; + qcom,inst-id = <13>; + + in-ports { + port { + qmi_in_turing_etm0: endpoint { + remote-endpoint = + <&turing_etm0_out_qmi>; + }; + }; + }; + }; + + turing_etm0: turing-etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + + qcom,atid-num = <2>; + atid = <38 39>; + trace-name = "turing-etm0"; + + + out-ports { + port@0 { + reg = <0>; + turing_etm0_out_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_in_turing_etm0>; + }; + }; + + port@1 { + reg = <1>; + turing_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_turing_etm0>; + }; + }; + }; + }; + + wpss_etm: wpss_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-wpss-etm0"; + qcom,inst-id = <3>; + atid = <44>; + + out-ports { + port@0 { + reg = <0>; + wpss_etm0_out_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_in_wpss_etm0>; + }; + }; + + port@1 { + reg = <1>; + wpss_etm0_out_qmi: endpoint { + remote-endpoint = + <&qmi_in_wpss_etm0>; + }; + }; + }; + }; + + wpss-qmi { + compatible = "qcom,coresight-qmi"; + + coresight-name = "coresight-qmi-wpss"; + qcom,inst-id = <3>; + + in-ports { + port { + qmi_in_wpss_etm0: endpoint { + remote-endpoint = + <&wpss_etm0_out_qmi>; + }; + }; + }; + }; + + funnel_turing_dup: funnel@10940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + reg = <0x10940000 0x1000>, + <0x10983000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing_dup"; + + qcom,duplicate-funnel; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@5 { + reg = <5>; + funnel_turing_dup_in_turing_etm0: endpoint { + remote-endpoint = + <&turing_etm0_out_funnel_turing_dup>; + }; + }; + }; + + out-ports { + port { + funnel_turing_dup_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_funnel_turing_dup>; + }; + }; + }; + }; + modem-etm0 { compatible = "qcom,coresight-remote-etm"; @@ -3063,6 +3208,14 @@ }; }; + port@4 { + reg = <4>; + funnel_dlct_in_funnel_wpss: endpoint { + remote-endpoint = + <&funnel_wpss_out_funnel_dlct>; + }; + }; + port@6 { reg = <6>; funnel_dlct_6_in_funnel_gfx_dl: endpoint { @@ -3071,6 +3224,13 @@ }; }; + port@7 { + reg = <7>; + funnel_dlct_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_funnel_dlct>; + }; + }; }; out-ports { From 244a101b212ae138bdfc5838a8c5a9be035994bd Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Thu, 28 Nov 2024 12:25:59 +0530 Subject: [PATCH 18/67] ARM: dts: qcom: Add thermal overlay support for kera and tuna Add thermal overlay support for kera and tuna. Change-Id: I87a87a173715e9d748e8bab7250d34530be03554 Signed-off-by: Priyansh Jain --- qcom/kera.dtsi | 1 + qcom/tuna-cdp.dtsi | 1 - qcom/tuna-mtp.dtsi | 1 - qcom/tuna-pm7550ba.dtsi | 19 +++++++++++++++++++ qcom/tuna-pmih010x.dtsi | 19 +++++++++++++++++++ qcom/tuna-pmiv0108.dtsi | 19 +++++++++++++++++++ qcom/tuna-qrd.dtsi | 1 - qcom/tuna-thermal-overlay.dtsi | 19 ------------------- qcom/tuna.dtsi | 2 ++ 9 files changed, 60 insertions(+), 22 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 3986b5d3..65164f1d 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -3217,3 +3217,4 @@ vdd-usb-cp-supply = <&L7B>; }; }; +#include "tuna-thermal-overlay.dtsi" diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index eb92e52c..c188cee7 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -4,7 +4,6 @@ */ #include -#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 20a874ec..c5878f76 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -5,7 +5,6 @@ #include #include -#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index bb7acad2..f9ba9b63 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -315,6 +315,25 @@ }; }; }; + + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; }; &pm7550ba_eusb2_repeater { diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index f2ac1b7d..d9a16fe6 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -298,6 +298,25 @@ }; }; }; + + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; }; &pmih010x_eusb2_repeater { diff --git a/qcom/tuna-pmiv0108.dtsi b/qcom/tuna-pmiv0108.dtsi index 15c2767c..1cfe6696 100644 --- a/qcom/tuna-pmiv0108.dtsi +++ b/qcom/tuna-pmiv0108.dtsi @@ -240,6 +240,25 @@ }; }; }; + + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; }; &pmiv010x_eusb2_repeater { diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index f5b69fc1..52f76c03 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -4,7 +4,6 @@ */ #include #include -#include "tuna-thermal-overlay.dtsi" &qupv3_se4_spi { #address-cells = <1>; diff --git a/qcom/tuna-thermal-overlay.dtsi b/qcom/tuna-thermal-overlay.dtsi index c0f874df..e0c1e053 100644 --- a/qcom/tuna-thermal-overlay.dtsi +++ b/qcom/tuna-thermal-overlay.dtsi @@ -6,25 +6,6 @@ #include &thermal_zones { - socd { - cooling-maps { - socd_apc1 { - trip = <&socd_trip>; - cooling-device = <&APC1_MX_CX_PAUSE 1 1>; - }; - - socd_cdsp1 { - trip = <&socd_trip>; - cooling-device = <&cdsp_sw 4 4>; - }; - - socd_gpu0 { - trip = <&socd_trip>; - cooling-device = <&msm_gpu 4 4>; - }; - }; - }; - pmxr2230-bcl-lvl0 { cooling-maps { lbat_0_nr_scg { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 5080d089..58bbc1f8 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -3667,3 +3667,5 @@ vdd-usb-cp-supply = <&L7B>; }; }; + +#include "tuna-thermal-overlay.dtsi" From 99725ac98cd077faaaafcb071993141cd013b328 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 2 Dec 2024 14:59:13 +0530 Subject: [PATCH 19/67] ARM: dts: msm: Increase system cma size for kera Increase cma size by 4MB for use by memshare IMS usecase. This is inline with sun. Change-Id: I81f6da44aa02c00c895854d69dbd949b70f541ff Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 905c3a88..eb84ecfa 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -418,7 +418,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; + size = <0x0 0x2400000>; linux,cma-default; }; From 943d5a234b51716b35bbd47adb4de03011fe23a1 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Tue, 10 Dec 2024 16:01:24 +0530 Subject: [PATCH 20/67] ARM: dts: msm: Add ufs shutdown power supply for tuna Add ufs proxy power supply to add an additional vote for VCCQ LDO. In case of ufs shutdown, UFS VCCQ LDO would be turned off by PMIC regulator itself. Change-Id: I210474d8856f8b1160cc707db17898b1c0403093 Signed-off-by: Manish Pandey --- qcom/tuna-cdp.dtsi | 3 +++ qcom/tuna-mtp.dtsi | 3 +++ qcom/tuna-qrd.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index eb92e52c..fbfb524a 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -77,6 +77,9 @@ vccq-supply = <&L3F>; vccq-max-microamp = <1200000>; + qcom,vccq-proxy-vote-supply = <&L3F>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + /* VDD_PX10 is voted for the ufs_reset_n */ qcom,vddp-ref-clk-supply = <&L5B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 20a874ec..163aa0e4 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -78,6 +78,9 @@ vccq-supply = <&L3F>; vccq-max-microamp = <1200000>; + qcom,vccq-proxy-vote-supply = <&L3F>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + /* VDD_PX10 is voted for the ufs_reset_n */ qcom,vddp-ref-clk-supply = <&L5B>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index f5b69fc1..dd96b54a 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -80,6 +80,9 @@ vccq-supply = <&L3F>; vccq-max-microamp = <1200000>; + qcom,vccq-proxy-vote-supply = <&L3F>; + qcom,vccq-proxy-vote-max-microamp = <1200000>; + /* VDD_PX10 is voted for the ufs_reset_n */ qcom,vddp-ref-clk-supply = <&L5B>; qcom,vddp-ref-clk-max-microamp = <100>; From 11e52c272948c6b7503a724ade6e1e01f72e2c3f Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 2 Dec 2024 16:13:09 +0530 Subject: [PATCH 21/67] ARM: dts: msm: Update pmic support for kera 1.Disable some pmic dt nodes/properties which are not required for kera. 2. update regulator voltage support for kera as per latest HW recommendation. 3. Update i2c instance for kera for slave charger debug support. Change-Id: Iebcf53837ff021db418fb2cbd16f1fb1ba494304 Signed-off-by: Kavya Nunna --- qcom/kera-mtp-wcn7750-qmp1000.dtsi | 4 +++ qcom/kera-mtp-wcn7750-ufs3.dtsi | 4 +++ qcom/kera-mtp-wcn7750-ufs4.dtsi | 4 +++ qcom/kera-pm7550ba.dtsi | 28 ++++++++-------- qcom/kera-pmic-overlay.dtsi | 4 +++ qcom/kera-qrd-wcn7750-ufs2.dtsi | 4 +++ qcom/kera-qrd-wcn7750-ufs3.dtsi | 4 +++ qcom/kera-qrd-wcn7750-ufs4.dtsi | 4 +++ qcom/kera-qrd.dtsi | 10 +++--- qcom/kera-rcm-wcn7750-ufs2.dtsi | 4 +++ qcom/kera-rcm-wcn7750-ufs3.dtsi | 4 +++ qcom/kera-rcm-wcn7750-ufs4.dtsi | 4 +++ qcom/kera-regulators.dtsi | 52 +++++++++++++++++------------- qcom/kera.dtsi | 3 ++ 14 files changed, 91 insertions(+), 42 deletions(-) diff --git a/qcom/kera-mtp-wcn7750-qmp1000.dtsi b/qcom/kera-mtp-wcn7750-qmp1000.dtsi index a780aeb3..882915e8 100644 --- a/qcom/kera-mtp-wcn7750-qmp1000.dtsi +++ b/qcom/kera-mtp-wcn7750-qmp1000.dtsi @@ -5,3 +5,7 @@ #include "kera-mtp.dtsi" #include "kera_ufs3.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-mtp-wcn7750-ufs3.dtsi b/qcom/kera-mtp-wcn7750-ufs3.dtsi index a780aeb3..882915e8 100644 --- a/qcom/kera-mtp-wcn7750-ufs3.dtsi +++ b/qcom/kera-mtp-wcn7750-ufs3.dtsi @@ -5,3 +5,7 @@ #include "kera-mtp.dtsi" #include "kera_ufs3.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-mtp-wcn7750-ufs4.dtsi b/qcom/kera-mtp-wcn7750-ufs4.dtsi index f30576eb..1c032cfb 100644 --- a/qcom/kera-mtp-wcn7750-ufs4.dtsi +++ b/qcom/kera-mtp-wcn7750-ufs4.dtsi @@ -5,3 +5,7 @@ #include "kera-mtp.dtsi" #include "kera_ufs4.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-pm7550ba.dtsi b/qcom/kera-pm7550ba.dtsi index acd6f6ef..af5310a6 100644 --- a/qcom/kera-pm7550ba.dtsi +++ b/qcom/kera-pm7550ba.dtsi @@ -9,8 +9,8 @@ /delete-node/ i2c@104; /delete-node/ spmi@200; - i2c@104 { - reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + i2c@105 { + reg = <0x105>; /* I2C instance 5 in ADSP for SE4 */ #address-cells = <1>; #size-cells = <0>; qcom,bus-type = "i2c"; @@ -35,33 +35,33 @@ /delete-node/ smb1398_1_die_temp; smb1500_1_iin { - reg = <0x1046901>; - label = "smb1393_1_iin"; + reg = <0x1056901>; + label = "smb1500_1_iin"; }; smb1500_1_ichg { - reg = <0x1046902>; - label = "smb1393_1_ichg"; + reg = <0x1056902>; + label = "smb1500_1_ichg"; }; smb1500_1_die_temp { - reg = <0x1046903>; - label = "smb1393_1_die_temp"; + reg = <0x1056903>; + label = "smb1500_1_die_temp"; }; smb1500_2_iin { - reg = <0x1046801>; - label = "smb1393_2_iin"; + reg = <0x1056801>; + label = "smb1500_2_iin"; }; smb1500_2_ichg { - reg = <0x1046802>; - label = "smb1393_2_ichg"; + reg = <0x1056802>; + label = "smb1500_2_ichg"; }; smb1500_2_die_temp { - reg = <0x1046803>; - label = "smb1393_2_die_temp"; + reg = <0x1056803>; + label = "smb1500_2_die_temp"; }; }; diff --git a/qcom/kera-pmic-overlay.dtsi b/qcom/kera-pmic-overlay.dtsi index a523d4f0..7563e31f 100644 --- a/qcom/kera-pmic-overlay.dtsi +++ b/qcom/kera-pmic-overlay.dtsi @@ -23,3 +23,7 @@ bits = <0 0>; }; }; + +&thermal_zones { + /delete-node/ sys-therm-11; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs2.dtsi b/qcom/kera-qrd-wcn7750-ufs2.dtsi index 5743706b..02db5fed 100644 --- a/qcom/kera-qrd-wcn7750-ufs2.dtsi +++ b/qcom/kera-qrd-wcn7750-ufs2.dtsi @@ -5,3 +5,7 @@ #include "kera-qrd.dtsi" #include "kera_ufs2.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs3.dtsi b/qcom/kera-qrd-wcn7750-ufs3.dtsi index 0a4228ff..ce97b3de 100644 --- a/qcom/kera-qrd-wcn7750-ufs3.dtsi +++ b/qcom/kera-qrd-wcn7750-ufs3.dtsi @@ -5,3 +5,7 @@ #include "kera-qrd.dtsi" #include "kera_ufs3.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs4.dtsi b/qcom/kera-qrd-wcn7750-ufs4.dtsi index d28259d2..17883470 100644 --- a/qcom/kera-qrd-wcn7750-ufs4.dtsi +++ b/qcom/kera-qrd-wcn7750-ufs4.dtsi @@ -5,3 +5,7 @@ #include "kera-qrd.dtsi" #include "kera_ufs4.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi index 30bb3c7c..c9e7fd9f 100644 --- a/qcom/kera-qrd.dtsi +++ b/qcom/kera-qrd.dtsi @@ -74,8 +74,8 @@ }; &pmic_glink_debug { - i2c@104 { - reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + i2c@105 { + reg = <0x105>; /* I2C instance 5 in ADSP for SE4 */ #address-cells = <1>; #size-cells = <0>; qcom,bus-type = "i2c"; @@ -92,17 +92,17 @@ status = "ok"; smb1393_1_iin { - reg = <0x1043401>; + reg = <0x1053401>; label = "smb1393_1_iin"; }; smb1393_1_ichg { - reg = <0x1043402>; + reg = <0x1053402>; label = "smb1393_1_ichg"; }; smb1393_1_die_temp { - reg = <0x1043403>; + reg = <0x1053403>; label = "smb1393_1_die_temp"; }; }; diff --git a/qcom/kera-rcm-wcn7750-ufs2.dtsi b/qcom/kera-rcm-wcn7750-ufs2.dtsi index dc823592..963f60d5 100644 --- a/qcom/kera-rcm-wcn7750-ufs2.dtsi +++ b/qcom/kera-rcm-wcn7750-ufs2.dtsi @@ -5,3 +5,7 @@ #include "kera-rcm.dtsi" #include "kera_ufs2.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-rcm-wcn7750-ufs3.dtsi b/qcom/kera-rcm-wcn7750-ufs3.dtsi index 99203b93..a618b78a 100644 --- a/qcom/kera-rcm-wcn7750-ufs3.dtsi +++ b/qcom/kera-rcm-wcn7750-ufs3.dtsi @@ -5,3 +5,7 @@ #include "kera-rcm.dtsi" #include "kera_ufs3.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-rcm-wcn7750-ufs4.dtsi b/qcom/kera-rcm-wcn7750-ufs4.dtsi index 4834e869..7a442a73 100644 --- a/qcom/kera-rcm-wcn7750-ufs4.dtsi +++ b/qcom/kera-rcm-wcn7750-ufs4.dtsi @@ -5,3 +5,7 @@ #include "kera-rcm.dtsi" #include "kera_ufs4.dtsi" + +&L11B { + /delete-property/ regulator-always-on; +}; diff --git a/qcom/kera-regulators.dtsi b/qcom/kera-regulators.dtsi index 1b90a63c..2b82ef1f 100644 --- a/qcom/kera-regulators.dtsi +++ b/qcom/kera-regulators.dtsi @@ -17,8 +17,8 @@ S1B: pmxr2230_s1: vreg-pmxr2230-s1 { regulator-name = "pmxr2230_s1"; qcom,set = ; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <2044000>; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; qcom,init-voltage = <1856000>; qcom,init-mode = ; }; @@ -36,7 +36,7 @@ regulator-name = "pmxr2230_s2"; qcom,set = ; regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <2092000>; + regulator-max-microvolt = <1408000>; qcom,init-voltage = <1256000>; qcom,init-mode = ; }; @@ -49,8 +49,8 @@ S3B: pmxr2230_s3: vreg-pmxr2230-s3 { regulator-name = "pmxr2230_s3"; qcom,set = ; - regulator-min-microvolt = <920000>; - regulator-max-microvolt = <2736000>; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1040000>; qcom,init-voltage = <952000>; }; }; @@ -63,7 +63,7 @@ regulator-name = "pmxr2230_s4"; qcom,set = ; regulator-min-microvolt = <2156000>; - regulator-max-microvolt = <2700000>; + regulator-max-microvolt = <2600000>; qcom,init-voltage = <2156000>; }; }; @@ -116,9 +116,9 @@ L2B: pmxr2230_l2: vreg-pmxr2230-l2 { regulator-name = "pmxr2230_l2"; qcom,set = ; - regulator-min-microvolt = <880000>; + regulator-min-microvolt = <720000>; regulator-max-microvolt = <950000>; - qcom,init-voltage = <880000>; + qcom,init-voltage = <720000>; qcom,init-mode = ; }; }; @@ -152,8 +152,8 @@ L4B: pmxr2230_l4: vreg-pmxr2230-l4 { regulator-name = "pmxr2230_l4"; qcom,set = ; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; }; @@ -167,14 +167,16 @@ ; qcom,mode-threshold-currents = <0 30000>; + status = "disabled"; L5B: pmxr2230_l5: vreg-pmxr2230-l5 { regulator-name = "pmxr2230_l5"; qcom,set = ; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1370000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; + status = "disabled"; }; }; @@ -210,7 +212,7 @@ regulator-name = "pmxr2230_l7"; qcom,set = ; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; }; @@ -228,8 +230,8 @@ L8B: pmxr2230_l8: vreg-pmxr2230-l8 { regulator-name = "pmxr2230_l8"; qcom,set = ; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; }; @@ -286,7 +288,7 @@ regulator-name = "pmxr2230_l11"; qcom,set = ; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; regulator-always-on; @@ -669,7 +671,7 @@ regulator-name = "pm_v6d_l2"; qcom,set = ; regulator-min-microvolt = <556000>; - regulator-max-microvolt = <816000>; + regulator-max-microvolt = <868000>; qcom,init-voltage = <556000>; qcom,init-mode = ; }; @@ -766,8 +768,8 @@ L2G: pm_v6g_l2: vreg-pm_v6g-l2 { regulator-name = "pm_v6g_l2"; qcom,set = ; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <2000000>; qcom,init-voltage = <1080000>; qcom,init-mode = ; }; @@ -786,7 +788,7 @@ regulator-name = "pm_v6g_l3"; qcom,set = ; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; }; @@ -795,6 +797,7 @@ rpmh-regulator-smpi1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpi1"; + status = "disabled"; S1I: pmg1110i_s1: vreg-pmg1110i-s1 { regulator-name = "pmg1110i_s1"; @@ -802,12 +805,14 @@ regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; qcom,init-voltage = <904000>; + status = "disabled"; }; }; rpmh-regulator-smpj1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpj1"; + status = "disabled"; S1J: pmg1110j_s1: vreg-pmg1110j-s1 { regulator-name = "pmg1110j_s1"; @@ -815,6 +820,7 @@ regulator-min-microvolt = <556000>; regulator-max-microvolt = <816000>; qcom,init-voltage = <556000>; + status = "disabled"; }; }; @@ -831,7 +837,7 @@ regulator-name = "pmr735b_l1"; qcom,set = ; regulator-min-microvolt = <806000>; - regulator-max-microvolt = <901000>; + regulator-max-microvolt = <912000>; qcom,init-voltage = <806000>; qcom,init-mode = ; }; @@ -887,9 +893,9 @@ L4K: pmr735b_l4: vreg-pmr735b-l4 { regulator-name = "pmr735b_l4"; qcom,set = ; - regulator-min-microvolt = <120000>; + regulator-min-microvolt = <960000>; regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; + qcom,init-voltage = <960000>; qcom,init-mode = ; }; }; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 6e78dc8a..71183436 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -2263,6 +2263,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,can-sleep; + status = "disabled"; }; pm8550vs@6 { @@ -2279,6 +2280,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,can-sleep; + status = "disabled"; }; pmg1110@9 { @@ -2287,6 +2289,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,can-sleep; + status = "disabled"; }; pmr735d@a { From 7dcc0e4ed84096f5cccae19941ceb8b2bb130f7b Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 9 Dec 2024 17:39:11 +0530 Subject: [PATCH 22/67] ARM: dts: msm: Add Gaming variant soc-id for Ravelin VM Add Gaming variant soc-id for Ravelin VM. Change-Id: I318765551cc6c3cf9c54836ac8c7db2c8fb0a6b2 Signed-off-by: Saranya R --- qcom/ravelin-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/ravelin-vm.dtsi b/qcom/ravelin-vm.dtsi index 0f56a622..376e219e 100644 --- a/qcom/ravelin-vm.dtsi +++ b/qcom/ravelin-vm.dtsi @@ -7,7 +7,7 @@ #include / { - qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, <653 0x10000>, <654 0x10000>; interrupt-parent = <&vgic>; qcom,vm-config { From ba56528079ba589de3d0c3b8748b5c450e255b7b Mon Sep 17 00:00:00 2001 From: Fenil Panwala Date: Mon, 2 Dec 2024 11:12:15 +0530 Subject: [PATCH 23/67] ARM: dts: msm: Add memshare for Kera Memshare driver allocates and share the memory with the modem clients for their use. The device tree information for memshare driver on tuna is added to specify client details. Change-Id: I577cccac63d4aeb54dcf7a9470cd8672c6c016d4 Signed-off-by: Fenil Panwala --- qcom/kera.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index e5da4889..ca433d9e 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1486,6 +1486,51 @@ }; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + + qcom,client_ims_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x100000>; + qcom,client-id = <7>; + qcom,allocate-on-request; + qcom,shared; + label = "modem"; + }; + + qcom,client_ims_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x100000>; + qcom,client-id = <8>; + qcom,allocate-on-request; + qcom,shared; + label = "modem"; + }; + }; + eud: qcom,msm-eud@88e0000 { compatible = "qcom,msm-eud"; interrupt-names = "eud_irq"; From 75c5f1067d2e73bc39ead8cde30dc66bac5747c3 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 11 Dec 2024 12:07:09 +0530 Subject: [PATCH 24/67] ARM: dts: msm: Add IOMMU geometry configuration for tuna SoC Add qcom,iommu-geometry property to the tuna sdhc2 node. Change-Id: I80286749df5764995fbc374603920defb9fd8d24 Signed-off-by: Manish Pandey --- qcom/tuna.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index d8eb4671..34e0408c 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2353,6 +2353,7 @@ 0x090106C0 0x80040868>; iommus = <&apps_smmu 0x140 0x0>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; memory-region = <&sdhc_2_dma_resv>; From 45c0718e764cb958cc1a27d2a676863ca115af35 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Tue, 19 Nov 2024 13:00:31 +0530 Subject: [PATCH 25/67] ARM: dts: msm: Add support for partial CPU configuration Add PMQOS, CPUFREQ, IRQ affinity mapping support for partial CPU configuration. Change-Id: I55dd98bdd1d2bd3ebc99a2091c366c00b51a9507 Signed-off-by: Nitin Rawat --- qcom/sun.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index c8885373..355323b1 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2429,6 +2429,7 @@ qcom,ice-use-hwkm; qcom,prime-mask = <0xc0>; qcom,silver-mask = <0x3f>; + qcom,cluster-mask = <0x3F 0xC0>; /* affine cpu for each CQ starting from CQ:0 to CQ:max_cqs */ qcom,esi-affinity-mask = <4 5 3 4 5 3 7 7>; @@ -2481,25 +2482,19 @@ qcom,bypass-pbl-rst-wa; qcom,max-cpus = <8>; + qcom,storage-boost; msi-parent = <&gic_its 0x60>; status = "disabled"; qos0 { - mask = <0xc0>; vote = <44>; perf; - /* Set CPU6 to fmax, and CPU[6-7] will run at fmax */ - cpu_freq_vote = <6>; }; qos1 { - mask = <0x3f>; vote = <44>; - perf; - /* Set CPU0 to fmax, and CPU[0-5] will run at fmax */ - cpu_freq_vote = <0>; }; }; From 846159d0bd444077761d8134017baf14590dc409 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Wed, 11 Dec 2024 14:49:55 +0530 Subject: [PATCH 26/67] ARM: dts: msm: Add support for new WCN Card for Parrot VM Add board-id support for new WCN Card for Parrot VM. Change-Id: Ied8021ddc151a6d7c17a31464cfe17dabe920b8b Signed-off-by: Saranya R --- qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts | 2 +- qcom/parrot-vm-idp.dts | 2 +- qcom/parrot-vm-qrd-wcn6750.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts index 8cd3d4fb..8afb5c3e 100644 --- a/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts +++ b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts @@ -11,5 +11,5 @@ / { model = "Qualcomm Technologies, Inc. Parrot WCN6750 VM IDP + AMOLED + RCM"; compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; - qcom,board-id = <34 2>; + qcom,board-id = <34 2>, <34 6>; }; diff --git a/qcom/parrot-vm-idp.dts b/qcom/parrot-vm-idp.dts index d50413d5..cc44b70a 100644 --- a/qcom/parrot-vm-idp.dts +++ b/qcom/parrot-vm-idp.dts @@ -11,5 +11,5 @@ / { model = "Qualcomm Technologies, Inc. Parrot SVM IDP"; compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; - qcom,board-id = <34 0>; + qcom,board-id = <34 0>, <34 5>; }; diff --git a/qcom/parrot-vm-qrd-wcn6750.dts b/qcom/parrot-vm-qrd-wcn6750.dts index e773ce4b..7a595897 100644 --- a/qcom/parrot-vm-qrd-wcn6750.dts +++ b/qcom/parrot-vm-qrd-wcn6750.dts @@ -11,5 +11,5 @@ / { model = "Qualcomm Technologies, Inc. Parrot SVM QRD + WCN6750"; compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; - qcom,board-id = <0x1000B 1>; + qcom,board-id = <0x1000B 1>, <0x1000B 2>; }; From b6e99316a141cdc5a3263e1e53ecdbc6d45eb6fe Mon Sep 17 00:00:00 2001 From: Ravulapati Vishnu Vardhan Rao Date: Thu, 21 Nov 2024 18:34:07 +0530 Subject: [PATCH 27/67] ARM: dts: qcom: Add wcd usb_mode -Add wcd usb_mode for tuna7 to register WCD_USBSS for SDAM interrupts. Change-Id: I844746ba9820a558e70ed31bbb3ee93505376376 Signed-off-by: Ravulapati Vishnu Vardhan Rao --- qcom/tuna7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/tuna7.dtsi b/qcom/tuna7.dtsi index 84e58645..c1d47677 100644 --- a/qcom/tuna7.dtsi +++ b/qcom/tuna7.dtsi @@ -18,3 +18,13 @@ &llcc { compatible = "qcom,tuna7-llcc"; }; + +&wcd_usbss { + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_wcd"; + nvmem-cells = <&usb_mode>; + nvmem-cell-names = "usb_mode"; + status = "ok"; +}; + From 9c878c402146939d943e88d547f8c4318a66ad67 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Thu, 12 Dec 2024 10:01:17 +0530 Subject: [PATCH 28/67] ARM: dts: qcom: Update qup_iommu_region node name Currently single qup_iommu_region is getting created, leading to DMA RX inactivate. So update node name for qup_iommu_region0 and qup_iommu_region1. Change-Id: Id1355c98a07f912e6275ac3c2fb7504ae9f22f53 Signed-off-by: Swetha Chikkaboraiah --- qcom/parrot-qupv3.dtsi | 4 ++-- qcom/ravelin-qupv3.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/parrot-qupv3.dtsi b/qcom/parrot-qupv3.dtsi index 1163c5e5..615c34a8 100644 --- a/qcom/parrot-qupv3.dtsi +++ b/qcom/parrot-qupv3.dtsi @@ -19,7 +19,7 @@ * Qup1 5: SE 11 */ - qup_iommu_region0: qup_iommu_region { + qup_iommu_region0: qup_iommu_region0 { iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>, <&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>; }; @@ -325,7 +325,7 @@ }; }; - qup_iommu_region1: qup_iommu_region { + qup_iommu_region1: qup_iommu_region1 { iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>, <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; }; diff --git a/qcom/ravelin-qupv3.dtsi b/qcom/ravelin-qupv3.dtsi index 1fa9123b..f4a57d86 100644 --- a/qcom/ravelin-qupv3.dtsi +++ b/qcom/ravelin-qupv3.dtsi @@ -17,7 +17,7 @@ * Qup1 4: SE 9 */ - qup_iommu_region0: qup_iommu_region { + qup_iommu_region0: qup_iommu_region0 { iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>, <&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>; }; @@ -279,7 +279,7 @@ }; }; - qup_iommu_region1: qup_iommu_region { + qup_iommu_region1: qup_iommu_region1 { iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>, <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; }; From eff8df7c3b367b43b26114347642cf46241f5e3b Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Sat, 23 Nov 2024 22:49:32 +0530 Subject: [PATCH 29/67] ARM: dts: msm: enable QoS programming for TUNA Enable QoS programming for tuna and add necessary AXI and AHB clock handles for programming QoS for IPA and PCIE masters. Change-Id: Ie3d77ad7248a9dbfdbd75ccb7eaa009e58db260a Signed-off-by: Raviteja Laggyshetty --- qcom/tuna.dtsi | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index f1ecb6ae..7fc8dc6d 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2131,7 +2131,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; cnoc_main: interconnect@1500000 { @@ -2140,7 +2139,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; system_noc: interconnect@1680000 { @@ -2149,7 +2147,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; pcie_noc: interconnect@16c0000 { @@ -2160,7 +2157,8 @@ "pcie_crm_hw_0"; qcom,bcm-voters = <&apps_bcm_voter>, <&pcie_crm_hw_0_bcm_voter>; - qcom,skip-qos; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; }; aggre1_noc: interconnect@16e0000 { @@ -2169,7 +2167,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; aggre2_noc: interconnect@1700000 { @@ -2178,7 +2175,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1780000 { @@ -2207,7 +2204,6 @@ <&disp_crm_hw_4_bcm_voter>, <&disp_crm_hw_5_bcm_voter>, <&disp_crm_sw_0_bcm_voter>; - qcom,skip-qos; }; gem_noc: interconnect@24100000 { @@ -2238,7 +2234,6 @@ <&disp_crm_hw_4_bcm_voter>, <&disp_crm_hw_5_bcm_voter>, <&disp_crm_sw_0_bcm_voter>; - qcom,skip-qos; }; nsp_noc: interconnect@320c0000 { @@ -2247,7 +2242,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_ag_noc: interconnect@7e40000 { @@ -2256,7 +2250,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_lpiaon_noc: interconnect@7400000 { @@ -2265,7 +2258,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_lpicx_noc: interconnect@7420000 { @@ -2274,7 +2266,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; qcom,rmtfs_sharedmem@0 { From d15d548cbac5b4873f0dfab7fc674ea0667bb84f Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Fri, 29 Nov 2024 16:18:16 +0530 Subject: [PATCH 30/67] ARM: dts: msm: Increase system CMA size for tuna Increase cma size by 4MB for use by memshare IMS usecase. This is inline with sun. Change-Id: Ia8fb0ad84c52fed8d2b5dc80ef4bc38aacbe0266 Signed-off-by: Bibek Kumar Patro --- qcom/tuna.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 981db753..1db066bc 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -453,7 +453,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; + size = <0x0 0x2400000>; linux,cma-default; }; From d89207245ea73f0f4d3dc39a264707166384cebb Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 9 Dec 2024 15:29:32 +0530 Subject: [PATCH 31/67] ARM: dts: msm: Update i2c-pmic support for tuna Correct the I2C instances used for parallel charger debug interface. Change-Id: I3bbdb4fa2777802c04c8e65e2b35dd2e59e716b9 Signed-off-by: Kavya Nunna --- qcom/tuna-pm7550ba-pmd802x.dtsi | 59 ++++++++++++++++----------------- qcom/tuna-pm7550ba.dtsi | 16 ++++----- qcom/tuna-pmih010x.dtsi | 10 +++--- 3 files changed, 42 insertions(+), 43 deletions(-) diff --git a/qcom/tuna-pm7550ba-pmd802x.dtsi b/qcom/tuna-pm7550ba-pmd802x.dtsi index e93d1138..72f84c98 100644 --- a/qcom/tuna-pm7550ba-pmd802x.dtsi +++ b/qcom/tuna-pm7550ba-pmd802x.dtsi @@ -29,27 +29,26 @@ }; }; -&pmic_glink_debug { - /delete-node/ i2c@104; - /delete-node/ spmi@200; - i2c@104 { - reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ - #address-cells = <1>; - #size-cells = <0>; - qcom,bus-type = "i2c"; +&i2c_pmic_smb1398 { + status = "disabled"; +}; - qcom,smb1500@69 { - compatible = "qcom,i2c-pmic"; - reg = <0x69>; - qcom,can-sleep; - }; +&spmi_pmic_smb1510 { + status = "disabled"; +}; - qcom,smb1500@68 { - compatible = "qcom,i2c-pmic"; - reg = <0x68>; - qcom,can-sleep; - }; +&i2c_pmic { + qcom,smb1500@69 { + compatible = "qcom,i2c-pmic"; + reg = <0x69>; + qcom,can-sleep; + }; + + qcom,smb1500@68 { + compatible = "qcom,i2c-pmic"; + reg = <0x68>; + qcom,can-sleep; }; }; @@ -60,32 +59,32 @@ /delete-node/ smb1398_1_die_temp; smb1500_1_iin { - reg = <0x1046901>; - label = "smb1393_1_iin"; + reg = <0x1066901>; + label = "smb1500_1_iin"; }; smb1500_1_ichg { - reg = <0x1046902>; - label = "smb1393_1_ichg"; + reg = <0x1066902>; + label = "smb1500_1_ichg"; }; smb1500_1_die_temp { - reg = <0x1046903>; - label = "smb1393_1_die_temp"; + reg = <0x1066903>; + label = "smb1500_1_die_temp"; }; smb1500_2_iin { - reg = <0x1046801>; - label = "smb1393_2_iin"; + reg = <0x1066801>; + label = "smb1500_2_iin"; }; smb1500_2_ichg { - reg = <0x1046802>; - label = "smb1393_2_ichg"; + reg = <0x1066802>; + label = "smb1500_2_ichg"; }; smb1500_2_die_temp { - reg = <0x1046803>; - label = "smb1393_2_die_temp"; + reg = <0x1066803>; + label = "smb1500_2_die_temp"; }; }; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index bb7acad2..07ed3fe7 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -37,13 +37,13 @@ }; }; - i2c@104 { - reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + i2c_pmic:i2c@106 { + reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */ #address-cells = <1>; #size-cells = <0>; qcom,bus-type = "i2c"; - qcom,smb1398@34 { + i2c_pmic_smb1398: qcom,smb1398@34 { compatible = "qcom,i2c-pmic"; reg = <0x34>; qcom,can-sleep; @@ -51,13 +51,13 @@ }; /* SPMI bridge bus 1 with SMB1510 device */ - spmi@200 { + spmi_pmic:spmi@200 { reg = <0x200>; #address-cells = <2>; #size-cells = <0>; qcom,bus-type = "spmi"; - qcom,smb1510@d { + spmi_pmic_smb1510: qcom,smb1510@d { compatible = "qcom,spmi-pmic"; reg = <13 SPMI_USID>; qcom,can-sleep; @@ -69,17 +69,17 @@ status = "ok"; smb1398_1_iin { - reg = <0x1043401>; + reg = <0x1063401>; label = "smb1393_1_iin"; }; smb1398_1_ichg { - reg = <0x1043402>; + reg = <0x1063402>; label = "smb1393_1_ichg"; }; smb1398_1_die_temp { - reg = <0x1043403>; + reg = <0x1063403>; label = "smb1393_1_die_temp"; }; }; diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index f2ac1b7d..53203c9b 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -20,8 +20,8 @@ }; }; - i2c@104 { - reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + i2c_pmic:i2c@106 { + reg = <0x106>; /* I2C instance 6 in ADSP for SE5 */ #address-cells = <1>; #size-cells = <0>; qcom,bus-type = "i2c"; @@ -48,17 +48,17 @@ status = "ok"; smb1500_1_iin { - reg = <0x1046901>; + reg = <0x1066901>; label = "smb1393_1_iin"; }; smb1500_1_ichg { - reg = <0x1046902>; + reg = <0x1066902>; label = "smb1393_1_ichg"; }; smb1500_1_die_temp { - reg = <0x1046903>; + reg = <0x1066903>; label = "smb1393_1_die_temp"; }; }; From a91be36af9add97d5c114d6a17ff9a1db9a986b9 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 4 Dec 2024 15:52:49 +0530 Subject: [PATCH 32/67] ARM: dts: msm: Update the gcc and display clock controllers to tuna-v1 Update the gcc and display clock controllers to tuna-v1. Change-Id: Ib5ac5396315cdb876ad9d330f500b7c173c95259 Signed-off-by: Anaadi Mishra --- qcom/tuna.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 34e0408c..c4d130ac 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1794,7 +1794,7 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,tuna-dispcc", "syscon"; + compatible = "qcom,tuna-dispcc-v1", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; @@ -1832,7 +1832,7 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,tuna-gcc", "syscon"; + compatible = "qcom,tuna-gcc-v1", "syscon"; reg = <0x100000 0x1f4200>; reg-name = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; From 5f2a102d83407dd3dad662efff579e27d688e8af Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 11 Dec 2024 12:09:00 +0530 Subject: [PATCH 33/67] ARM: dts: msm: Add IOMMU geometry configuration to kera sdhc2 Add qcom,iommu-geometry property to the kera sdhc2 node. Change-Id: I5c58288ce8b2bf21acd23bc0a0e606d09cd1a068 Signed-off-by: Manish Pandey --- qcom/kera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 805a0525..21de54ec 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -2477,6 +2477,7 @@ 0x090106C0 0x80040868>; iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; dma-coherent; memory-region = <&sdhc_2_dma_resv>; From 04b5bc4ec374f47f6173b9b793d806ccff60844a Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Mon, 16 Dec 2024 15:13:20 +0800 Subject: [PATCH 34/67] ARM: dts: msm: add atclk for stm on sun Add atclk for coresight-stm on sun. Change-Id: Icfa764bdd57319a5e188de03b64a86395051b993 Signed-off-by: Yuanfang Zhang --- qcom/sun-coresight.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi index 46a3d97a..cdfcda39 100644 --- a/qcom/sun-coresight.dtsi +++ b/qcom/sun-coresight.dtsi @@ -4199,8 +4199,10 @@ coresight-name = "coresight-stm"; atid = <16>; - clocks = <&aoss_qmp>; - clock-names = "apb_pclk"; + clocks = <&aoss_qmp>, + <&scmi_clk 0>; + clock-names = "apb_pclk", + "atclk"; out-ports { port { From 30c853eb89acc2917a4011c35dc7d213ce6d9df1 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Thu, 12 Dec 2024 12:20:13 +0530 Subject: [PATCH 35/67] ARM: dts: msm: Fix for memory bootargs on kera Fix (4082b0db ARM: dts: msm: Update stdout-path with serial0 alias) to re-enable (09b0fdef ARM: dts: msm: update kernel bootargs for kera). While at it align the same bootargs on rumi files. Change-Id: I032af3b9ea9a78418ef7360fc5d8b94885c6a8e6 Signed-off-by: Wasim Nazir --- qcom/kera-rumi.dtsi | 2 +- qcom/kera.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 2b8a1e8c..7ee0e462 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -7,7 +7,7 @@ #include &chosen { - bootargs = "printk.devkmsg=on loglevel=8 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 irqaffinity=0-2 firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware ftrace_dump_on_oops slub_debug=- cpufreq.default_governor=performance"; + bootargs = "printk.devkmsg=on loglevel=8 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7 irqaffinity=0-2 firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket cpufreq.default_governor=performance"; }; &arch_timer { diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 4376bc8d..0c4d6636 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -69,7 +69,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops page_poison=on cgroup.memory=nokmem,nosocket"; stdout-path = "serial0:115200n8"; }; From 1d89ea2f090b41ac034727052c2431d057d3c8d3 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 16 Dec 2024 14:20:25 +0530 Subject: [PATCH 36/67] ARM: dts: msm: Update slave address for smb1500 for tuna qrd Update the slave address for slave charger debug support. While at it, replace the pmr735b with pmr735d for the correct pmic configuration for tuna/kera platforms. Change-Id: Ia03e24763a3fa8611719e8243b473f6c8507a29a Signed-off-by: Kavya Nunna --- qcom/tuna-pmic-overlay.dtsi | 2 +- qcom/tuna-pmih010x.dtsi | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi index f81e83c8..a934e553 100644 --- a/qcom/tuna-pmic-overlay.dtsi +++ b/qcom/tuna-pmic-overlay.dtsi @@ -9,7 +9,7 @@ #include "pmk8550.dtsi" #include "pmxr2230.dtsi" #include "pm8550vs.dtsi" -#include "pmr735b.dtsi" +#include "pmr735d.dtsi" #include "pm8550ve.dtsi" #include "pm8010.dtsi" diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index 53203c9b..ea2d7842 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -26,9 +26,9 @@ #size-cells = <0>; qcom,bus-type = "i2c"; - qcom,smb1500@69 { + qcom,smb1500@68 { compatible = "qcom,i2c-pmic"; - reg = <0x69>; + reg = <0x68>; qcom,can-sleep; }; }; @@ -48,18 +48,18 @@ status = "ok"; smb1500_1_iin { - reg = <0x1066901>; - label = "smb1393_1_iin"; + reg = <0x1066801>; + label = "smb1500_1_iin"; }; smb1500_1_ichg { - reg = <0x1066902>; - label = "smb1393_1_ichg"; + reg = <0x1066802>; + label = "smb1500_1_ichg"; }; smb1500_1_die_temp { - reg = <0x1066903>; - label = "smb1393_1_die_temp"; + reg = <0x1066803>; + label = "smb1500_1_die_temp"; }; }; From eea1d75da56d70d98e71b87eaf77d479752e1aea Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 11 Dec 2024 17:20:49 +0530 Subject: [PATCH 37/67] bindings: soc: qcom: Document pcie-pdc compatible for kera Document pcie pdc device support for kera. Change-Id: Ief7d219f0cce276a27c5cb09253b131ec959e4c2 Signed-off-by: Sneh Mankad --- bindings/soc/qcom/qcom,pcie-pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/soc/qcom/qcom,pcie-pdc.yaml b/bindings/soc/qcom/qcom,pcie-pdc.yaml index 37a32c9f..62a9f3fe 100644 --- a/bindings/soc/qcom/qcom,pcie-pdc.yaml +++ b/bindings/soc/qcom/qcom,pcie-pdc.yaml @@ -22,6 +22,7 @@ properties: - qcom,pineapple-pcie-pdc - qcom,cliffs-pcie-pdc - qcom,tuna-pcie-pdc + - qcom,kera-pcie-pdc - qcom,pcie-pdc reg: From bbf809aca93e2be5bbc4ae09efd93d4bf0a76ef1 Mon Sep 17 00:00:00 2001 From: songchai Date: Mon, 16 Dec 2024 22:12:24 -0800 Subject: [PATCH 38/67] ARM: dts: msm: add reserved mem for secure_etr Add reserved mem for secure_etr on Kera. Change-Id: Iba7321717cac50b17d85ef03cf3ae16ec407adcc Signed-off-by: songchai --- qcom/kera-coresight.dtsi | 1 + qcom/kera-reserved-memory.dtsi | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi index 62f2958f..c3bf6524 100644 --- a/qcom/kera-coresight.dtsi +++ b/qcom/kera-coresight.dtsi @@ -2443,6 +2443,7 @@ real-name = "coresight-tmc-etr1"; qdss,buffer-size = <0x2000000>; qcom,secure-component; + memory-region = <&qdss_apps_mem>; coresight-csr = <&csr>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi index 665a87f6..96bd02e3 100644 --- a/qcom/kera-reserved-memory.dtsi +++ b/qcom/kera-reserved-memory.dtsi @@ -117,6 +117,12 @@ reg = <0x0 0x82700000 0x0 0x100000>; }; + qdss_apps_mem: qdss_apps_region@82800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + dsm_partition_1_mem: dsm_partition_1_region@84a00000 { no-map; reg = <0x0 0x84a00000 0x0 0x3700000>; From 422ccfa1e6acb439a80c828e160ffdb88301ab9c Mon Sep 17 00:00:00 2001 From: songchai Date: Mon, 16 Dec 2024 22:00:51 -0800 Subject: [PATCH 39/67] ARM: dts: msm: correct tpdms'name for kera correct tpdms'name for kera. Change-Id: Id5ce09d1ba9389594826c511d3fdf200f83724c1 Signed-off-by: songchai --- qcom/kera-coresight.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi index 62f2958f..d3ba5190 100644 --- a/qcom/kera-coresight.dtsi +++ b/qcom/kera-coresight.dtsi @@ -1842,10 +1842,10 @@ }; }; - tpdm_lpass_crdl: tpdm@10bb4000 { + tpdm_lpass_crdl: tpdm@10b84000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; - reg = <0x10bb4000 0x1000>; + reg = <0x10b84000 0x1000>; reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-lpass-crdl"; @@ -3024,7 +3024,7 @@ reg = <0x10820000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-dlct-dsb"; + coresight-name = "coresight-tpdm-dlct-dsb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3046,7 +3046,7 @@ reg = <0x10821000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-dlct-cmb"; + coresight-name = "coresight-tpdm-dlct-cmb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3263,7 +3263,7 @@ reg = <0x109a4000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-mm-dsb"; + coresight-name = "coresight-tpdm-mm-dsb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3286,7 +3286,7 @@ reg = <0x109ae000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-west-dsb"; + coresight-name = "coresight-tpdm-west-dsb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3309,7 +3309,7 @@ reg = <0x109a5000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-south-dsb"; + coresight-name = "coresight-tpdm-south-dsb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3330,7 +3330,7 @@ reg = <0x109ab000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-ipcc-cmb"; + coresight-name = "coresight-tpdm-ipcc-cmb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3352,7 +3352,7 @@ reg = <0x109aa000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-center-dsb"; + coresight-name = "coresight-tpdm-center-dsb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3374,7 +3374,7 @@ reg = <0x109a7000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-rdpm-cx"; + coresight-name = "coresight-tpdm-rdpm-cx"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3396,7 +3396,7 @@ reg = <0x109a9000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-rdpm-mxc"; + coresight-name = "coresight-tpdm-rdpm-mxc"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3418,7 +3418,7 @@ reg = <0x109a8000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-rdpm-mxa"; + coresight-name = "coresight-tpdm-rdpm-mxa"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3440,7 +3440,7 @@ reg = <0x109ac000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-center-cmb"; + coresight-name = "coresight-tpdm-center-cmb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3462,7 +3462,7 @@ reg = <0x109af000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-south-cmb"; + coresight-name = "coresight-tpdm-south-cmb"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From 71b8a2ffafd6ed8a263dc57a707b8be0f93cf906 Mon Sep 17 00:00:00 2001 From: Fenil Panwala Date: Thu, 28 Nov 2024 14:11:08 +0530 Subject: [PATCH 40/67] ARM: dts: msm: Add memshare for tuna Memshare driver allocates and share the memory with the modem clients for their use. The device tree information for memshare driver on tuna is added to specify client details. Change-Id: I586040870c763494c18b273692d578b9b1a0bc10 Signed-off-by: Fenil Panwala --- qcom/tuna.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 7989917a..e3bb0ab8 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2048,6 +2048,51 @@ }; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + + qcom,client_ims_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x100000>; + qcom,client-id = <7>; + qcom,allocate-on-request; + qcom,shared; + label = "modem"; + }; + + qcom,client_ims_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x100000>; + qcom,client-id = <8>; + qcom,allocate-on-request; + qcom,shared; + label = "modem"; + }; + }; + google,debug-kinfo { compatible = "google,debug-kinfo"; memory-region = <&kinfo_mem>; From 3bef50a94b964c7d73026a1a7d503dfe67dd11c3 Mon Sep 17 00:00:00 2001 From: Akhil Budampati Date: Wed, 18 Dec 2024 12:41:56 +0530 Subject: [PATCH 41/67] ARM: dts: qcom: Add smmu-proxy-message-queue-pair node for tuna and kera Add smmu-proxy-message-queue-pair node for tuna and kera for CSF 2.5 feature. Change-Id: If0ef76a04f487fccb31928caeb98427a4eafbaac Signed-off-by: Akhil Budampati --- qcom/kera-vm.dtsi | 9 +++++++++ qcom/tuna-vm.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi index 452ce2e8..92359460 100644 --- a/qcom/kera-vm.dtsi +++ b/qcom/kera-vm.dtsi @@ -226,6 +226,15 @@ }; }; + smmu-proxy-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/smmu-proxy-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0xA>; + }; + msgqsock-msgq { vdevice-type = "message-queue-pair"; generate = "/hypervisor/msgqsock-msgq-pair"; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 93fd4c0c..28e6007b 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -301,6 +301,15 @@ }; }; + smmu-proxy-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/smmu-proxy-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0xA>; + }; + msgqsock-msgq { vdevice-type = "message-queue-pair"; generate = "/hypervisor/msgqsock-msgq-pair"; From 0c6044acc32cf6a4551b5e89303c02d65f8ebb53 Mon Sep 17 00:00:00 2001 From: Bhasker Reddy Komatireddy Date: Fri, 13 Dec 2024 13:58:53 +0530 Subject: [PATCH 42/67] ARM: dts: qcom: Add support for Kera IoT platform Add base device tree support for CDP platform for Kera IoT. Change-Id: I3242fd041fa15ad9d0a8316d6d3a9e1c304cd813 Signed-off-by: Bhasker Reddy Komatireddy --- qcom/Makefile | 1 + qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts | 18 ++++++++++++++++++ qcom/kera-iot-cdp-qca6750-ufs4.dtsi | 6 ++++++ qcom/platform_map.bzl | 1 + 4 files changed, 26 insertions(+) create mode 100644 qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts create mode 100644 qcom/kera-iot-cdp-qca6750-ufs4.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index ed06ed4a..2c009344 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -89,6 +89,7 @@ KERA_BOARDS += \ kera-cdp-qca6750-ufs2-overlay.dtbo \ kera-cdp-qca6750-ufs3-overlay.dtbo \ kera-cdp-qca6750-ufs4-overlay.dtbo \ + kera-iot-cdp-qca6750-ufs4-overlay.dtbo \ kera-qrd-wcn7750-ufs4-overlay.dtbo \ kera-qrd-wcn7750-ufs2-overlay.dtbo \ kera-qrd-wcn7750-ufs3-overlay.dtbo \ diff --git a/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts new file mode 100644 index 00000000..aaca3064 --- /dev/null +++ b/qcom/kera-iot-cdp-qca6750-ufs4-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-cdp-qca6750-ufs4-overlay.dts" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS4 for IoT"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x50001 0>; +}; diff --git a/qcom/kera-iot-cdp-qca6750-ufs4.dtsi b/qcom/kera-iot-cdp-qca6750-ufs4.dtsi new file mode 100644 index 00000000..b732b80b --- /dev/null +++ b/qcom/kera-iot-cdp-qca6750-ufs4.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-cdp-qca6750-ufs4.dtsi" diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index e795bebb..19173a92 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -123,6 +123,7 @@ _platform_map = { {"name": "kera-cdp-qca6750-ufs2-overlay.dtbo"}, {"name": "kera-cdp-qca6750-ufs3-overlay.dtbo"}, {"name": "kera-cdp-qca6750-ufs4-overlay.dtbo"}, + {"name": "kera-iot-cdp-qca6750-ufs4-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs4-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs2-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs3-overlay.dtbo"}, From 87876b303b5ed88248aed44850a6f1c186382d2e Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Tue, 17 Dec 2024 10:49:22 +0530 Subject: [PATCH 43/67] ARM: dts: qcom: Update HLOS Audio LPM memory region for kera Update the HLOS Audio LPM memory region for Kera to reflect the updated Slimbus memory mapping. Older Allocation: HLOS Slimbus Driver : Address: 0x6C8E000 + 0x2000 Q6 Slimbus Driver : Address: 0x6C90000 + 0x2000 Remaining Memory for Audio Driver : From 0x6C80000 up to 56KB. Updated Memory Layout: HLOS Slimbus Driver: Address: 0x6C92000+ 0x2000 Q6 Slimbus Driver: Address: 0x6C91000 + 0x1000 Audio Driver: Remaining 68KB Memory. Change-Id: I945fe7932ab8caa246bfca9cb1dcc02eb4bd903e Signed-off-by: Prasanna S --- qcom/kera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 805a0525..ed42e27c 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1115,7 +1115,7 @@ slimbam: bamdma@6c04000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>; + reg = <0x6c04000 0x20000>, <0x6c93000 0x1000>; reg-names = "bam", "bam_remote_mem"; interrupts = ; num-channels = <31>; @@ -1127,7 +1127,7 @@ slim_msm: slim@6c40000 { compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x6c40000 0x2c000>, <0x6c8E000 0x1000>; + reg = <0x6c40000 0x2c000>, <0x6c92000 0x1000>; reg-names = "ctrl", "slimbus_remote_mem"; interrupts = ; dmas = <&slimbam 3>, <&slimbam 4>; From 66c89fe720e820a508cb56a184026fce9de4864c Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Thu, 19 Dec 2024 12:19:56 +0530 Subject: [PATCH 44/67] ARM: dts: msm: Add glink probe entry for Tuna Add glink probe driver entry to Tuna to have a way for glink core to get pm notifications during apps suspend/resume. Change-Id: Id2e6328217312ae3f220d57cc1ec2c69d48942e9 Signed-off-by: Sarannya S --- qcom/tuna.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 7989917a..72f595c6 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1255,6 +1255,10 @@ }; }; + qcom,glink { + compatible = "qcom,glink"; + }; + sys-pm-vx@c320000 { compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna"; reg = <0xc320000 0x400>; From 42dfbf50fbb8fcce4469de524ea77849d053b5b1 Mon Sep 17 00:00:00 2001 From: songchai Date: Wed, 18 Dec 2024 23:03:09 -0800 Subject: [PATCH 45/67] ARM: dts: msm: correct apss-tpda's element size correct apss-tpda's element size. Change-Id: Ib5e1901ef9c893d3dc042a8153e91e2b64d79ab0 Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index a43b3421..77e6f70b 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -1934,8 +1934,15 @@ coresight-name = "coresight-tpda-apss"; + qcom,dsb-elem-size = <2 32>, + <5 32>, + <8 32>; + qcom,cmb-elem-size = <0 32>, - <1 32>; + <1 32>, + <3 32>, + <6 64>, + <7 64>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From 6317952c042a2eaf9eb7bb390b252b8e559f7178 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Fri, 20 Dec 2024 11:33:45 +0530 Subject: [PATCH 46/67] ARM: dts: msm: pcie: Set ultrashort channel settings TUNA PCIe Set RX settings mode to zero for Ultrashort channel settings for TUNA PCIe controller. Change-Id: Iff8a09f2ae474e8b8bec35a4dbbdc3df6fb40147 Signed-off-by: Vivek Pernamitta --- qcom/tuna-pcie.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi index 1080a5ca..336c5867 100644 --- a/qcom/tuna-pcie.dtsi +++ b/qcom/tuna-pcie.dtsi @@ -186,12 +186,12 @@ 0x1174 0x5c 0x0 0x1178 0x9c 0x0 0x117c 0x1a 0x0 - 0x1180 0x89 0x0 + 0x1180 0x8f 0x0 0x1170 0xdc 0x0 0x1188 0x94 0x0 0x118c 0x5b 0x0 0x1190 0x1a 0x0 - 0x1194 0x89 0x0 + 0x1194 0x8f 0x0 0x10cc 0x00 0x0 0x1008 0x09 0x0 0x1014 0x05 0x0 @@ -217,12 +217,12 @@ 0x1974 0x5c 0x0 0x1978 0x9c 0x0 0x197c 0x1a 0x0 - 0x1980 0x89 0x0 + 0x1980 0x8f 0x0 0x1970 0xdc 0x0 0x1988 0x94 0x0 0x198c 0x5b 0x0 0x1990 0x1a 0x0 - 0x1994 0x89 0x0 + 0x1994 0x8f 0x0 0x18cc 0x00 0x0 0x1808 0x09 0x0 0x1814 0x05 0x0 From 7fffe24d3db5d8774d5b3bb194f9aa1ef561574a Mon Sep 17 00:00:00 2001 From: songchai Date: Thu, 19 Dec 2024 22:42:56 -0800 Subject: [PATCH 47/67] ARM: dts: msm: correct apss-tpda's element size correct apss-tpda's element size for kera. Change-Id: I39218beffeee8cc70d46a4f427bf5805a2e1b63c Signed-off-by: songchai --- qcom/kera-coresight.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi index 62f2958f..256ff7d8 100644 --- a/qcom/kera-coresight.dtsi +++ b/qcom/kera-coresight.dtsi @@ -922,8 +922,12 @@ coresight-name = "coresight-tpda-apss"; + qcom,dsb-elem-size = <2 32>, + <8 32>; + qcom,cmb-elem-size = <0 32>, - <1 32>; + <1 32>, + <6 64>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From 9f99f6782eec1fd9efd62ff1d5b755b7246f850c Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 20 Dec 2024 14:12:20 +0530 Subject: [PATCH 48/67] ARM: dts: msm: Add pin configuration for USB3 PHY portselect on Kera TLMM pin is used to notify USB3/DP Combo PHY about the orientation. Select this pinctrl from the usb_qmp_dp_phy and ensure it is selecting the "usb0_phy_ps" pin function for Kera. Change-Id: Ib4c9b61a36473dc6a00cf7a271c54f2245d4f9d8 Signed-off-by: Uttkarsh Aggarwal --- qcom/kera-pinctrl.dtsi | 30 ++++++++++++++++++++++++++++++ qcom/kera-usb.dtsi | 3 +++ 2 files changed, 33 insertions(+) diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index 3eef2cd5..d50dca92 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -1860,6 +1860,36 @@ }; }; }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio122"; + function = "usb0_phy_ps"; + }; + + config { + pins = "gpio122"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + usb3phy_portselect_gpio: usb3phy_portselect_gpio { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + /* touchscreen pins */ pmx_ts_active { ts_active: ts_active { diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index 60032b6f..92e1213a 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -147,6 +147,9 @@ <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "global_phy_reset", "phy_reset"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = Date: Wed, 11 Dec 2024 17:22:17 +0530 Subject: [PATCH 49/67] ARM: dts: msm: Add pcie-pdc device for kera Add PCIe device to wakeup SoC from PCIe clk request gpio. Change-Id: I6d1e3f123ac1fc6de30fc7ece6def57e44961103 Signed-off-by: Sneh Mankad --- qcom/kera.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d39d3fdf..522e92ae 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -693,6 +693,11 @@ qcom,rproc-handle = <&adsp_pas>; }; + pcie_pdc: pdc@b360000 { + compatible = "qcom,kera-pcie-pdc", "qcom,pcie-pdc"; + reg = <0xb360000 0x10000>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,kera-adsp-pas"; reg = <0x03000000 0x10000>; From 202e2bbd82ce03f58435ca5025365444935b0706 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 23 Jul 2024 16:36:11 +0530 Subject: [PATCH 50/67] ARM: dts: msm: Add support for graphics clock controller on KERA Add support for GPU clock controller and move corresponding gdsc's from dummy to real on Kera platform. While at it, add the clocks property to camera and display gdscs. Change-Id: If3061a7603035e799e7548f0e2a93b7ded0e3005 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d39d3fdf..5d016158 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1845,8 +1845,17 @@ }; gpucc: clock-controller@3d90000 { - compatible = "qcom,dummycc"; - clock-output-names = "gpucc_clocks"; + compatible = "qcom,kera-gpucc", "syscon"; + reg = <0x3d90000 0xa000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + clock-names = "bi_tcxo", + "gpll0_out_main", + "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -3080,26 +3089,32 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_ofe_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_tfe_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; status = "ok"; }; &cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; interconnect-names = "mmnoc"; parent-supply = <&VDD_CX_LEVEL>; @@ -3107,11 +3122,13 @@ }; &disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; @@ -3161,13 +3178,17 @@ }; &gpu_cc_cx_gdsc { - compatible = "regulator-fixed"; reg = <0x3d99110 0x4>; + parent-supply = <&VDD_CX_LEVEL>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &gpu_cc_gx_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_GFX_LEVEL>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; From 0a06675a87e07787db28fdd9c8c363ed1fa723f2 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 23 Sep 2024 16:36:06 +0530 Subject: [PATCH 51/67] ARM: dts: msm: Add support for RPMHCC and DEBUGCC on Kera platform Add support for rpmh and debug clock controller nodes on Kera platform. While at it, keep rpmhcc node as dummy for KERA rumi platform. Change-Id: Ic11513d45bbc9b3f172a411f854a2348af4bfb94 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 6 ++++++ qcom/kera.dtsi | 52 +++++++++++++++++++++++++++++++++++++++------ 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 2b8a1e8c..8e1cfa60 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -158,3 +158,9 @@ &APSS_OFF { status = "disabled"; }; + +&rpmhcc { + compatible = "fixed-clock"; + clock-output-names = "rpmh_clocks"; + clock-frequency = <19200000>; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 5d016158..05843866 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -636,6 +636,11 @@ qcom,llcc-bcm-name = "SH5"; }; + + rpmhcc: clock-controller { + compatible = "qcom,tuna-rpmh-clk"; + #clock-cells = <1>; + }; }; }; @@ -1732,13 +1737,6 @@ }; }; - rpmhcc: clock-controller { - compatible = "fixed-clock"; - clock-output-names = "rpmh_clocks"; - clock-frequency = <19200000>; - #clock-cells = <1>; - }; - cambistmclkcc: clock-controller@1760000 { compatible = "qcom,tuna-cambistmclkcc", "syscon"; reg = <0x1760000 0x6000>; @@ -3083,6 +3081,46 @@ qcom,count-unit = <0x10000>; qcom,target-dev = <&qcom_ddr_dcvs_hw>; }; + + apsscc: syscon@17a80000 { + compatible = "syscon"; + reg = <0x17a80000 0x21000>; + }; + + mccc: syscon@240ba000 { + compatible = "syscon"; + reg = <0x240ba000 0x800>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,kera-debugcc"; + qcom,apsscc = <&apsscc>; + qcom,cambistmclkcc = <&cambistmclkcc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,tcsrcc = <&tcsrcc>; + qcom,videocc = <&videocc>; + qcom,mccc = <&mccc>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&cambistmclkcc 0>, + <&camcc 0>, + <&dispcc 0>, + <&gcc 0>, + <&gpucc 0>, + <&tcsrcc 0>, + <&videocc 0>; + clock-names = "xo_clk_src", + "cambistmclkcc", + "camcc", + "dispcc", + "gcc", + "gpucc", + "tcsrcc", + "videocc"; + #clock-cells = <1>; + }; }; #include "tuna-gdsc.dtsi" From 8d7f1a22a8fd8063710eba9b2740abfa42bf8071 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 12:26:45 +0530 Subject: [PATCH 52/67] ARM: dts: msm: Update videocc clock node as GenPD provider on Kera Mark videocc clock node as GenPD provider and disable the video GDSC regulator nodes for kera platform. While at it, keep the gdsc's as it is on kera-rumi platform. Change-Id: I4a41aacbaa7d144f72db48b9af3a336a92ef95aa Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 8e1cfa60..76d7f98c 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -164,3 +164,11 @@ clock-output-names = "rpmh_clocks"; clock-frequency = <19200000>; }; + +&video_cc_mvs0_gdsc { + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 05843866..4018f135 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1872,6 +1872,7 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; vdd_mxc-supply = <&VDD_MX_LEVEL>; + vdd_mm_mxc_voter-supply = <&VDD_CX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, @@ -1882,6 +1883,7 @@ "iface"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; qti,smmu-proxy { @@ -3233,14 +3235,12 @@ &video_cc_mvs0_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0c_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &reserved_memory { From f42efc56a8806138a4bd7d7ff7664a56b0d404c9 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 12 Dec 2024 15:59:26 +0530 Subject: [PATCH 53/67] dt-bindings: clock: qcom: add the DISPCC binding for kera Add DISPCC clock binding for kera platform. Change-Id: I3fd06bb26f5dd2b98653c0be22a2ff742de485ac Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,dispcc-sm8x50.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 0d15434e..4c5564e3 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -32,6 +32,7 @@ properties: - qcom,sun-dispcc - qcom,tuna-dispcc - qcom,tuna-dispcc-v1 + - qcom,kera-dispcc clocks: items: From fc794cac57689fd2829a815b5da54c9a3086e179 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 25 Sep 2024 16:36:41 +0530 Subject: [PATCH 54/67] ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera Mark dispcc clock node as GenPD provider and disable the display GDSC regulator nodes for kera platform. While at it, keep the gdsc's as it is on kera-rumi platform and update the compatible to align with freq plan. Change-Id: If01f876b3d160cf5c1cfe6be13e3e4b42f62cfa6 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 5 ++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 76d7f98c..e05aabe2 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -172,3 +172,11 @@ &video_cc_mvs0c_gdsc { status = "ok"; }; + +&disp_cc_mdss_core_gdsc { + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 4018f135..68308926 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1798,7 +1798,7 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,tuna-dispcc", "syscon"; + compatible = "qcom,kera-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; @@ -1814,6 +1814,7 @@ qcom,disp_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; gcc: clock-controller@100000 { @@ -3164,13 +3165,11 @@ &disp_cc_mdss_core_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gcc_pcie_0_gdsc { From 0e53b492e5461e31e71e6cec30ef8e072ec87e2d Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Tue, 24 Dec 2024 14:49:05 +0530 Subject: [PATCH 55/67] ARM: dts: msm: Remove vm dma heaps dtsi for kera The device tree for dma heaps on vm was incorrectly included. so, remove it. Fixes: 92398e011cce ("ARM: dts: msm: Enable securemsm related nodes for kera") Change-Id: Ib812725bedfd0510d6a998ecc83fe5df8619391c Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d39d3fdf..956a4e28 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -406,7 +406,6 @@ #include "kera-reserved-memory.dtsi" #include "msm-arm-smmu-kera.dtsi" #include "kera-dma-heaps.dtsi" -#include "kera-vm-dma-heaps.dtsi" &reserved_memory { #address-cells = <2>; From a2853c528bee6b48a68c3d39b5e387821e7e34f0 Mon Sep 17 00:00:00 2001 From: songchai Date: Tue, 24 Dec 2024 17:41:05 -0800 Subject: [PATCH 56/67] ARM: dts: msm: correct dl4-tpda's element size correct dl4-tpda's element size for tuna. Change-Id: Id29c520789977f41d74f31ec8d29d5e946278503 Signed-off-by: songchai --- qcom/tuna-coresight.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index 2bf4bfbd..0ca24200 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -796,10 +796,8 @@ coresight-name = "coresight-tpda-dl4"; - qcom,cmb-elem-size = <0 32>, - <1 32>, - <2 32>, - <3 32>; + qcom,dsb-elem-size = <16 32>; + qcom,cmb-elem-size = <17 32>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; From 7bbc05c5d6b0ee4d34dd0c593f7484b5f8ab7dc2 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Wed, 25 Dec 2024 13:00:22 +0530 Subject: [PATCH 57/67] ARM: dts: msm: Add High Speed USB support on Kera Currently, the node for eusb2_phy0 is defined but not used by controller which makes the associated resources to be consumed. Therefore if phy probes doesn't happen the controller goes into core soft reset failure. Fix this by utilizing the node in the controller. This will call the phy's probe and hence clocks & regulators will be initialized. Change-Id: Ica46af01154d5e583e011e4f2d84a80fb0589ac8 Signed-off-by: Udipto Goswami --- qcom/kera-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index 60032b6f..8e6f20b2 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -73,7 +73,7 @@ dma-coherent; interrupts = ; - usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>; + usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; From f9ccff95c8f626d0b10e5e64e6108677f28ad15e Mon Sep 17 00:00:00 2001 From: Priyansh Jain Date: Wed, 25 Dec 2024 12:44:26 +0530 Subject: [PATCH 58/67] ARM: dts: qcom: Add cooling cell property for gpu node for kera Add cooling cell property for gpu node for kera. Change-Id: Ic6c313f077c706817958c6941398c7c89aaa58cd Signed-off-by: Priyansh Jain --- qcom/kera-thermal.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/kera-thermal.dtsi b/qcom/kera-thermal.dtsi index f042a59c..7cc541af 100644 --- a/qcom/kera-thermal.dtsi +++ b/qcom/kera-thermal.dtsi @@ -5,6 +5,10 @@ #include +&msm_gpu { + #cooling-cells = <2>; +}; + &soc { tsens0: tsens0@c228000 { compatible = "qcom,tsens-v2"; @@ -196,6 +200,11 @@ }; }; + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + qcom,cpufreq-cdev { compatible = "qcom,cpufreq-cdev"; @@ -977,6 +986,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpuss-1 { @@ -1009,6 +1025,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; video { From f28b0bdded5243670d1cf9e6a2da0773ee5e200a Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 28 Aug 2024 14:16:14 +0530 Subject: [PATCH 59/67] ARM: dts: msm: Update gpucc node as GenPD provider Mark gpucc clock node as GenPD provider and disable the graphics GDSC regulator nodes. While at it, keep the gdsc's as it is on rumi platform. Change-Id: I91b4915723e26685e950de3ae575540ac3940036 Signed-off-by: Anaadi Mishra --- qcom/kera-rumi.dtsi | 8 ++++++++ qcom/kera.dtsi | 6 ++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index c3ef9498..343aecd6 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -180,3 +180,11 @@ &disp_cc_mdss_core_int2_gdsc { status = "ok"; }; + +&gpu_cc_cx_gdsc { + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + status = "ok"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cef15bc2..c107ded7 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1853,14 +1853,18 @@ reg-name = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_gx-supply = <&VDD_GFX_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; clock-names = "bi_tcxo", + "bi_tcxo_ao", "gpll0_out_main", "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; tcsrcc: clock-controller@1f40000 { @@ -3225,14 +3229,12 @@ parent-supply = <&VDD_CX_LEVEL>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &gpu_cc_gx_gdsc { parent-supply = <&VDD_GFX_LEVEL>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0_gdsc { From 7037f12c766641d1de718bf322bda90daf909088 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 12 Dec 2024 15:57:48 +0530 Subject: [PATCH 60/67] ARM: dts: msm: Move the pcie_1 clocks to protected-clocks Mark the pcie_1 clocks as protected and remove the pcie_1 gdsc nodes. Change-Id: I3102a52895a6531fb82a411bdb760073fc3c28f3 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index c107ded7..0cfad6d4 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1843,6 +1843,12 @@ "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + protected-clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_AUX_CLK_SRC>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, + <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_1_PIPE_DIV2_CLK_SRC>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -3192,12 +3198,10 @@ &gcc_pcie_1_gdsc { parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gcc_pcie_1_phy_gdsc { parent-supply = <&VDD_MX_LEVEL>; - status = "ok"; }; &gcc_ufs_mem_phy_gdsc { From 6c751c7e73cac130025fec1168c65d45b8b1d1fa Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Fri, 25 Oct 2024 10:16:16 +0530 Subject: [PATCH 61/67] ARM: dts: msm: Add support for cpufreq_hw node on KERA Add support for cpufreq_hw and cpufreq_hw_debug nodes on kera platform. While at it, set the default governor to performance on kera platform. Change-Id: Id6fd146d3c80f686780591e5efa594bd76155bcd Signed-off-by: Ajit Pandey --- qcom/kera.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 0cfad6d4..a6c5b1f9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -101,6 +101,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; @@ -125,6 +126,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; dynamic-power-coefficient = <100>; capacity-dmips-mhz = <1024>; @@ -139,6 +141,7 @@ cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_2>; #cooling-cells = <2>; dynamic-power-coefficient = <100>; @@ -158,6 +161,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_3>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -177,6 +181,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_4>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -196,6 +201,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_5>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -215,6 +221,7 @@ cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_6>; #cooling-cells = <2>; dynamic-power-coefficient = <263>; @@ -234,6 +241,7 @@ cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; next-level-cache = <&L2_7>; #cooling-cells = <2>; dynamic-power-coefficient = <289>; @@ -1905,6 +1913,24 @@ compatible = "smmu-proxy-sender"; }; + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17d91000 0x1000>, <0x17d92000 0x1000>, <0x17d93000 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; + #freq-domain-cells = <1>; + }; + + qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>; + }; + clk_virt: interconnect@0 { compatible = "qcom,kera-clk_virt"; #interconnect-cells = <1>; From 74c8fb319cd56a8432ee66c6b37dfde8bd12071c Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Tue, 24 Dec 2024 19:28:22 +0530 Subject: [PATCH 62/67] ARM: dts: msm: Enable CDP SLT platform for Kera Provide separate file for SLT so that ABL can pick it properly. Currently, ABL doesn't check if multiple board-id is added. Change-Id: I9140ca7b19f6b0b368798950145abbe28e32e778 Signed-off-by: Wasim Nazir --- qcom/Makefile | 1 + qcom/kera-cdp-qca6750-ufs4-overlay.dts | 2 +- qcom/kera-cdp-qca6750-ufs4-slt-overlay.dts | 19 +++++++++++++++++++ qcom/platform_map.bzl | 1 + 4 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 qcom/kera-cdp-qca6750-ufs4-slt-overlay.dts diff --git a/qcom/Makefile b/qcom/Makefile index 2c009344..4da30b34 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -90,6 +90,7 @@ KERA_BOARDS += \ kera-cdp-qca6750-ufs3-overlay.dtbo \ kera-cdp-qca6750-ufs4-overlay.dtbo \ kera-iot-cdp-qca6750-ufs4-overlay.dtbo \ + kera-cdp-qca6750-ufs4-slt-overlay.dtbo \ kera-qrd-wcn7750-ufs4-overlay.dtbo \ kera-qrd-wcn7750-ufs2-overlay.dtbo \ kera-qrd-wcn7750-ufs3-overlay.dtbo \ diff --git a/qcom/kera-cdp-qca6750-ufs4-overlay.dts b/qcom/kera-cdp-qca6750-ufs4-overlay.dts index 747e5c50..58e1fefb 100644 --- a/qcom/kera-cdp-qca6750-ufs4-overlay.dts +++ b/qcom/kera-cdp-qca6750-ufs4-overlay.dts @@ -15,5 +15,5 @@ "qcom,cdp"; qcom,msm-id = <686 0x10000>, <659 0x10000>; - qcom,board-id = <0x10001 0>, <0x40001 0>; + qcom,board-id = <0x10001 0>; }; diff --git a/qcom/kera-cdp-qca6750-ufs4-slt-overlay.dts b/qcom/kera-cdp-qca6750-ufs4-slt-overlay.dts new file mode 100644 index 00000000..e021fe36 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs4-slt-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-cdp-qca6750-ufs4.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS4 + SLT"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x40001 0>; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 19173a92..41162b2f 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -124,6 +124,7 @@ _platform_map = { {"name": "kera-cdp-qca6750-ufs3-overlay.dtbo"}, {"name": "kera-cdp-qca6750-ufs4-overlay.dtbo"}, {"name": "kera-iot-cdp-qca6750-ufs4-overlay.dtbo"}, + {"name": "kera-cdp-qca6750-ufs4-slt-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs4-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs2-overlay.dtbo"}, {"name": "kera-qrd-wcn7750-ufs3-overlay.dtbo"}, From cf4a2ab06ad66f7665eea549978cee8a0946259a Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Wed, 25 Dec 2024 02:28:11 +0530 Subject: [PATCH 63/67] ARM: dts: msm: Add supply for remoteproc instances Add supply for adsp/cdsp/modem instances. Change-Id: I07d21eea5db9074c6fe952466ce2d9af88c3b4d7 Signed-off-by: Wasim Nazir --- qcom/kera.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index cef15bc2..104b406f 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -707,7 +707,9 @@ reg = <0x03000000 0x10000>; status = "ok"; + cx-supply = <&VDD_LPI_CX_LEVEL>; cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; mx-uV-uA = ; reg-names = "cx", "mx"; @@ -785,8 +787,11 @@ reg = <0x32300000 0x10000>; status = "ok"; + cx-supply = <&VDD_CX_LEVEL>; cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; mx-uV-uA = ; + nsp-supply = <&VDD_NSP1_LEVEL>; nsp-uV-uA = ; reg-names = "cx","mx","nsp"; @@ -865,7 +870,9 @@ reg = <0x4080000 0x10000>; status = "ok"; + cx-supply = <&VDD_CX_LEVEL>; cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; mx-uV-uA = ; reg-names = "cx", "mx"; From ab05b35d77d9c5bcec37f22f4b176cab5fb37ebc Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 27 Dec 2024 22:13:53 +0530 Subject: [PATCH 64/67] ARM: dts: msm: tuna: Add USB_AXI clock for programming USB QoS Add USB AXI clock handle for accessing USB QoS register to program QoS. Change-Id: I4e0a0057e55283578ab6333f0da1b46c36e01fe5 Signed-off-by: Raviteja Laggyshetty --- qcom/tuna.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 4b16ef83..10b4c359 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2281,6 +2281,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { From ddb6fa17148e9c1c4bb34f51f197be9501568f21 Mon Sep 17 00:00:00 2001 From: Swetha Chintavatla Date: Tue, 24 Dec 2024 16:20:47 +0530 Subject: [PATCH 65/67] ARM: dts: msm: enable QoS programming for KERA Enable QoS programming for kera and add necessary AXI and AHB clock handles for programming QoS for USB, IPA and PCIE masters. Change-Id: I51bcc6a841005b6daf8ab3f22a79e6704dc3b3ed Signed-off-by: Swetha Chintavatla --- qcom/kera.dtsi | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d39d3fdf..67669614 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1901,7 +1901,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; cnoc_main: interconnect@1500000 { @@ -1910,7 +1909,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; system_noc: interconnect@1680000 { @@ -1919,7 +1917,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; pcie_noc: interconnect@16c0000 { @@ -1928,7 +1925,8 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; }; aggre1_noc: interconnect@16e0000 { @@ -1937,7 +1935,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -1946,7 +1944,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1780000 { @@ -1955,7 +1953,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; gem_noc: interconnect@24100000 { @@ -1964,7 +1961,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; nsp_noc: interconnect@320c0000 { @@ -1973,7 +1969,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_ag_noc: interconnect@7e40000 { @@ -1982,7 +1977,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_lpiaon_noc: interconnect@7400000 { @@ -1991,7 +1985,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_lpicx_noc: interconnect@7420000 { @@ -2000,7 +1993,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { From 02f2e181d10d4c1e5a7b05043821ad40a203d709 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Sun, 29 Dec 2024 14:08:07 +0530 Subject: [PATCH 66/67] ARM: dts: msm: enable touch support for Kera RCM platform Enable touch support for Kera RCM platform. Change-Id: Ib065708aaffd287f5ab12dd67cd3b2b7cda90c3f Signed-off-by: Anand Tarakh --- qcom/kera-rcm.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/qcom/kera-rcm.dtsi b/qcom/kera-rcm.dtsi index fccccc16..f9d8f28b 100644 --- a/qcom/kera-rcm.dtsi +++ b/qcom/kera-rcm.dtsi @@ -23,3 +23,44 @@ status = "ok"; }; + +&qupv3_se8_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + goodix,reset-gpio = <&tlmm 16 0x00>; + goodix,irq-gpio = <&tlmm 13 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L22B>; + iovdd-supply = <&L8B>; + goodix,touch-type = "primary"; + goodix,qts_en; + + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; From 0a6ca3411ea11488c5bbf975aa37ed333440c9a8 Mon Sep 17 00:00:00 2001 From: Yuhui Zhao Date: Fri, 27 Dec 2024 15:15:20 +0800 Subject: [PATCH 67/67] ARM: dts: msm: Correct FSA4480 I2C node Correct FSA4480 I2C node. Change-Id: I3e391d5f2984a9b17a60c670bfc6a5a3a20ca80d Signed-off-by: Yuhui Zhao --- qcom/kera-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi index c9e7fd9f..bc809756 100644 --- a/qcom/kera-qrd.dtsi +++ b/qcom/kera-qrd.dtsi @@ -24,7 +24,7 @@ status = "ok"; }; -&qupv3_se7_i2c { +&qupv3_se4_i2c { status = "ok"; fsa4480: fsa4480@42 { compatible = "qcom,fsa4480-i2c";