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bindings: soc: qcom: Add CRMV register

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Add CRMV register as required.
While at this also fix the issues with compilation failures.

 - Fix the schema path.
 - Fix max items in reg, interrupts properties.
 - Fix indentation.
 - Update examples.

Change-Id: I435ca457f3a2a60ac2c5063b7b65cfa4357ee7dd
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
This commit is contained in:
Minghao Zhang
2024-01-16 14:40:29 +05:30
parent 0f113cefea
commit bdae31f18b
1 changed files with 50 additions and 33 deletions
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83
bindings/soc/qcom/qcom,crm.yaml
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@@ -1,10 +1,13 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom-crm.yaml#
$id: http://devicetree.org/schemas/soc/qcom/qcom,crm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) CRM bindings
title: Qualcomm Technologies, Inc. (QTI) CESTA Resource Manager
maintainers:
- Maulik Shah <quic_mkshah@quicinc.com>
description:
Support for communication with the hardened-CRM blocks. A set of HW and
@@ -14,49 +17,45 @@ description:
properties:
label:
$ref: /schemas/types.yaml#/definitions/string-array
maxItems: 1
oneOf:
- items:
- const: cam_crm
- const: pcie_crm
- const: disp_crm
- description: Specifies the name of the CRM.
items:
- enum:
- cam_crm
- pcie_crm
- disp_crm
compatible:
enum:
- qcom,cam-crm
- qcom,pcie-crm
- qcom,cam-crm-v2
- qcom,pcie-crm-v2
- qcom,disp-crm-v2
oneOf:
- description: v1 of CESTA HW
items:
- enum:
- qcom,cam-crm
- qcom,pcie-crm
- description: v2 of CESTA HW
items:
- enum:
- qcom,cam-crm-v2
- qcom,pcie-crm-v2
- qcom,disp-crm-v2
reg:
maxItems: 4
items:
- description:
Should specify the addresses for the CRM device which includes
the base, common, crm_c and crm_b address.
minItems: 5
reg-names:
maxItems: 4
items:
- const: base
- const: common
- const: crm_b
- const: crm_c
- const: crm_v
- const: common
interrupts:
maxItems: 1
items:
- description: SW drv vote completion IRQ.
interrupt-names:
maxItems: 1
oneOf:
- items:
- const: cam_crm
- const: pcie_crm
- const: disp_crm
qcom,hw-drv-ids:
description: List of HW DRV IDs.
@@ -77,7 +76,6 @@ properties:
maximum: 1
clocks:
maxItems: 1
items:
- description: Bus Clock
@@ -96,7 +94,7 @@ oneOf:
if:
required:
- qcom,sw-drv-ids
- qcom,sw-drv-ids
then:
required:
- interrupts
@@ -108,11 +106,13 @@ examples:
# Example of Camera CRM device with HW DRVs
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,camcc-kalama.h>
cam_crm: crm@add7000 {
#include <dt-bindings/clock/qcom,camcc-sun.h>
cam_crm: crm@adcb000 {
label = "cam_crm";
compatible = "qcom,cam-crm";
reg = <0xadd7000 0x2000>;
reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>,
<0xadcf600 0x700>, <0xadcfd00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
qcom,hw-drv-ids = <0 1 2>;
};
@@ -122,10 +122,27 @@ examples:
pcie_crm: crm@1d01000 {
label = "pcie_crm";
compatible = "qcom,pcie-crm";
reg = <0x1d01000 0x3000>;
reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>,
<0x1d05800 0x700>, <0x1d05f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pcie_crm";
clocks = <&pcie_0_pipe_clk>;
qcom,sw-drv-ids = <0>;
};
# Example of Disp CRM device with SW DRVs
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sun.h>
disp_crm: crm@af21000 {
label = "disp_crm";
compatible = "qcom,disp-crm-v2";
reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>,
<0xaf29800 0x700>, <0xaf29f00 0x100>;
reg-names = "base", "crm_b", "crm_c", "crm_v", "common";
interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "disp_crm";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
qcom,sw-drv-ids = <0>;
};
...