Merge "dt-bindings: clock: Add gcc, debugcc and rpmhcc for sdxbaagha"

bindings/clock/qcom,debugcc.yaml

@@ -20,6 +20,7 @@ properties:
       - qcom,sun-debugcc
       - qcom,parrot-debugcc
       - qcom,sdx75-debugcc
+      - qcom,sdxbaagha-debugcc
       - qcom,sm4450-debugcc
       - qcom,monaco-debugcc
       - qcom,tuna-debugcc

bindings/clock/qcom,rpmhcc.yaml

@@ -26,6 +26,7 @@ properties:
       - qcom,sdx55-rpmh-clk
       - qcom,sdx65-rpmh-clk
       - qcom,sdx75-rpmh-clk
+      - qcom,sdxbaagha-rpmh-clk
       - qcom,sm4450-rpmh-clk
       - qcom,sm6350-rpmh-clk
       - qcom,sm8150-rpmh-clk

bindings/clock/qcom,sdxbaagha-gcc.yaml

@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sdxbaagha-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
+
+maintainers:
+  - Taniya Das <quic_tdas@quicinc.com>
+
+description: |
+  Global clock control module which supports the clocks, resets and
+  power domains on sdxbaagha
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-sdxbaagha.h
+
+properties:
+  compatible:
+    const: qcom,sdxbaagha-gcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board active XO source
+      - description: PCIE Pipe clock source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: bi_tcxo_ao
+      - const: pcie_pipe_clk
+      - const: sleep_clk
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@80000 {
+          compatible = "qcom,sdxbaagha-gcc";
+          reg = <0x80000 0x1f4200>;
+          clocks = <&rpmhcc RPMH_CXO_CLK>,<&rpmhcc RPMH_CXO_CLK_A>,
+                   <&pcie_pipe_clk>,<&sleep_clk>;
+          clock-names = "bi_tcxo","bi_tcxo_ao",
+                        "pcie_pipe_clk","sleep_clk";
+          #clock-cells = <1>;
+          #reset-cells = <1>;
+    };
+...