From 98ab567a07ea93fee164a3df2d94464428d5f7c2 Mon Sep 17 00:00:00 2001
From: David Collins <quic_collinsd@quicinc.com>
Date: Fri, 25 Aug 2023 16:26:58 -0700
Subject: [PATCH] dt-bindings: mfd: add qcom-i2c-pmic bindings

Add bindings for the I2C PMIC Controller.  This device handles
interrupts from an I2C PMIC and supports various subnodes which
each correspond to a PMIC peripheral (e.g. LDO regulator, GPIO,
etc).

Change-Id: I83528bd1239f1eb645f17a579216edc616ff2fcd
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
---
 bindings/mfd/qcom,i2c-pmic.yaml | 80 +++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 bindings/mfd/qcom,i2c-pmic.yaml

diff --git a/bindings/mfd/qcom,i2c-pmic.yaml b/bindings/mfd/qcom,i2c-pmic.yaml
new file mode 100644
index 00000000..e350ba79
--- /dev/null
+++ b/bindings/mfd/qcom,i2c-pmic.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qcom,i2c-pmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. I2C PMIC Controller Multi-Function Device
+
+maintainers:
+  - David Collins <quic_collinsd@quicinc.com>
+
+description: |
+  I2C PMIC controller multi-function devices communicate over an I2C bus. An I2C
+  PMIC controller node typically contains one or more child nodes corresponding
+  to the device's peripherals.
+
+  The controller also handles interrupts for all of the peripherals on the bus.
+  The controller takes a summary interrupt, deciphers which peripheral triggered
+  the interrupt, and determines which of the peripheral's interrupts were
+  triggered. It then notifies peripheral subdevices about the interrupts.
+
+properties:
+  compatible:
+    const: qcom,i2c-pmic
+
+  reg:
+    description: 7-bit I2C address of the device
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  interrupts:
+    maxItems: 1
+    description: Summary interrupt specifier
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 3
+
+  qcom,periph-map:
+    description: |
+      List of peripheral addresses specifying the mapping of peripherals to
+      summary status register bits. The mapping is ordered from the least
+      significant status bit to the most significant.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+      minimum: 0x0
+      maximum: 0xff
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: true
+
+examples:
+  - |
+    i2c_bus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        pmic@8 {
+            compatible = "qcom,i2c-pmic";
+            reg = <0x8>;
+            interrupt-parent = <&tlmm_pinmux>;
+            interrupts = <83 0>;
+            interrupt-controller;
+            #interrupt-cells = <3>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+            pinctrl-names = "default";
+            pinctrl-0 = <&smb_stat_active>;
+            qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>;
+        };
+    };