diff --git a/config/sun.mk b/config/sun.mk index 5ff2a2f5..7c40229e 100644 --- a/config/sun.mk +++ b/config/sun.mk @@ -9,3 +9,5 @@ dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera.dtbo dtbo-$(CONFIG_ARCH_TUNA) += tuna-camera-sensor-mtp.dtbo \ tuna-camera-sensor-cdp.dtbo \ tuna-camera-sensor-qrd.dtbo + +dtbo-$(CONFIG_ARCH_KERA) += kera-camera.dtbo diff --git a/kera-camera.dts b/kera-camera.dts new file mode 100644 index 00000000..81127fc1 --- /dev/null +++ b/kera-camera.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "kera-camera.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Kera SoC"; + compatible = "qcom,kera"; + qcom,msm-id = <686 0x10000>, <686 0x20000>, <659 0x10000>, <659 0x20000>; + qcom,board-id = <0 0>; +}; diff --git a/kera-camera.dtsi b/kera-camera.dtsi new file mode 100644 index 00000000..4d0e9a88 --- /dev/null +++ b/kera-camera.dtsi @@ -0,0 +1,1730 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + + +&soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + expanded_memory; + force_cache_allocs; + need_shared_buffer_padding; + #address-cells = <2>; + #size-cells = <2>; + + msm_cam_smmu_ife: msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1C00 0x00>; + dma-coherent; + cam-smmu-label = "ife"; + multiple-client-devices; + memory-region = <&cam_smmu_ife_resv_region>; + cam_smmu_ife_resv_region: cam_smmu_ife_resv_region { + iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>; + }; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 64 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address: 0x100000 */ + /* leaving 1 MB pad at start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xfffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0xf 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg: msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x18A0 0x00>; + cam-smmu-label = "jpeg"; + dma-coherent; + memory-region = <&cam_smmu_jpeg_resv_region>; + cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region { + iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>; + }; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* start address:0x100000 */ + /* leaving 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* Length: 0xffe00000 */ + /* leaving 1 MB pad at end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_icp: msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1820 0x00>, + <&apps_smmu 0x1800 0xC0>, + <&apps_smmu 0x1980 0x00>; + cam-smmu-label = "icp", "icp1"; + multiple-client-devices; + multiple-same-region-clients = "icp", "icp1"; + dma-coherent; + memory-region = <&cam_smmu_icp_resv_region>; + cam_smmu_icp_resv_region: cam_smmu_icp_resv_region { + iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>; + }; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared1 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0x80e00000 */ + iova-region-start = <0x0 0x80e00000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-shared2 { + /* Shared region is ~900MB long */ + iova-region-name = "shared"; + /* Start address: 0xb9200000 */ + iova-region-start = <0x0 0xb9200000>; + /* Length: 0x38400000 */ + iova-region-len = <0x0 0x38400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-fwuncached-region1 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80400000 */ + iova-region-start = <0x0 0x80400000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80500000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80400000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-region-fwuncached-region2 { + /* FW uncached region is 5 MB long */ + iova-region-name = "fw_uncached"; + /* Start address: 0x80900000 */ + iova-region-start = <0x0 0x80900000>; + /* Length: 0x500000 */ + iova-region-len = <0x0 0x500000>; + iova-region-id = <0x6>; + subregion_support; + status = "ok"; + + /* Used for HFI queues/sec heap */ + iova-mem-region-generic-region { + iova-region-name = "icp_hfi"; + iova-region-start = <0x0 0x80a00000>; + /* Length: 0x200000 */ + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x0>; + }; + + /* Global Sync Memory for IPC */ + iova-mem-region-global-sync-region { + iova-region-name = "global_sync"; + iova-region-start = <0x0 0x80900000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x3>; + phy-addr = <0x82600000>; + }; + }; + + iova-mem-device-region { + /* Device region is appropriate 1MB */ + iova-region-name = "device"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x300000>; + iova-region-id = <0x7>; + subregion_support; + status = "ok"; + + iova-mem-region-synx-hwmutex { + iova-region-name = "synx_hwmutex"; + iova-region-start = <0x0 0x80100000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x1>; + phy-addr = <0x1f4a000>; + }; + + iova-mem-region-ipc-hwmutex { + iova-region-name = "ipc_hwmutex"; + iova-region-start = <0x0 0x80101000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x2>; + phy-addr = <0x1f4b000>; + }; + + iova-mem-region-global_cntr { + iova-region-name = "global_cntr"; + iova-region-start = <0x0 0x80102000>; + iova-region-len = <0x0 0x1000>; + iova-region-id = <0x4>; + phy-addr = <0xc220000>; + }; + iova-mem-region-llcc-register { + iova-region-name = "llcc-register"; + iova-region-start = <0x0 0x80103000>; + iova-region-len = <0x0 0x200000>; + iova-region-id = <0x5>; + phy-addr = <0x26C00000>; + }; + }; + + iova-mem-region-io { + /* IO region is approximately 60 GB */ + iova-region-name = "io"; + /* Start address: 0xf1600000 */ + iova-region-start = <0x0 0xf1600000>; + /* Length: 0xf0ea00000 */ + iova-region-len = <0xf 0x0ea00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + /* Start address: 0x80000000 */ + iova-region-start = <0x0 0x80000000>; + /* Length: 0x100000 */ + iova-region-len = <0x0 0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x37790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cdm: msm_cam_smmu_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1860 0x00>; + cam-smmu-label = "rt-cdm"; + dma-coherent; + multiple-client-devices; + memory-region = <&cam_smmu_cdm_resv_region>; + cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region { + iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>, + <&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>; + }; + rt_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x0 0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0x0 0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + qti,smmu-proxy-cb-id = ; + }; + }; + + qcom,cam-cpas@ac04000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh"; + reg = <0x0ac04000 0x1000>, + <0x0ac62000 0x9200>, + <0x0ad90000 0x9000>, + <0x0bbf0000 0x1f00>; + reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000>; + interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt"; + interrupts = , + ; + camnoc-axi-min-ib-bw = <3000000000>; + cam-max-rt-axi-bw = <0x3 0x60447100>; + regulator-names = "top-gdsc"; + top-gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_drv_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_top_fast_ahb_clk", + "camnoc_rt_axi_clk_src", + "camnoc_rt_axi_clk", + "camnoc_nrt_axi_clk", + "cam_cc_drv_xo_clk", + "cam_cc_pll0", + "cam_cc_qdss_debug_xo_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_DRV_AHB_CLK>, + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_DRV_XO_CLK>, + <&camcc CAM_CC_PLL0>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>, + <0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "camnoc_rt_axi_clk_src"; + domain-id-support-clks = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clock-names-option = "ife_lite_csid_clk", + "ife_lite_ahb", "csid_clk_src", "csid_clk"; + clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>; + clock-rates-option = <400000000>, + <0>, <0>, <0>, <0>; + shared-clks-option = <0 0 0 1 0>; + control-camnoc-axi-clk; + cam-crmb-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + domain-id = , + ; + cam-icc-path-names = "cam_ahb"; + interconnect-names = "cam_ahb", + "cam_hf_0", + "cam_sf_0", + "cam_sf_icp"; + interconnects = <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF + &mc_virt SLAVE_EBI1>; + rpmh-bcm-info = <13 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", + "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", + "cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0", + "jpeg-dma0", "jpeg-enc0"; + sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf"; + sys-cache-uids = <71 72 73 74 75>; + sys-cache-concur = <1 1 1 0 0>; + enable-smart-qos; + rt-wr-priority-min = <4>; + rt-wr-priority-max = <5>; + rt-wr-priority-clamp = <6>; + rt-wr-slope-factor = <70>; + rt-wr-leaststressed-clamp-threshold = <10>; + rt-wr-moststressed-clamp-threshold = <6>; + rt-wr-highstress-indicator-threshold = <50>; + rt-wr-lowstress-indicator-threshold = <0>; + rt-wr-bw-ratio-scale-factor = <1>; + status = "ok"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt_rd_wr_sum: level3-rt-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + rt-axi-port; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_hf_0"; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = "cam_sf_0"; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + cam-icc-path-names = + "cam_sf_icp"; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt_wr: level2-rt-wr { + cell-index = <3>; + node-name = "level2-rt-wr"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt_rd: level2-rt-rd { + cell-index = <4>; + node-name = "level2-rt-rd"; + parent-node = <&level3_rt_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_wr: level2-nrt-wr { + cell-index = <5>; + node-name = "level2-nrt-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt_rd: level2-nrt-rd { + cell-index = <6>; + node-name = "level2-nrt-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_icp_rd: level2-icp-rd { + cell-index = <7>; + node-name = "level2-icp-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt1_wr: level1-rt1-wr { + cell-index = <8>; + node-name = " level1-rt1-ife-ubwc-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x4830>; + priority-lut-high-offset = <0x4834>; + }; + + level1_rt2_wr: level1-rt2-wr { + cell-index = <9>; + node-name = "level1-rt2-ife-stats"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <36>; + priority-lut-low-offset = <0x4A30>; + priority-lut-high-offset = <0x4A34>; + }; + + level1_rt3_wr: level1-rt3-wr { + cell-index = <10>; + node-name = "level1-rt3-ife-pdaf-lite"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_rt4_wr: level1-rt4-wr1 { + cell-index = <11>; + node-name = "level1-rt4-ife-rdi-wr"; + parent-node = <&level2_rt_wr>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <134>; + priority-lut-low-offset = <0x5230>; + priority-lut-high-offset = <0x5234>; + }; + + level1_rt3_rd: level1-rt3-rd { + cell-index = <12>; + node-name = "level1-rt3-cdm-rd"; + parent-node = <&level2_rt_rd>; + traffic-merge-type = + ; + rt-wr-niu; + niu-size = <92>; + priority-lut-low-offset = <0x4C30>; + priority-lut-high-offset = <0x4C34>; + }; + + level1_nrt2_wr: level1-nrt2-wr { + cell-index = <13>; + node-name = "level1-nrt2-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_wr: level1-nrt6-wr { + cell-index = <14>; + node-name = "level1-nrt6-wr"; + parent-node = <&level2_nrt_wr>; + traffic-merge-type = + ; + }; + + level1_nrt6_rd: level1-nrt6-rd { + cell-index = <15>; + node-name = "level1-nrt6-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt7_rd: level1-nrt7-rd { + cell-index = <16>; + node-name = "level1-nrt7-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <17>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt5_rd: level1-nrt5-rd { + cell-index = <18>; + node-name = "level1-nrt5-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt4_rd: level1-nrt4-rd { + cell-index = <19>; + node-name = "level1-nrt4-rd"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt3_wr: level1-nrt3-wr { + cell-index = <20>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + + level1_nrt9_rd: level1-nrt9-rd { + cell-index = <21>; + node-name = "level1-nrt3-wr"; + parent-node = <&level2_nrt_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <22>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <23>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <24>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <25>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <26>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt4_wr>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <27>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pdaf_linear_wr: ife0-pdaf-linear-wr { + cell-index = <28>; + node-name = "ife0-pdaf-linear-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife1_pdaf_linear_wr: ife1-pdaf-linear-wr { + cell-index = <29>; + node-name = "ife1-pdaf-linear-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife2_pdaf_linear_wr: ife2-pdaf-linear-wr { + cell-index = <30>; + node-name = "ife2-pdaf-linear-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <31>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt3_wr>; + }; + + ife0_stats_wr: ife0-stats-wr { + cell-index = <32>; + node-name = "ife0-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife1_stats_wr: ife1-stats-wr { + cell-index = <33>; + node-name = "ife1-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ife2_stats_wr: ife2-stats-wr { + cell-index = <34>; + node-name = "ife2-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt2_wr>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <35>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt_wr>; + }; + + cre0_all_wr: cre0-all-wr { + cell-index = <36>; + node-name = "cre0-all-wr"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt2_wr>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <37>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <38>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_wr>; + }; + + cre0_all_rd: cre0-all-rd { + cell-index = <39>; + node-name = "cre0-all-rd"; + client-name = "cre0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt5_rd>; + }; + + jpeg_enc0_all_rd: jpeg0-enc0-all-rd { + cell-index = <40>; + node-name = "jpeg-enc0-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + jpeg_dma0_all_rd: jpeg0-dma0-all-rd { + cell-index = <41>; + node-name = "jpeg-dma0-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt6_rd>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <42>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt7_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <43>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt7_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <44>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <45>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <46>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + rt_cdm3_all_rd: rt-cdm3-all-rd { + cell-index = <47>; + node-name = "rt-cdm3-all-rd"; + client-name = "rt-cdm3"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt3_rd>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <48>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + icp1_all_rd: icp1-all-rd { + cell-index = <49>; + node-name = "icp1-all-rd"; + client-name = "icp1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_icp_rd>; + }; + + ofe0_linear_wr: ofe0-linear-wr { + cell-index = <50>; + node-name = "ofe0-linear-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt2_wr>; + }; + + ofe0_in_rd: ofe0-in-rd { + cell-index = <51>; + node-name = "ofe0-in-rd"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt4_rd>; + }; + + ofe0_ubwc_wr: ofe0-ubwc-wr { + cell-index = <52>; + node-name = "ofe0-ubwc-wr"; + client-name = "ofe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt3_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,rt-cdm0@ac7f000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac7f000 0x580>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x7f000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <25>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac80000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac80000 0x580>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x80000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <26>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac81000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac81000 0x580>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x81000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <27>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm3@ac82000 { + cell-index = <3>; + compatible = "qcom,cam-rt-cdm2_2"; + label = "rt-cdm"; + reg = <0x0ac82000 0x580>; + reg-names = "rt-cdm3"; + reg-cam-base = <0x82000>; + interrupt-names = "rt-cdm3"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_cam_top_ahb_clk"; + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "turbo"; + nrt-device; + cdm-client-names = "ife3"; + config-fifo; + fifo-depths = <64 0 0 0>; + cam_hw_pid = <24>; + cam-hw-mid = <0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "mc_tfe"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@ad26000 { + cell-index = <0>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad27000 0x2b00>; + reg-cam-base = <0x127000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac86000{ + cell-index = <0>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0ac86000 0x10000>; + reg-cam-base = <0x86000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "gdsc", "tfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe0-supply = <&cam_cc_tfe_0_gdsc>; + clock-names = + "tfe_0_main_fast_ahb", + "tfe_0_clk_src", + "tfe_0_main_clk", + "cam_cc_camnoc_rt_tfe_0_main_clk", + "tfe_0_bayer_fast_ahb", + "tfe_0_bayer_clk", + "cam_cc_camnoc_rt_tfe_0_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_CLK_SRC>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_0_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe_0_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <0 9 16 4>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@ad29000 { + cell-index = <1>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad2a000 0x2b00>; + reg-cam-base = <0x12a000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac96000 { + cell-index = <1>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0ac96000 0x10000>; + reg-cam-base = <0x96000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "gdsc", "tfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe1-supply = <&cam_cc_tfe_1_gdsc>; + clock-names = + "tfe_1_main_fast_ahb", + "tfe_1_clk_src", + "tfe_1_main_clk", + "cam_cc_camnoc_rt_tfe_1_main_clk", + "tfe_1_bayer_fast_ahb", + "tfe_1_bayer_clk", + "cam_cc_camnoc_rt_tfe_1_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_CLK_SRC>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "tfe_1_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <1 10 17 5>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@ad2c000 { + cell-index = <2>; + compatible = "qcom,csid970"; + reg-names = "csid"; + reg = <0x0ad2d000 0x2b00>; + reg-cam-base = <0x12d000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "csid_clk_src", + "csid_clk", + "csiphy_rx_clk"; + clocks = + <&camcc CAM_CC_CSID_CLK_SRC>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>, + <480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@aca6000 { + cell-index = <2>; + compatible = "qcom,mc_tfe970"; + reg-names = "ife"; + reg = <0x0aca6000 0x10000>; + reg-cam-base = <0xa6000>; + rt-wrapper-base = <0x86000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "gdsc", "tfe2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + tfe2-supply = <&cam_cc_tfe_2_gdsc>; + clock-names = + "tfe_2_main_fast_ahb", + "tfe_2_clk_src", + "tfe_2_main_clk", + "cam_cc_camnoc_rt_tfe_2_main_clk", + "tfe_2_bayer_fast_ahb", + "tfe_2_bayer_clk", + "cam_cc_camnoc_rt_tfe_2_bayer_clk"; + clocks = + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_CLK_SRC>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_BAYER_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>; + clock-rates = + <0 445000000 0 0 0 0 0>, + <0 567000000 0 0 0 0 0>, + <0 644000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>, + <0 785000000 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "tfe_2_clk_src"; + clock-control-debugfs = "true"; + ubwc-static-cfg = <0x1026 0x1026>; + cam_hw_pid = <2 8 18 6>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,csid-lite970"; + reg-names = "csid-lite"; + reg = <0x0ad6d000 0xa00>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "csid-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 1 0 0 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 400000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>, + <0 480000000 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@ad6c000 { + cell-index = <3>; + compatible = "qcom,vfe-lite970"; + reg-names = "ife-lite"; + reg = <0x0ad6d000 0x2800>; + reg-cam-base = <0x16d000>; + rt-wrapper-base = <0x16c000>; + interrupt-names = "ife-lite0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <0 0 0 1 0 0>; + clock-names = + "ife_lite_ahb", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_camnoc_rt_ife_lite_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>; + clock-rates = + <0 0 0 400000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>, + <0 0 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <19>; + status = "ok"; + }; + + qcom,cam-icp0 { + compatible = "qcom,cam-icp0"; + cell-index = <0>; + compat-hw-name = "qcom,icp0", + "qcom,ipe0"; + num-icp = <1>; + num-ipe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + synx_signaling_en; + }; + + qcom,cam-icp1 { + compatible = "qcom,cam-icp1"; + cell-index = <1>; + compat-hw-name = "qcom,icp1", + "qcom,ofe"; + num-icp = <1>; + num-ofe = <1>; + status = "ok"; + icp_pc_en; + icp_use_pil; + ipe_bps_pc_en; + }; + + cam_icp0: qcom,icp0@ac05000 { + cell-index = <0>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac06000 0x1000>, + <0x0ac09000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x6000 0x9000>; + interrupt-names = "icp"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_mem>; + clock-names = + "icp_ahb_clk", + "icp_clk_src", + "icp_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_0_AHB_CLK>, + <&camcc CAM_CC_ICP_0_CLK_SRC>, + <&camcc CAM_CC_ICP_0_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "icp_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_970"; + ubwc-ipe-fetch-cfg = <0x707B 0x707B>; + ubwc-ipe-write-cfg = <0x161EF 0x161EF>; + qos-val = <0x808>; + fw-pas-id = <33>; + cam_hw_pid = <11>; + status = "ok"; + }; + + cam_icp1: qcom,icp1@ac15000 { + cell-index = <1>; + compatible = "qcom,cam-icp_v2_1"; + icp-version = <0x0201>; + reg = <0x0ac16000 0x1000>, + <0x0ac19000 0x1000>; + reg-names = "icp_csr", "icp_wd0"; + reg-cam-base = <0x16000 0x19000>; + interrupt-names = "icp1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + memory-region = <&camera_2_mem>; + clock-names = + "icp_1_ahb_clk", + "icp_1_clk_src", + "icp_1_clk", + "camcc_debug_clk"; + clocks = + <&camcc CAM_CC_ICP_1_AHB_CLK>, + <&camcc CAM_CC_ICP_1_CLK_SRC>, + <&camcc CAM_CC_ICP_1_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-rates = + <0 400000000 0 0>, + <0 480000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>, + <0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "icp_1_clk_src"; + clock-control-debugfs = "true"; + fw_name = "CAMERA_ICP_1_970"; + ubwc-ofe-fetch-cfg = <0x707B 0x707B>; + ubwc-ofe-write-cfg = <0x161EF 0x161EF>; + qos-val = <0x808>; + fw-pas-id = <50>; + cam_hw_pid = <10>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe680"; + reg = <0x0ac42000 0x18000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_nps_ahb_clk", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk", + "ipe_pps_clk", + "cam_cc_camnoc_nrt_ipe_nps_clk"; + clocks = + <&camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&camcc CAM_CC_IPE_NPS_CLK>, + <&camcc CAM_CC_IPE_PPS_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>; + clock-rates = + <0 0 0 450000000 0 0 0>, + <0 0 0 575000000 0 0 0>, + <0 0 0 675000000 0 0 0>, + <0 0 0 825000000 0 0 0>, + <0 0 0 825000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <15 14 26 27>; + status = "ok"; + }; + + cam_ofe: qcom,ofe@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam-ofe"; + reg = <0x0ac2a000 0x18000>; + reg-names = "ofe0_top"; + reg-cam-base = <0x2a000>; + regulator-names = "ofe0-vdd"; + ofe0-vdd-supply = <&cam_cc_ofe_gdsc>; + clock-names = + "camnoc_nrt_ofe_anchor", + "camnoc_nrt_ofe_hdr", + "ofe_clk_src", + "ofe_main_clk", + "camnoc_nrt_ofe_main_clk", + "ofe_ahb_clk", + "ofe_anchor_clk", + "ofe_anchor_fast_ahb", + "ofe_hdr_fast_ahb", + "ofe_hdr_clk", + "ofe_main_fast_ahb"; + clocks = + <&camcc CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_CLK_SRC>, + <&camcc CAM_CC_OFE_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>, + <&camcc CAM_CC_OFE_AHB_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_CLK>, + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>, + <&camcc CAM_CC_OFE_HDR_CLK>, + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>; + clock-rates = + <0 0 436000000 0 0 0 0 0 0 0 0>, + <0 0 570000000 0 0 0 0 0 0 0 0>, + <0 0 675000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>, + <0 0 757000000 0 0 0 0 0 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + nrt-device; + src-clock-name = "ofe_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <13 28 6>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc0", + "qcom,jpegdma0"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc0: qcom,jpegenc0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc_780"; + reg-names = "jpegenc_hw", "cam_camnoc_nrt"; + reg = <0x0ac25000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x25000 0x62000>; + interrupt-names = "jpeg_enc0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegenc_clk_src", + "jpegenc_0_clk", + "jpegenc_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <17 19>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + + cam_jpeg_dma0: qcom,jpegdma0@ac26000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma_780"; + reg-names = "jpegdma_hw", "cam_camnoc_nrt"; + reg = <0x0ac26000 0x1000>, + <0x0ac62000 0x9200>; + reg-cam-base = <0x26000 0x62000>; + interrupt-names = "jpeg_dma0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + shared-clks = <1 0 0>; + clock-names = + "jpegdma_clk_src", + "jpegdma_0_clk", + "jpegdma_1_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_0_CLK>, + <&camcc CAM_CC_JPEG_1_CLK>; + clock-rates = <600000000 0 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + nrt-device; + cam_hw_pid = <16 18>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; + status = "ok"; + }; + +};