ARM: dts: msm: dt snapshot for monaco target

DT snapshot from branch msm-5.15.c2 commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute"). Change-Id: If3e807289b6d981865430c4e1a45dabf236fa345 Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
2024-03-11 15:01:31 +05:30
parent 1a37a8d13b
commit b471e42ad0
47 changed files with 12247 additions and 0 deletions
--- a/qcom/monaco-usb.dtsi
+++ b/qcom/monaco-usb.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-monaco.h>
+#include <dt-bindings/interconnect/qcom,monaco.h>
+
+&soc {
+	/* Primary USB port related controller */
+	usb0: hsusb@4e00000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x4e00000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq", "hs_phy_irq";
+
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_USB2_PRIM_CLKREF_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"xo", "sleep_clk", "utmi_clk";
+
+		resets = <&gcc GCC_USB20_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
+		dpdm-supply = <&usb2_phy0>;
+		extcon = <&eud>;
+
+		qcom,core-clk-rate = <60000000>;
+		qcom,default-bus-vote = <2>; /* use svs bus voting */
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
+				<&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
+				<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
+
+		qcom,pm-qos-latency = <2>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+
+		dwc3@4e00000 {
+			compatible = "snps,dwc3";
+			reg = <0x4e00000 0xcd00>;
+
+			iommus = <&apps_smmu 0x120 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@1613000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x1613000 0x120>,
+			<0x01612000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L12A>;
+		vdda18-supply = <&L14A>;
+		vdda33-supply = <&L25A>;
+		qcom,vdd-voltage-level = <0 904000 904000>;
+
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+};