ARM: dts: msm: dt snapshot for monaco target

DT snapshot from branch msm-5.15.c2
commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute").

Change-Id: If3e807289b6d981865430c4e1a45dabf236fa345
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>

qcom/monaco-thermal-overlay.dtsi

@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&thermal_zones {
+	pm5100-tz {
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&CPU0 1 1>;
+			};
+
+			trip1_cpu2 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip1_cpu3 {
+				trip = <&pm5100_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl0 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&CPU0 2 2>;
+			};
+
+			cpu2_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			cpu3_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl1 {
+		cooling-maps {
+			cpu0_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&CPU0 2 2>;
+			};
+
+			cpu1_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+
+	pm5100-bcl-lvl2 {
+		cooling-maps {
+			/* Need to update once we get fine tuned data */
+		};
+	};
+
+	socd {
+		cooling-maps {
+			soc_cpu0 {
+				trip = <&socd_trip>;
+				cooling-device = <&CPU0 1 1>;
+			};
+
+			soc_cpu2 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			soc_cpu3 {
+				trip = <&socd_trip>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			gpu_cdev {
+				trip = <&socd_trip>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+};