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ARM: dts: msm: dt snapshot for monaco target

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DT snapshot from branch msm-5.15.c2
commit 8ae5ffe89e0f ("ARM: dts: msm: Add mdsp heap for mDSP compute").

Change-Id: If3e807289b6d981865430c4e1a45dabf236fa345
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
This commit is contained in:
Naresh Kumar Lingagalla
2024-03-11 15:01:31 +05:30
parent 1a37a8d13b
commit b471e42ad0
47 changed files with 12247 additions and 0 deletions
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505
qcom/monaco-qupv3.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup0 5: SE 5
* Qup0 6: SE 6
* Qup0 7: SE 7
*/
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@4a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x4a00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xf6 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0xf>;
qcom,ev-factor = <2>;
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x4ac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0xe3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
ranges;
status = "ok";
/* Debug UART Instance */
qupv3_se6_2uart: qcom,qup_uart@4a98000 {
compatible = "qcom,geni-debug-uart";
reg = <0x4a98000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se6_2uart_rx_active>;
pinctrl-1 = <&qupv3_se6_2uart_sleep>;
status = "disabled";
};
/* HS UART Instance */
qupv3_se5_4uart: qcom,qup_uart@4a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0x4a94000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 29 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
<&qupv3_se5_tx>, <&qupv3_se5_rx>;
pinctrl-2 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
qcom,wakeup-byte = <0xFD>;
status = "disabled";
};
qupv3_se0_i2c: i2c@4a80000 {
compatible = "qcom,i2c-geni";
reg = <0x4a80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma0 0 0 3 64 0>,
<&gpi_dma0 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se0_spi: spi@4a80000 {
compatible = "qcom,spi-geni";
reg = <0x4a80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma0 0 0 1 64 0>,
<&gpi_dma0 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se1_i2c: i2c@4a84000 {
compatible = "qcom,i2c-geni";
reg = <0x4a84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma0 1 0 3 64 0>,
<&gpi_dma0 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@4a84000 {
compatible = "qcom,spi-geni";
reg = <0x4a84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma0 0 1 1 64 0>,
<&gpi_dma0 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se2_i2c: i2c@4a88000 {
compatible = "qcom,i2c-geni";
reg = <0x4a88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
dmas = <&gpi_dma0 0 2 3 64 0>,
<&gpi_dma0 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se2_spi: spi@4a88000 {
compatible = "qcom,spi-geni";
reg = <0x4a88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
dmas = <&gpi_dma0 0 2 1 64 0>,
<&gpi_dma0 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se3_i2c: i2c@4a8c000 {
compatible = "qcom,i2c-geni";
reg = <0x4a8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
dmas = <&gpi_dma0 0 3 3 64 0>,
<&gpi_dma0 1 3 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se3_spi: spi@4a8c000 {
compatible = "qcom,spi-geni";
reg = <0x4a8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
<&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
pinctrl-1 = <&qupv3_se3_spi_sleep>;
dmas = <&gpi_dma0 0 3 1 64 0>,
<&gpi_dma0 1 3 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@4a90000 {
compatible = "qcom,i2c-geni";
reg = <0x4a90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma0 0 4 3 64 0>,
<&gpi_dma0 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se4_spi: spi@4a90000 {
compatible = "qcom,spi-geni";
reg = <0x4a90000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>, <&qupv3_se4_spi_cs_sleep> ;
dmas = <&gpi_dma0 0 4 1 64 0>,
<&gpi_dma0 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se5_i2c: i2c@4a94000 {
compatible = "qcom,i2c-geni";
reg = <0x4a94000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
dmas = <&gpi_dma0 0 5 3 64 0>,
<&gpi_dma0 1 5 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se5_spi: spi@4a94000 {
compatible = "qcom,spi-geni";
reg = <0x4a94000 0x4000>;
reg-names = "se_phys";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
dmas = <&gpi_dma0 0 5 1 64 0>,
<&gpi_dma0 1 5 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se6_i2c: i2c@4a98000 {
compatible = "qcom,i2c-geni";
reg = <0x4a98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma0 0 6 3 64 0>,
<&gpi_dma0 1 6 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se6_spi: spi@4a98000 {
compatible = "qcom,spi-geni";
reg = <0x4a98000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma0 0 6 1 64 0>,
<&gpi_dma0 1 6 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c_a: i2c_a@4a9c000 {
compatible = "qcom,i2c-geni";
reg = <0x4a9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_a>, <&qupv3_se7_i2c_scl_a>;
pinctrl-1 = <&qupv3_se7_i2c_sleep_a>;
dmas = <&gpi_dma0 0 7 3 64 0>,
<&gpi_dma0 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se7_spi_a: spi@4a9c000 {
compatible = "qcom,spi-geni";
reg = <0x4a9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_mosi_a>, <&qupv3_se7_spi_miso_a>,
<&qupv3_se7_spi_clk_a>, <&qupv3_se7_spi_cs_a>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma0 0 7 1 64 0>,
<&gpi_dma0 1 7 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c_b: i2c_b@4a9c000 {
compatible = "qcom,i2c-geni";
reg = <0x4a9c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_b>, <&qupv3_se7_i2c_scl_b>;
pinctrl-1 = <&qupv3_se7_i2c_sleep_b>;
dmas = <&gpi_dma0 0 7 3 64 0>,
<&gpi_dma0 1 7 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
};
};