diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index 555eadf1..ddbc78f4 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8550-llcc - qcom,pineapple-llcc - qcom,sun-llcc + - qcom,sdxpinn-llcc - qcom,kera-llcc - qcom,x1e80100-llcc @@ -60,26 +61,26 @@ properties: - const: qcom,llcc-perfmon - const: qcom,scid-heuristics - qcom,heuristics_scid: + qcom,heuristics-scid: $ref: '/schemas/types.yaml#/definitions/uint32' description: | SCID number of HEURISTICS SID - freq,threshold_idx: + qcom,freq-threshold-idx: $ref: '/schemas/types.yaml#/definitions/uint32-array' description: | CPU DVFS frequency threshold index minItems: 1 maxItems: 2 - freq,threshold_residency: + qcom,frequency-threshold-residency: $ref: '/schemas/types.yaml#/definitions/uint32-array' description: | CPU DVFS frequency threshold Residency value in micro seconds minItems: 1 maxItems: 2 - qcom,scid_heuristics_enabled: + qcom,scid-heuristics-enabled: description: | - On enabling this flag, Heristics driver will communicate to qcom - control software to enable the Heristics based SCID functionality. + On enabling this flag, Heuristics driver will communicate to qcom + control software to enable the Heuristics based SCID functionality. type: boolean required: @@ -141,10 +142,10 @@ examples: scid_heuristics { compatible = "qcom,scid-heuristics"; - qcom,heuristics_scid = <32>; - freq,threshold_idx = <11>, <10>; - freq,threshold_residency = <5000>, <5000>; - qcom,scid_heuristics_enabled; + qcom,heuristics-scid = <32>; + qcom,freq-threshold-idx = <11>, <10>; + qcom,frequency-threshold-residency = <5000>, <5000>; + qcom,scid-heuristics-enabled; }; }; }; diff --git a/bindings/clock/qcom,cambistmclkcc.yaml b/bindings/clock/qcom,cambistmclkcc.yaml index 1d178d46..87114edd 100644 --- a/bindings/clock/qcom,cambistmclkcc.yaml +++ b/bindings/clock/qcom,cambistmclkcc.yaml @@ -20,6 +20,7 @@ properties: enum: - qcom,sun-cambistmclkcc - qcom,tuna-cambistmclkcc + - qcom,sun-cambistmclkcc-v2 clocks: items: diff --git a/bindings/pinctrl/qcom,pmic-gpio.yaml b/bindings/pinctrl/qcom,pmic-gpio.yaml index a68c1301..cc3fbe2a 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -28,6 +28,7 @@ properties: - qcom,pm6450-gpio - qcom,pm7250b-gpio - qcom,pm7325-gpio + - qcom,pm7550ba-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio - qcom,pm8018-gpio @@ -59,6 +60,7 @@ properties: - qcom,pmi8994-gpio - qcom,pmi8998-gpio - qcom,pmih010x-gpio + - qcom,pmiv0108-gpio - qcom,pmk8350-gpio - qcom,pmk8550-gpio - qcom,pmm8155au-gpio @@ -179,6 +181,7 @@ allOf: - qcom,pm8350b-gpio - qcom,pm8550ve-gpio - qcom,pm8950-gpio + - qcom,pm7550ba-gpio then: properties: gpio-line-names: @@ -218,6 +221,7 @@ allOf: - qcom,pmc8180-gpio - qcom,pmi8994-gpio - qcom,pmm8155au-gpio + - qcom,pmiv0108-gpio then: properties: gpio-line-names: @@ -433,6 +437,7 @@ $defs: - gpio1-gpio9 for pm6450 - gpio1-gpio12 for pm7250b - gpio1-gpio10 for pm7325 + - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 - gpio1-gpio6 for pm8018 @@ -463,6 +468,7 @@ $defs: - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio18 for pmih010x + - gpio1-gpio10 for pmiv0108 - gpio1-gpio4 for pmk8350 - gpio1-gpio6 for pmk8550 - gpio1-gpio10 for pmm8155au diff --git a/qcom/qcom,cycle-cntr.yaml b/bindings/soc/qcom/qcom,cycle-cntr.yaml similarity index 100% rename from qcom/qcom,cycle-cntr.yaml rename to bindings/soc/qcom/qcom,cycle-cntr.yaml diff --git a/bindings/soc/qcom/qcom,mpam-msc.yaml b/bindings/soc/qcom/qcom,mpam-msc.yaml new file mode 100644 index 00000000..530c81ed --- /dev/null +++ b/bindings/soc/qcom/qcom,mpam-msc.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,mpam-msc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) MPAM MSC + +maintainers: + - Avinash Philip + +description: | + The Qualcomm Technologies, Inc. (QTI) MPAM MSC abstraction to + describe MPAM MSC topology. MPAM (Memory System Resource + Partitioning and Monitoring) specification is supporting + different type of MSC (Memory System Component) to control the + resources like cache allocation, bandwidth etc and monitoring + the utilization. MPAM MSC child node for SLC (System Level Cache) + defines SLC side support for MPAM gear (capacity) configuration + and monitor side support. Child node abstraction helps to understand + system level MPAM topology. + +properties: + compatible: + items: + - const: qcom,mpam-msc + + child-node: + description: | + Child node for mpam slc msc device + type: object + properties: + compatible: + items: + - const: qcom,slc-mpam + + reg: + items: + - description: | + address and size of CPUCP DTIM area for CPUCP SLC monitor data + + reg-names: + items: + - const: mon-base + + qcom,msc-id: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + MSC id of the child node. + + qcom,msc-name: + $ref: '/schemas/types.yaml#/definitions/string' + description: | + MSC name of the child node. + + qcom,dev-index: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Device index for the MSC device + + qcom,num-read-miss-cfg: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Number of read miss configurations present. + + qcom,num-cap-cfg: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Number of capacity configrurations present, + + qcom,slc-clients: + $ref: '/schemas/types.yaml#/definitions/string-array' + description: | + APPS_CLIENT + APPS SLC Client + GPU_CLIENT + GPU SLC Client + NSP_CLIENT + NSP SLC client + + required: + - compatible + - reg + - reg-names + - qcom,msc-id + - qcom,msc-name + - qcom,dev-index + - qcom,num-read-miss-cfg + - qcom,num-cap-cfg + - qcom,slc-clients + + additionalProperties: false + +required: + - compatible + - address-cells + - size-cells + - ranges + +additionalProperties: false + +examples: + - | + qcom-mpam-msc { + compatible = "qcom,mpam-msc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom-slc-mpam@17b6f800 { + compatible = "qcom,slc-mpam"; + reg = <0x17b6f800 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <2>; + qcom,msc-name = "slc"; + qcom,dev-index = <0>; + qcom,num-read-miss_cfg = <2>; + qcom,num-cap-cfg = <5>; + qcom,slc-clients = "APPS_CLIENT", "GPU_CLIENT", + "NSP_CLIENT"; + }; + }; diff --git a/bindings/usb/qcom,dwc-usb3-msm.yaml b/bindings/usb/qcom,dwc-usb3-msm.yaml index ee819cae..96d9b20a 100644 --- a/bindings/usb/qcom,dwc-usb3-msm.yaml +++ b/bindings/usb/qcom,dwc-usb3-msm.yaml @@ -104,6 +104,10 @@ properties: description: disable cm l1. type: boolean + qcom,sleep-clk-bcr: + description: If present, use additional delay after BCR. + type: boolean + qcom,core-clk-rate: description: Core/Master clock rate. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/qcom/Makefile b/qcom/Makefile index e309beee..6c58c159 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -172,7 +172,8 @@ endif ifeq ($(CONFIG_ARCH_SDXKOVA), y) sdxkova-dtb-$(CONFIG_ARCH_SDXKOVA) += sdxkova-idp-cpe.dtb \ - sdxkova-idp-mbb.dtb + sdxkova-idp-mbb.dtb \ + sdxkova-idp-m2.dtb dtb-y += $(sdxkova-dtb-y) endif @@ -219,6 +220,37 @@ monaco-dtb-$(CONFIG_ARCH_MONACO) += \ monaco-overlays-dtb-$(CONFIG_ARCH_MONACO) += $(MONACO_BOARDS) $(MONACO_BASE_DTB) dtb-y += $(monaco-dtb-y) +ifeq ($(CONFIG_ARCH_PARROT), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +parrot_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += parrot-vm-rumi.dtb \ + parrot-vm-atp.dtb \ + parrot-vm-idp.dtb \ + parrot-vm-idp-wcn3990.dtb \ + parrot-vm-idp-wcn3990-amoled-rcm.dtb \ + parrot-vm-idp-wcn6750-amoled.dtb \ + parrot-vm-idp-wcn6750-amoled-rcm.dtb \ + parrot-vm-qrd.dtb \ + parrot-vm-qrd-wcn6750.dtb + +dtb-y += $(parrot_tuivm-dtb-y) + +endif +endif + +ifeq ($(CONFIG_ARCH_RAVELIN), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +parrot_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += ravelin-vm-rumi.dtb \ + ravelin-vm-atp.dtb \ + ravelin-vm-idp.dtb \ + ravelin-vm-idp-wcn3988.dtb \ + ravelin-vm-idp-wcn3950-amoled-rcm.dtb \ + ravelin-vm-qrd.dtb + +dtb-y += $(parrot_tuivm-dtb-y) + +endif +endif + always-y := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/kera-dma-heaps.dtsi b/qcom/kera-dma-heaps.dtsi index 6472b080..ac87057a 100644 --- a/qcom/kera-dma-heaps.dtsi +++ b/qcom/kera-dma-heaps.dtsi @@ -9,5 +9,11 @@ qcom,dma-heaps { compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,cma-secure-cdsp"; + qcom,dma-heap-type = ; + memory-region = <&cdsp_secure_heap_cma>; + }; }; }; diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index f0567b81..1aa1ce71 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -4,4 +4,44 @@ */ &tlmm { + qupv3_se13_2uart_pins: qupv3_se13_2uart_pins { + qupv3_se13_2uart_tx_active: qupv3_se13_2uart_tx_active { + mux { + pins = "gpio18"; + function = "qup2_se5_l2"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_2uart_rx_active: qupv3_se13_2uart_rx_active { + mux { + pins = "gpio19"; + function = "qup2_se5_l3"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; diff --git a/qcom/kera-qupv3.dtsi b/qcom/kera-qupv3.dtsi new file mode 100644 index 00000000..5f79ee9c --- /dev/null +++ b/qcom/kera-qupv3.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3_2 Wrapper Instance */ + qupv3_2: qcom,qupv3_1_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + ranges; + status = "ok"; + + /* Debug UART Instance */ + qupv3_se13_2uart: qcom,qup_uart@894000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_2uart_tx_active>, <&qupv3_se13_2uart_rx_active>; + pinctrl-1 = <&qupv3_se13_2uart_sleep>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d75b7787..0fbeb4e6 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -39,7 +39,9 @@ qcom_scm: qcom_scm { }; }; - aliases {}; + aliases { + serial0 = &qupv3_se13_2uart; + }; cpus { #address-cells = <2>; @@ -489,6 +491,12 @@ status = "ok"; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -721,7 +729,28 @@ no-map; reg = <0x0 0x81c60000 0x0 0x20000>; }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x4800000>; + }; }; #include "kera-pinctrl.dtsi" #include "kera-usb.dtsi" +#include "kera-qupv3.dtsi" + +&qupv3_se13_2uart { + status = "ok"; +}; diff --git a/qcom/monaco-walt.dtsi b/qcom/monaco-walt.dtsi new file mode 100644 index 00000000..da618cdd --- /dev/null +++ b/qcom/monaco-walt.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + walt { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom,cycle-cntr { + compatible = "qcom,cycle-cntr-hw"; + reg = <0xf521000 0x1400>; + reg-names = "freq-domain0"; + }; + }; +}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 4e95d4af..3928427b 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1928,6 +1928,7 @@ #include "monaco-usb.dtsi" #include "monaco-thermal.dtsi" #include "msm-rdbg-monaco.dtsi" +#include "monaco-walt.dtsi" &gcc_camss_top_gdsc { parent-supply = <&VDD_CX_LEVEL>; diff --git a/qcom/msm-arm-smmu-sdxkova.dtsi b/qcom/msm-arm-smmu-sdxkova.dtsi index 66732ae4..c02552d5 100644 --- a/qcom/msm-arm-smmu-sdxkova.dtsi +++ b/qcom/msm-arm-smmu-sdxkova.dtsi @@ -8,7 +8,7 @@ &soc { apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x40000>; + reg = <0x0 0x15000000 0x0 0x40000>; #iommu-cells = <2>; qcom,use-3-lvl-tables; #global-interrupts = <1>; diff --git a/qcom/msm-arm-smmu-tuna.dtsi b/qcom/msm-arm-smmu-tuna.dtsi index c2367e2c..8fcc06c3 100644 --- a/qcom/msm-arm-smmu-tuna.dtsi +++ b/qcom/msm-arm-smmu-tuna.dtsi @@ -17,6 +17,13 @@ ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = + "gpu_cc_hlos1_vote_gpu_smmu"; + interrupts = , , , @@ -44,11 +51,16 @@ , ; + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x000 0x3ff 0x32B>; + gpu_qtb: gpu_qtb@3de8000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x3de8000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <49>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; }; @@ -179,11 +191,54 @@ , ; + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c00 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0800 0x0002 0x00000001>, + <0x0801 0x0000 0x00000001>, + + /* NSP:Compute */ + <0x0c01 0x0040 0x00000303>, + <0x0c02 0x0020 0x00000303>, + <0x0c03 0x0040 0x00000303>, + <0x0c04 0x0040 0x00000303>, + <0x0c05 0x0040 0x00000303>, + <0x0c06 0x0020 0x00000303>, + <0x0c07 0x0040 0x00000303>, + <0x0c08 0x0020 0x00000303>, + <0x0c09 0x0040 0x00000303>, + <0x0c0c 0x0040 0x00000303>, + <0x0c0d 0x0020 0x00000303>, + <0x0c0e 0x0040 0x00000303>, + + /* SF:Camera */ + <0x1800 0x00c0 0x00000001>, + <0x1820 0x0000 0x00000001>, + <0x1860 0x0000 0x00000103>, + <0x18a0 0x0000 0x00000103>, + <0x18e0 0x0000 0x00000103>, + <0x1980 0x0000 0x00000001>, + + /* SF:EVA */ + <0x1900 0x0020 0x00000103>, + <0x1904 0x0020 0x00000103>, + <0x1923 0x0000 0x00000103>, + + /* SF:Video */ + <0x1940 0x0000 0x00000103>, + <0x1941 0x0004 0x00000103>, + <0x1943 0x0000 0x00000103>, + <0x1944 0x0000 0x00000103>, + <0x1947 0x0000 0x00000103>; + anoc_1_qtb: anoc_1_qtb@16f2000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; reg = <0x16f2000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -192,6 +247,7 @@ reg = <0x171b000 0x1000>; qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -200,6 +256,7 @@ reg = <0x17f7000 0x1000>; qcom,stream-id-range = <0x1c00 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -208,6 +265,7 @@ reg = <0x7d3000 0x1000>; qcom,stream-id-range = <0xc00 0x400>; qcom,iova-width = <32>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -216,6 +274,7 @@ reg = <0x7b3000 0x1000>; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <32>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -224,6 +283,7 @@ reg = <0x16cd000 0x1000>; qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <32>; + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; qcom,opt-out-tbu-halting; }; @@ -233,6 +293,7 @@ reg = <0x17b7000 0x1000>; qcom,stream-id-range = <0x1800 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_VIDEO_EVA &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -241,6 +302,7 @@ reg = <0x17f6000 0x1000>; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; + interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; }; diff --git a/qcom/msm-arm-smmu-waipio-vm.dtsi b/qcom/msm-arm-smmu-waipio-vm.dtsi new file mode 100644 index 00000000..77bc069a --- /dev/null +++ b/qcom/msm-arm-smmu-waipio-vm.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x2>; + num-smrs = <0x3>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + qcom,actlr = + <0x2803 0x0400 0x00000001>, + <0x2804 0x0402 0x00000001>; + }; +}; diff --git a/qcom/parrot-reserved-memory.dtsi b/qcom/parrot-reserved-memory.dtsi index d4ab5c93..33496207 100644 --- a/qcom/parrot-reserved-memory.dtsi +++ b/qcom/parrot-reserved-memory.dtsi @@ -134,9 +134,9 @@ reg = <0x0 0xe0600000 0x0 0x400000>; }; - trust_ui_vm_mem: trust_ui_vm_region@e0b00000 { + trust_ui_vm_mem: trust_ui_vm_region@e0c00000 { no-map; - reg = <0x0 0xe0b00000 0x0 0x4af3000>; + reg = <0x0 0xe0c00000 0x0 0x49f3000>; }; trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 { diff --git a/qcom/parrot-thermal.dtsi b/qcom/parrot-thermal.dtsi index 76f426f8..42661ede 100644 --- a/qcom/parrot-thermal.dtsi +++ b/qcom/parrot-thermal.dtsi @@ -9,6 +9,12 @@ #cooling-cells = <2>; }; +&aoss_qmp { + cx_cdev: cx_cdev { + #cooling-cells = <2>; + }; +}; + &soc { tsens0: thermal-sensor@c263000 { compatible = "qcom,tsens-v2"; @@ -1129,6 +1135,13 @@ type = "passive"; }; }; + + cooling-maps { + wcss_cx_vdd_cdev { + trip = <&min_temp_0_trip>; + cooling-device = <&cx_cdev 1 1>; + }; + }; }; zeroc-1 { @@ -1148,5 +1161,12 @@ type = "passive"; }; }; + + cooling-maps { + wcss_cx_vdd_cdev { + trip = <&min_temp_1_trip>; + cooling-device = <&cx_cdev 1 1>; + }; + }; }; }; diff --git a/qcom/parrot-vm-atp.dts b/qcom/parrot-vm-atp.dts new file mode 100644 index 00000000..840a6997 --- /dev/null +++ b/qcom/parrot-vm-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SVM ATP"; + compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/parrot-vm-atp.dtsi b/qcom/parrot-vm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/parrot-vm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dts b/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dts new file mode 100644 index 00000000..29bbe8c9 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-idp-wcn3990-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN3990 VM IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dtsi b/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dtsi new file mode 100644 index 00000000..5d2ec880 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn3990-amoled-rcm.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/parrot-vm-idp-wcn3990.dts b/qcom/parrot-vm-idp-wcn3990.dts new file mode 100644 index 00000000..586b9ffc --- /dev/null +++ b/qcom/parrot-vm-idp-wcn3990.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-idp-wcn3990.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SVM IDP + WCN3990"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/parrot-vm-idp-wcn3990.dtsi b/qcom/parrot-vm-idp-wcn3990.dtsi new file mode 100644 index 00000000..5d2ec880 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn3990.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts new file mode 100644 index 00000000..8cd3d4fb --- /dev/null +++ b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-idp-wcn6750-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot WCN6750 VM IDP + AMOLED + RCM"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dtsi b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dtsi new file mode 100644 index 00000000..5d2ec880 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn6750-amoled-rcm.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/parrot-vm-idp-wcn6750-amoled.dts b/qcom/parrot-vm-idp-wcn6750-amoled.dts new file mode 100644 index 00000000..6d13dca5 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn6750-amoled.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-idp-wcn6750-amoled.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot VM WCN6750 IDP + AMOLED"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/parrot-vm-idp-wcn6750-amoled.dtsi b/qcom/parrot-vm-idp-wcn6750-amoled.dtsi new file mode 100644 index 00000000..5d2ec880 --- /dev/null +++ b/qcom/parrot-vm-idp-wcn6750-amoled.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/parrot-vm-idp.dts b/qcom/parrot-vm-idp.dts new file mode 100644 index 00000000..d50413d5 --- /dev/null +++ b/qcom/parrot-vm-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SVM IDP"; + compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/parrot-vm-idp.dtsi b/qcom/parrot-vm-idp.dtsi new file mode 100644 index 00000000..985f19ef --- /dev/null +++ b/qcom/parrot-vm-idp.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; + +&qupv3_se9_i2c { + status = "ok"; + novatek@62 { + reg = <0x62>; + novatek,trusted-touch-mode = "vm_mode"; + novatek,touch-environment = "tvm"; + novatek,trusted-touch-spi-irq = <566>; + novatek,trusted-touch-io-bases = <0xa8c000 0xa10000>; + novatek,trusted-touch-io-sizes = <0x1000 0x4000>; + novatek,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/parrot-vm-qrd-wcn6750.dts b/qcom/parrot-vm-qrd-wcn6750.dts new file mode 100644 index 00000000..e773ce4b --- /dev/null +++ b/qcom/parrot-vm-qrd-wcn6750.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-qrd-wcn6750.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SVM QRD + WCN6750"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 1>; +}; diff --git a/qcom/parrot-vm-qrd-wcn6750.dtsi b/qcom/parrot-vm-qrd-wcn6750.dtsi new file mode 100644 index 00000000..c7009e0b --- /dev/null +++ b/qcom/parrot-vm-qrd-wcn6750.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "parrot-vm-qrd.dtsi" + +&soc { +}; diff --git a/qcom/parrot-vm-qrd.dts b/qcom/parrot-vm-qrd.dts new file mode 100644 index 00000000..8681a2e8 --- /dev/null +++ b/qcom/parrot-vm-qrd.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot VM QRD"; + compatible = "qcom,parrot-qrd", "qcom,parrot", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/parrot-vm-qrd.dtsi b/qcom/parrot-vm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/parrot-vm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/parrot-vm-rumi.dts b/qcom/parrot-vm-rumi.dts new file mode 100644 index 00000000..2d049a01 --- /dev/null +++ b/qcom/parrot-vm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "parrot-vm.dtsi" +#include "parrot-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Parrot SVM RUMI"; + compatible = "qcom,parrot-rumi", "qcom,parrot", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/parrot-vm-rumi.dtsi b/qcom/parrot-vm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/parrot-vm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi new file mode 100644 index 00000000..a8f8d09a --- /dev/null +++ b/qcom/parrot-vm.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "waipio-vm.dtsi" + +/ { + qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, + <633 0x10000>, <634 0x10000>, <638 0x10000>; + interrupt-parent = <&vgic>; + + qcom,vm-config { + iomemory-ranges = <0x0 0x0a28000 0x0 0x0a28000 0x0 0x4000 0x0 + 0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1 + 0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1 + 0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1 + 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; + + gic-irq-ranges = <325 325>; /* PVM->SVM IRQ transfer */ + vdevices { + gvsock-message-queue-pair { + status = "disabled"; + }; + }; + }; +}; + +&soc { + + /delete-node/ interrupt-controller@17100000; + + qcom,spmi@c42d000 { + status = "disabled"; + }; + + vgic: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + }; + + pinctrl@f000000 { + compatible = "qcom,parrot-vm-tlmm"; + gpios = /bits/ 16 <>; + qcom,gpios-reserved = <0 1 2 3 38>; + }; + + tlmm-vm-mem-access { + tlmm-vm-gpio-list = <>; + }; + + apps-smmu@15000000 { + qcom,actlr = + /* Display and camera clients, +0 PF */ + <0x800 0x7ff 0x1>, + <0x2000 0xE0 0x1>, + <0x2100 0x60 0x1>, + /* For video clients, +3 PF */ + <0x2180 0x27 0x103>, + /* NSP clients, +15PF */ + <0x1000 0x7ff 0x303>; + }; + + /delete-node/ qup_common_iommu_group; + /delete-node/ qcom,qupv3_0_geni_se@9c0000; + /delete-node/ qcom,gpi-dma@900000; + /delete-node/ i2c@990000; + /delete-node/ spi@990000; + + qup_iommu_group: qup_common_iommu_group { + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + }; + + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x418 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,gpii-mask = <0x40>; + qcom,ev-factor = <2>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + iommus = <&apps_smmu 0x418 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + status = "ok"; + + /* TUI over I2C */ + qupv3_se9_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + +}; diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index a188b6d5..d36b3a45 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -29,7 +29,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@98c000:115200n8"; - bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on cgroup_disable=pressure"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; @@ -1439,8 +1439,8 @@ compatible = "qcom,sdhci-msm-v5"; reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>, - <0x007C8000 0x8000>, <0x007D0000 0x9000>; - reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm"; + <0x007C8000 0x18000>; + reg-names = "hc", "cqhci", "ice"; interrupts = , ; @@ -1450,6 +1450,7 @@ nvmem-cells = <&boot_config>; nvmem-cell-names = "boot_conf"; + qcom,ice-use-hwkm; bus-width = <8>; non-removable; supports-cqe; @@ -2051,12 +2052,20 @@ shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>; }; - qcom,virtio_backend@0 { - compatible = "qcom,virtio_backend"; + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { qcom,vm = <&trust_ui_vm>; qcom,label = <0x11>; }; + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + memory-region = <&trust_ui_vm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0>; + }; + qrtr-gunyah { compatible = "qcom,qrtr-gunyah"; qcom,master; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index e31044d2..19f3ffec 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -3,6 +3,7 @@ _platform_map = { "dtb_list": [ # keep sorted {"name": "sdxkova-idp-cpe.dtb"}, + {"name": "sdxkova-idp-m2.dtb"}, {"name": "sdxkova-idp-mbb.dtb"}, ], "dtbo_list": [ @@ -85,6 +86,26 @@ _platform_map = { }, ], }, + "parrot-tuivm": { + "dtb_list": [ + # keep sorted + {"name": "parrot-vm-rumi.dtb"}, + {"name": "parrot-vm-atp.dtb"}, + {"name": "parrot-vm-idp.dtb"}, + {"name": "parrot-vm-idp-wcn3990.dtb"}, + {"name": "parrot-vm-idp-wcn3990-amoled-rcm.dtb"}, + {"name": "parrot-vm-idp-wcn6750-amoled.dtb"}, + {"name": "parrot-vm-idp-wcn6750-amoled-rcm.dtb"}, + {"name": "parrot-vm-qrd.dtb"}, + {"name": "parrot-vm-qrd-wcn6750.dtb"}, + {"name": "ravelin-vm-rumi.dtb"}, + {"name": "ravelin-vm-atp.dtb"}, + {"name": "ravelin-vm-idp.dtb"}, + {"name": "ravelin-vm-idp-wcn3988.dtb"}, + {"name": "ravelin-vm-idp-wcn3950-amoled-rcm.dtb"}, + {"name": "ravelin-vm-qrd.dtb"}, + ], + }, "sun-tuivm": { "dtb_list": [ # keep sorted diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi new file mode 100644 index 00000000..bd9d9220 --- /dev/null +++ b/qcom/pm7550ba.dtsi @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm7550ba@7 { + compatible = "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550ba_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550ba_sdam_1: sdam@7000 { + compatible = "qcom,spmi-sdam"; + reg = <0x7000>; + }; + + pm7550ba_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + }; + + pm7550ba_sdam_3: sdam@7200 { + compatible = "qcom,spmi-sdam"; + reg = <0x7200>; + }; + + pm7550ba_sdam_4: sdam@7300 { + compatible = "qcom,spmi-sdam"; + reg = <0x7300>; + }; + + pm7550ba_gpios: pinctrl@8800 { + compatible = "qcom,pm7550ba-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550ba_eusb2_repeater: eusb2-repeater@fd00 { + compatible = "qcom,pmic-eusb2-repeater"; + reg = <0xfd00>; + status = "disabled"; + }; + + pm7550ba_vib: qcom,vibrator@df00 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0xdf00>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + status = "disabled"; + }; + + pm7550ba_amoled: qcom,amoled { + compatible = "qcom,amoled-regulator"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + oledb_vreg: oledb@fa00 { + reg = <0xfa00>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <8000000>; + qcom,swire-control; + }; + + ab_vreg: ab@f900 { + reg = <0xf900>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <5200000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@f800 { + reg = <0xf800>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <1400000>; + regulator-max-microvolt = <6600000>; + qcom,swire-control; + regulator-allow-set-load; + }; + }; + + pm7550ba_amoled_ecm: qcom,amoled-ecm@f900 { + compatible = "qcom,amoled-ecm"; + reg = <0xf900>; + status = "disabled"; + + nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1", + "amoled-ecm-sdam2"; + nvmem = <&pmk8550_sdam_13>, <&pmk8550_sdam_14>, + <&pmk8550_sdam_41>; + interrupt-names = "ecm-sdam0", "ecm-sdam1", + "ecm-sdam2"; + interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x98 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm7550ba_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>, + <0x7 0x47 0x1 IRQ_TYPE_NONE>, + <0x7 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&thermal_zones { + pm7550ba_temp_alarm: pm7550ba_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm7550ba_tz>; + + trips { + pm7550ba_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm7550ba_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pm7550ba_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm7550ba-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7550ba-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <9000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7550ba-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7550ba-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm7550ba-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pmr735b.dtsi b/qcom/pmr735b.dtsi new file mode 100644 index 00000000..0877abf4 --- /dev/null +++ b/qcom/pmr735b.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmr735b@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735b_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735b_gpios: pinctrl@8800 { + compatible = "qcom,pmr735b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmr735b_temp_alarm: pmr735b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmr735b_tz>; + + trips { + pmr735b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + pmr735b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pmxr2230.dtsi b/qcom/pmxr2230.dtsi new file mode 100644 index 00000000..5dcf1017 --- /dev/null +++ b/qcom/pmxr2230.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmxr2230@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmxr2230_tz: pmxr2230-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmxr2230_gpios: pinctrl@8800 { + compatible = "qcom,pmxr2230-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmxr2230_pwm_1: pwms@e800 { + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <3>; + nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; + qcom,lut-sdam-base = <0x45>; + qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 + 90 80 70 60 50 40 30 20 10 0>; + qcom,tick-duration-us = <7800>; + + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pmxr2230_pwm_2: pwms@e900 { + compatible = "qcom,pwm-lpg"; + reg = <0xe900>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + + pmxr2230_pwm_4: pwms@eb00 { + compatible = "qcom,pwm-lpg"; + reg = <0xeb00>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + + pmxr2230_rgb: qcom,leds@ef00 { + compatible = "qcom,tri-led"; + reg = <0xef00>; + + red { + label = "red"; + pwms = <&pmxr2230_pwm_1 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pmxr2230_pwm_1 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pmxr2230_pwm_1 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pmxr2230_flash: qcom,flash_led@ee00 { + compatible = "qcom,qti-pm8350c-flash-led"; + reg = <0xee00>; + interrupts = <0x1 0xee 0x0 IRQ_TYPE_EDGE_RISING>, + <0x1 0xee 0x3 IRQ_TYPE_EDGE_RISING>, + <0x1 0xee 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,thermal-derate-current = <200 500>; + status = "disabled"; + + pmxr2230_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_flash3: qcom,flash_3 { + label = "flash"; + qcom,led-name = "led:flash_3"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash3_trigger"; + qcom,id = <3>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_torch3: qcom,torch_3 { + label = "torch"; + qcom,led-name = "led:torch_3"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch3_trigger"; + qcom,id = <3>; + qcom,ires-ua = <12500>; + }; + + pmxr2230_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmxr2230_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,default-led-trigger = "switch1_trigger"; + }; + + pmxr2230_switch2: qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,default-led-trigger = "switch2_trigger"; + }; + }; + + pmxr2230_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>, + <0x1 0x47 0x1 IRQ_TYPE_NONE>, + <0x1 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + }; +}; + +&thermal_zones { + pmxr2230_temp_alarm: pmxr2230_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmxr2230_tz>; + + trips { + pmxr2230_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmxr2230_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmxr2230_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmxr2230-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmxr2230_bcl 5>; + + trips { + bcl_lvl0: bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmxr2230-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmxr2230_bcl 6>; + + trips { + bcl_lvl1: bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmxr2230-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmxr2230_bcl 7>; + + trips { + bcl_lvl2: bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/ravelin-reserved-memory.dtsi b/qcom/ravelin-reserved-memory.dtsi index 03120f6d..9fefd3db 100644 --- a/qcom/ravelin-reserved-memory.dtsi +++ b/qcom/ravelin-reserved-memory.dtsi @@ -129,9 +129,9 @@ reg = <0x0 0xe0600000 0x0 0x400000>; }; - trust_ui_vm_mem: trust_ui_vm_region@e0b00000 { + trust_ui_vm_mem: trust_ui_vm_region@e0c00000 { no-map; - reg = <0x0 0xe0b00000 0x0 0x4af3000>; + reg = <0x0 0xe0c00000 0x0 0x49f3000>; }; trust_ui_vm_qrtr: trust_ui_vm_qrtr@e55f3000 { diff --git a/qcom/ravelin-vm-atp.dts b/qcom/ravelin-vm-atp.dts new file mode 100644 index 00000000..21831a11 --- /dev/null +++ b/qcom/ravelin-vm-atp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SVM ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/qcom/ravelin-vm-atp.dtsi b/qcom/ravelin-vm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/ravelin-vm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dts b/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dts new file mode 100644 index 00000000..d9f7ccf0 --- /dev/null +++ b/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-idp-wcn3950-amoled-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin WCN3950 VM IDP + AMOLED + RCM"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dtsi new file mode 100644 index 00000000..fbdec33a --- /dev/null +++ b/qcom/ravelin-vm-idp-wcn3950-amoled-rcm.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/ravelin-vm-idp-wcn3988.dts b/qcom/ravelin-vm-idp-wcn3988.dts new file mode 100644 index 00000000..ceb8fb37 --- /dev/null +++ b/qcom/ravelin-vm-idp-wcn3988.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-idp-wcn3988.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SVM IDP + WCN3988"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/ravelin-vm-idp-wcn3988.dtsi b/qcom/ravelin-vm-idp-wcn3988.dtsi new file mode 100644 index 00000000..fbdec33a --- /dev/null +++ b/qcom/ravelin-vm-idp-wcn3988.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "ravelin-vm-idp.dtsi" + +&soc { +}; diff --git a/qcom/ravelin-vm-idp.dts b/qcom/ravelin-vm-idp.dts new file mode 100644 index 00000000..aba26eb0 --- /dev/null +++ b/qcom/ravelin-vm-idp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SVM IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/ravelin-vm-idp.dtsi b/qcom/ravelin-vm-idp.dtsi new file mode 100644 index 00000000..fd0e6de3 --- /dev/null +++ b/qcom/ravelin-vm-idp.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; + +&qupv3_se1_i2c { + status = "ok"; + focaltech@38 { + reg = <0x38>; + focaltech,display-coords = <0 0 1080 2408>; + focaltech,max-touch-number = <5>; + focaltech,ic-type = <0x8726081C>; + focaltech,reset-gpio-base = <0xF10C000>; + focaltech,intr-gpio-base = <0xF10D000>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-type = "primary"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0x984000 0x910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x4000>; + focaltech,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/ravelin-vm-qrd.dts b/qcom/ravelin-vm-qrd.dts new file mode 100644 index 00000000..5f5030ec --- /dev/null +++ b/qcom/ravelin-vm-qrd.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin VM QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/ravelin-vm-qrd.dtsi b/qcom/ravelin-vm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/ravelin-vm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/ravelin-vm-rumi.dts b/qcom/ravelin-vm-rumi.dts new file mode 100644 index 00000000..7edec701 --- /dev/null +++ b/qcom/ravelin-vm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ravelin-vm.dtsi" +#include "ravelin-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin SVM RUMI"; + compatible = "qcom,ravelin-rumi", "qcom,ravelin", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/ravelin-vm-rumi.dtsi b/qcom/ravelin-vm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/ravelin-vm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/ravelin-vm.dtsi b/qcom/ravelin-vm.dtsi new file mode 100644 index 00000000..a2fd924e --- /dev/null +++ b/qcom/ravelin-vm.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "waipio-vm.dtsi" + +/ { + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>; + interrupt-parent = <&vgic>; + + qcom,vm-config { + iomemory-ranges = <0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0 + 0x0 0x0928000 0x0 0x0928000 0x0 0x4000 0x0 + 0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1 + 0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1 + 0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1>; + gic-irq-ranges = <282 282>; /* PVM->SVM IRQ transfer */ + vdevices { + gvsock-message-queue-pair { + status = "disabled"; + }; + }; + }; +}; + +&soc { + + /delete-node/ interrupt-controller@17100000; + + qcom,spmi@c42d000 { + status = "disabled"; + }; + + vgic: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + }; + + pinctrl@f000000 { + compatible = "qcom,ravelin-vm-tlmm"; + gpios = /bits/ 16 <>; + qcom,gpios-reserved = <0 1 2 3 38>; + }; + + tlmm-vm-mem-access { + tlmm-vm-gpio-list = <>; + }; + + apps-smmu@15000000 { + qcom,actlr = + /* Display and camera clients, +0 PF */ + <0x1900 0x3F 0x1>, + <0x1800 0xFF 0x1>, + <0x800 0x7FF 0x1>, + /* For video clients, +3 PF */ + <0x1980 0x3F 0x103>; + }; + + /delete-node/ qup_common_iommu_group; + /delete-node/ qcom,qupv3_0_geni_se@9c0000; + /delete-node/ qcom,gpi-dma@900000; + /delete-node/ i2c@990000; + /delete-node/ spi@990000; + + qup_iommu_group: qup_common_iommu_group { + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + }; + + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x178 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,gpii-mask = <0x40>; + qcom,ev-factor = <2>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + iommus = <&apps_smmu 0x178 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + status = "ok"; + + /* Legacy Touch over I2C */ + qupv3_se1_i2c: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + qupv3_se1_spi: spi@984000 { + compatible = "qcom,spi-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; +}; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 5f66177f..5cfc434b 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -805,6 +805,11 @@ qcom,vmid = <3>; }; + qcom,hdcp { + compatible = "qcom,hdcp"; + qcom,use-smcinvoke = <1>; + }; + qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; qcom,msgq-names = "trusted_vm"; @@ -2453,12 +2458,20 @@ shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>; }; - qcom,virtio_backend@0 { - compatible = "qcom,virtio_backend"; + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { qcom,vm = <&trust_ui_vm>; qcom,label = <0x11>; }; + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + memory-region = <&trust_ui_vm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0>; + }; + vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; diff --git a/qcom/sdxkova-idp-m2.dts b/qcom/sdxkova-idp-m2.dts new file mode 100644 index 00000000..51d11ed7 --- /dev/null +++ b/qcom/sdxkova-idp-m2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sdxkova.dtsi" +#include "sdxkova-idp-m2.dtsi" +#include "sdxkova-reserved-memory.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXKOVA IDP M2"; + compatible = "qcom,sdxkova-idp", + "qcom,sdxkova", "qcom,idp"; + qcom,board-id = <0x4020022 0x304>; +}; diff --git a/qcom/sdxkova-idp-m2.dtsi b/qcom/sdxkova-idp-m2.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/sdxkova-idp-m2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 749406b2..2d686d77 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -6,7 +6,7 @@ #include "sdx75.dtsi" /delete-node/ &apps_smmu; #include "msm-arm-smmu-sdxkova.dtsi" -/ { +/{ qcom_tzlog: tz-log@14680720 { compatible = "qcom,tz-log"; reg = <0x14680720 0x3000>; @@ -15,21 +15,128 @@ hyplog-size-offset = <0x414>; }; -/delete-node/ reserved-memory; + /delete-node/ reserved-memory; -reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - system_cma: linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + soc: soc { + /delete-node/ rsc@17a00000; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,drv-count = <3>; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-offset = <0xd00>; + qcom,tcs-config = , + , + , + , + ; + }; + + }; + }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sdx75-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sdx75-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; + }; + + aliases: aliases { + serial0 = &uart1; }; }; +&tlmm { + gpio-reserved-ranges = <110 6>; +}; + +&qupv3_id_0 { + status = "ok"; +}; + +&uart1 { + status = "ok"; }; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index 40d81ac1..3382150e 100644 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -88,14 +88,14 @@ qcom,glinkpkt-slate-ssc-hal { qcom,glink-channels = "ssc_hal"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-sso-hal { qcom,glink-channels = "sso_hal"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-cam-hal { @@ -106,8 +106,8 @@ qcom,glinkpkt-slate-ssc-usta { qcom,glink-channels = "ssc_usta"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-location-ctrl { @@ -118,92 +118,92 @@ qcom,glinkpkt-slate-ssc-test-0 { qcom,glink-channels = "ssc_test_0"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-1 { qcom,glink-channels = "ssc_test_1"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-2 { qcom,glink-channels = "ssc_test_2"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-3 { qcom,glink-channels = "ssc_test_3"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-4 { qcom,glink-channels = "ssc_test_4"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-5 { qcom,glink-channels = "ssc_test_5"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-6 { qcom,glink-channels = "ssc_test_6"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-7 { qcom,glink-channels = "ssc_test_7"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-8 { qcom,glink-channels = "ssc_test_8"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-9 { qcom,glink-channels = "ssc_test_9"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-10 { qcom,glink-channels = "ssc_test_10"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-11 { qcom,glink-channels = "ssc_test_11"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-12 { qcom,glink-channels = "ssc_test_12"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-13 { qcom,glink-channels = "ssc_test_13"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glinkpkt-slate-ssc-test-14 { qcom,glink-channels = "ssc_test_14"; - qcom,intents = <0x2710 2 - 0x3E8 2>; + qcom,intents = <0x1388 3 + 0x3E8 7>; }; qcom,glink-ss-bt-ctrl { diff --git a/qcom/sun-atp-overlay.dts b/qcom/sun-atp-overlay.dts index e97fb466..c521d397 100644 --- a/qcom/sun-atp-overlay.dts +++ b/qcom/sun-atp-overlay.dts @@ -12,7 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun ATP"; compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, - <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x10021 0>; }; diff --git a/qcom/sun-oemvm.dtsi b/qcom/sun-oemvm.dtsi index 0f8177f3..7bee5578 100644 --- a/qcom/sun-oemvm.dtsi +++ b/qcom/sun-oemvm.dtsi @@ -76,7 +76,7 @@ vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0"; qcom,sensitive; - vm-attrs = "crash-fatal", "context-dump"; + vm-attrs = "crash-fatal", "context-dump", "crash-restart"; memory { #address-cells = <0x2>; diff --git a/qcom/sun-pcie.dtsi b/qcom/sun-pcie.dtsi index e2f83bcc..c46df45c 100644 --- a/qcom/sun-pcie.dtsi +++ b/qcom/sun-pcie.dtsi @@ -141,12 +141,12 @@ 0x1374 0x09 0x0 0x1378 0x49 0x0 0x137c 0x1b 0x0 - 0x1380 0x9c 0x0 + 0x1380 0x8f 0x0 0x1370 0xd1 0x0 0x1388 0x09 0x0 0x138c 0x49 0x0 0x1390 0x1b 0x0 - 0x1394 0x9c 0x0 + 0x1394 0x8f 0x0 0x1384 0xd1 0x0 0x12c4 0x3e 0x0 0x12c8 0x1e 0x0 @@ -178,12 +178,12 @@ 0x1b74 0x09 0x0 0x1b78 0x49 0x0 0x1b7c 0x1b 0x0 - 0x1b80 0x9c 0x0 + 0x1b80 0x8f 0x0 0x1b70 0xd1 0x0 0x1b88 0x09 0x0 0x1b8c 0x49 0x0 0x1b90 0x1b 0x0 - 0x1b94 0x9c 0x0 + 0x1b94 0x8f 0x0 0x1b84 0xd1 0x0 0x1ac4 0x3e 0x0 0x1ac8 0x1e 0x0 diff --git a/qcom/sun-rcm-kiwi-overlay.dts b/qcom/sun-rcm-kiwi-overlay.dts index fe46bac7..ba95281f 100644 --- a/qcom/sun-rcm-kiwi-overlay.dts +++ b/qcom/sun-rcm-kiwi-overlay.dts @@ -12,7 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, - <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x40015 0>; }; diff --git a/qcom/sun-rcm-kiwi-v8-overlay.dts b/qcom/sun-rcm-kiwi-v8-overlay.dts index bfc48fba..367d553a 100644 --- a/qcom/sun-rcm-kiwi-v8-overlay.dts +++ b/qcom/sun-rcm-kiwi-v8-overlay.dts @@ -12,7 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, - <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x20015 0>; }; diff --git a/qcom/sun-rcm-overlay.dts b/qcom/sun-rcm-overlay.dts index 19d1d174..b5d3a092 100644 --- a/qcom/sun-rcm-overlay.dts +++ b/qcom/sun-rcm-overlay.dts @@ -11,7 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, - <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x15 0>; }; diff --git a/qcom/sun-rcm-v8-overlay.dts b/qcom/sun-rcm-v8-overlay.dts index e8465ce0..a109fbfc 100644 --- a/qcom/sun-rcm-v8-overlay.dts +++ b/qcom/sun-rcm-v8-overlay.dts @@ -12,7 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, - <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x30015 0>; }; diff --git a/qcom/sun-v2.dtsi b/qcom/sun-v2.dtsi index 9ca06a7f..ee577831 100644 --- a/qcom/sun-v2.dtsi +++ b/qcom/sun-v2.dtsi @@ -14,6 +14,10 @@ compatible = "qcom,sun-videocc-v2", "syscon"; }; +&cambistmclkcc { + compatible = "qcom,sun-cambistmclkcc-v2", "syscon"; +}; + &tsens1 { #qcom,sensors = <7>; }; diff --git a/qcom/sun-vm-dma-heaps.dtsi b/qcom/sun-vm-dma-heaps.dtsi index 575b2573..5fda6434 100644 --- a/qcom/sun-vm-dma-heaps.dtsi +++ b/qcom/sun-vm-dma-heaps.dtsi @@ -38,5 +38,11 @@ qcom,dma-heap-type = ; qcom,dynamic-heap; }; + + qcom,tui_test { + qcom,dma-heap-name = "qcom,tui_test"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; }; }; diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index f2f25f6e..494c5e9c 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -102,7 +102,7 @@ vm-guid = "598085da-c516-5b25-a9c1-927a02819770"; qcom,sensitive; - vm-attrs = "crash-fatal", "context-dump"; + vm-attrs = "crash-fatal", "context-dump", "crash-restart"; iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0 diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index be6624b9..a3d28847 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -926,11 +926,11 @@ scid_heuristics { compatible = "qcom,scid-heuristics"; - qcom,heuristics_scid = <32>; + qcom,heuristics-scid = <32>; /* Need to update different value for V2 device */ - freq,threshold_idx = <11>, <10>; - freq,threshold_residency = <5000>, <5000>; - qcom,scid_heuristics_enabled; + qcom,freq-threshold-idx = <11>, <10>; + qcom,frequency-threshold-residency = <5000>, <5000>; + qcom,scid-heuristics-enabled; }; }; @@ -3276,6 +3276,58 @@ }; }; + qcom-mpam-msc { + compatible = "qcom,mpam-msc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom-slc-mpam@17b6f800 { + compatible = "qcom,slc-mpam"; + reg = <0x17b6f800 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <2>; + qcom,msc-name = "slc"; + qcom,dev-index = <0>; + qcom,num-read-miss-cfg = <2>; + qcom,num-cap-cfg = <5>; + qcom,slc-clients = "APPS_CLIENT", "GPU_CLIENT", + "NSP_CLIENT"; + }; + }; + + qcom_slc_mpam: qcom,slc_mpam { + compatible = "qcom,mpam-slc"; + qcom,msc-name = "slc"; + + apps { + qcom,client-id = <0>; + qcom,client-name = "apps"; + + part-id0 { + qcom,part-id = <0>; + }; + + part-id1 { + qcom,part-id = <1>; + }; + + part-id2 { + qcom,part-id = <2>; + }; + }; + + gpu { + qcom,client-id = <1>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <2>; + qcom,client-name = "nsp"; + }; + }; + llcc_pmu: llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; @@ -3594,8 +3646,13 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; + interconnects = <&aggre2_noc MASTER_SOCCP_AGGR_NOC &mc_virt SLAVE_EBI1>, + <&cnoc_main MASTER_CNOC_CFG &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "rproc_cnoc"; + memory-region = <&soccp_mem 0>; - soccp-config = <&tcsr 0x1a000>; + soccp-tcsr = <&tcsr 0x1a000>; + soccp-spare = <0xda0024>; /* Inputs from SOCCP */ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, @@ -3603,16 +3660,14 @@ <&soccp_smp2p_in 1 0>, <&soccp_smp2p_in 3 0>, <&soccp_smp2p_in 2 0>, - <&soccp_smp2p_in 9 0>, - <&soccp_smp2p_in 10 0>; + <&soccp_smp2p_in 9 0>; interrupt-names = "wdog", "fatal", "ready", "stop-ack", "handover", - "pong", - "wake-ack"; + "pong"; /* Outputs to soccp */ qcom,smem-states = <&soccp_smp2p_out 0>, <&soccp_smp2p_out 10>, <&soccp_smp2p_out 9>; @@ -3654,12 +3709,7 @@ gunyah_hyp_mem: gunyah_hyp_region@80000000 { no-map; - reg = <0x0 0x80000000 0x0 0xe00000>; - }; - - cpusys_vm_mem: cpusys_vm_region@80e00000 { - no-map; - reg = <0x0 0x80e00000 0x0 0x400000>; + reg = <0x0 0x80000000 0x0 0x1200000>; }; cpucp_pdp_mem: cpucp_pdp_region@81200000 { diff --git a/qcom/tuna-dma-heaps.dtsi b/qcom/tuna-dma-heaps.dtsi index 6472b080..ac87057a 100644 --- a/qcom/tuna-dma-heaps.dtsi +++ b/qcom/tuna-dma-heaps.dtsi @@ -9,5 +9,11 @@ qcom,dma-heaps { compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,cma-secure-cdsp"; + qcom,dma-heap-type = ; + memory-region = <&cdsp_secure_heap_cma>; + }; }; }; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi new file mode 100644 index 00000000..67e544ad --- /dev/null +++ b/qcom/tuna-pm7550ba.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pm7550ba.dtsi" +#include + +/ { + qcom,pmic-id-size = <8>; + qcom,pmic-id = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x4C>; +}; + +&spmi0_debug_bus { + qcom,pm7550ba-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + +&pmic_glink_debug { + /* Primary SPMI bus */ + glink_debug_spmi0: spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm7550ba-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + qcom,can-sleep; + }; + }; +}; + +&pm7550ba_vib { + status = "okay"; +}; + +&pm7550ba_amoled { + status = "okay"; +}; + diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi new file mode 100644 index 00000000..e6ad7b1b --- /dev/null +++ b/qcom/tuna-pmic-overlay.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "pmk8550.dtsi" +#include "pmxr2230.dtsi" +#include "pm8550vs.dtsi" +#include "pmr735b.dtsi" +#include "pm8550ve.dtsi" +#include "pmd802x.dtsi" +#include "pm8010.dtsi" + +&pm8550vs_g { + status = "ok"; +}; + +&pm8550vs_g_temp_alarm { + status = "ok"; +}; + +&pm8550vs_d { + status = "ok"; +}; + +&pm8550vs_d_temp_alarm { + status = "ok"; +}; + +&pm8550ve_f { + status = "ok"; +}; + +&pm8550ve_f_temp_alarm { + status = "ok"; +}; + +&pmxr2230_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pmxr2230_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pmxr2230_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pmxr2230_flash { + status = "ok"; +}; + +&pmk8550_gpios { + pinctrl-0 = <&alt_sleep_clk_default>; + pinctrl-names = "default"; + + alt_sleep_clk { + alt_sleep_clk_default: alt_sleep_clk_default { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&pmxr2230_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + + sys_therm_6_gpio7 { + sys_therm_6_gpio7_default: sys_therm_6_gpio7_default { + pins = "gpio7"; + bias-high-impedance; + }; + }; +}; + +&soc { + gpio_key { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + vol_up { + label = "volume_up"; + gpios = <&pmxr2230_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&thermal_zones { + sys-therm-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM4_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sys-therm-6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX3_GPIO7_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pmk8550_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&sys_therm_6_gpio7_default>; + + /delete-node/ pm8550_offset_ref; + /delete-node/ pm8550_vref_1p25; + /delete-node/ pm8550_die_temp; + /delete-node/ pm8550_vph_pwr; + + /* PMXR2230 Channel nodes */ + pmxr2230_offset_ref { + reg = ; + label = "pmxr2230_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + pmxr2230_vref_1p25 { + reg = ; + label = "pmxr2230_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmxr2230_die_temp { + reg = ; + label = "pmxr2230_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmxr2230_vph_pwr { + reg = ; + label = "pmxr2230_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pmk8550_sys_therm_0 { + reg = ; + label = "pmk8550_sys_therm_0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_1 { + reg = ; + label = "pmxr2230_sys_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_2 { + reg = ; + label = "pmxr2230_sys_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_3 { + reg = ; + label = "pmxr2230_sys_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_4 { + reg = ; + label = "pmxr2230_sys_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_5 { + reg = ; + label = "pmxr2230_sys_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pmxr2230_sys_therm_6 { + reg = ; + label = "pmxr2230_sys_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550vs_d_die_temp { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8550vs_g_die_temp { + reg = ; + label = "pm8550vs_j_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8550ve_f_die_temp { + reg = ; + label = "pm8550ve_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + +}; + +&pm8550vs_g_tz { + io-channels = <&pmk8550_vadc PM8550VX_ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550vs_d_tz { + io-channels = <&pmk8550_vadc PM8550VX_ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_f_tz { + io-channels = <&pmk8550_vadc PM8550VX_ADC5_GEN3_DIE_TEMP(5)>; + io-channel-names = "thermal"; +}; diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index c72f91ac..e6ac068f 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -130,3 +130,47 @@ &qupv3_se7_2uart { qcom,rumi_platform; }; + +&GOLD_OFF_CL0 { + status = "disabled"; +}; + +&GOLD_OFF_CL1 { + status = "disabled"; +}; + +&GOLD_OFF_CL2 { + status = "disabled"; +}; + +&GOLD_RAIL_OFF_CL0 { + status = "disabled"; +}; + +&GOLD_RAIL_OFF_CL1 { + status = "disabled"; +}; + +&GOLD_RAIL_OFF_CL2 { + status = "disabled"; +}; + +&GOLD_PLUS_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_RAIL_OFF { + status = "disabled"; +}; + +&CLUSTER_PWR_DN { + status = "disabled"; +}; + +&CX_RET { + status = "disabled"; +}; + +&APSS_OFF { + status = "disabled"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 04a31470..a26e7263 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -59,7 +60,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_0>; L2_0: l2-cache { @@ -78,7 +82,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_1>; L2_1: l2-cache { @@ -93,7 +100,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_2>; L2_2: l2-cache { @@ -107,7 +117,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_3>; L2_3: l2-cache { @@ -121,7 +134,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_4>; L2_4: l2-cache { @@ -135,7 +151,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_5>; L2_5: l2-cache { @@ -149,7 +168,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_6>; L2_6: l2-cache { @@ -163,7 +185,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; - enable-method = "spin-table"; /* TODO: Update to psci */ + enable-method = "psci"; + cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_7>; L2_7: l2-cache { @@ -216,6 +241,117 @@ }; }; + idle-states { + entry-method = "psci"; + + GOLD_OFF_CL0: gold-cluster0-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF_CL0: gold-cluster0-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF_CL1: gold-cluster1-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF_CL1: gold-cluster1-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF_CL2: gold-cluster2-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF_CL2: gold-cluster2-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_PLUS_OFF: gold-plus-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <450>; + exit-latency-us = <1200>; + min-residency-us = <6230>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41001344>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + arm,psci-suspend-param = <0x4100b344>; + }; + }; + soc: soc { }; }; @@ -245,6 +381,56 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -335,6 +521,7 @@ interrupts = , , ; + power-domains = <&CLUSTER_PD>; apps_rsc_drv2: drv@2 { qcom,drv-id = <2>; @@ -354,6 +541,16 @@ }; }; + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + cam_rsc: rsc@adc8000 { label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; @@ -700,6 +897,12 @@ interrupt-names = "smp2p-sleepstate-in"; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -1015,6 +1218,13 @@ qcom,skip-qos; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x400000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + ufsphy_mem: ufsphy_mem@1d80000 { reg = <0x1d80000 0x2000>; reg-names = "phy_mem"; @@ -1099,6 +1309,202 @@ status = "disabled"; }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi1_bus: qcom,spmi@c432000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc432000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4d0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <1>; + depends-on-supply = <&spmi0_bus>; + status = "disabled"; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + pmk8550@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmxr2230@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmd802x@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550ve@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmr735d@a { + compatible = "qcom,spmi-pmic"; + reg = <10 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@d { + compatible = "qcom,spmi-pmic"; + reg = <13 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + }; + + thermal_zones: thermal-zones { + }; + + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + }; + + pmic_glink_adc: qcom,glink-adc { + compatible = "qcom,glink-adc"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; }; #include "tuna-gdsc.dtsi" @@ -1227,6 +1633,22 @@ no-map; reg = <0x0 0x81c60000 0x0 0x20000>; }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x4800000>; + }; }; #include "tuna-pinctrl.dtsi" @@ -1234,6 +1656,7 @@ #include "tuna-usb.dtsi" #include "tuna-qupv3.dtsi" #include "msm-rdbg.dtsi" +#include "tuna-pmic-overlay.dtsi" &qupv3_se7_2uart { status = "ok"; diff --git a/qcom/waipio-vm-dma-heaps.dtsi b/qcom/waipio-vm-dma-heaps.dtsi new file mode 100644 index 00000000..34c6196c --- /dev/null +++ b/qcom/waipio-vm-dma-heaps.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,tui { + qcom,dma-heap-name = "qcom,tui"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + }; +}; diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi new file mode 100644 index 00000000..7e9220d5 --- /dev/null +++ b/qcom/waipio-vm.dtsi @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <457 0x10000>, <482 0x10000>; + interrupt-parent = <&vgic>; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,vmid = <45>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable root=/dev/ram rw init=/init"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DWN: d4 { /* C4+D4 */ + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + arm,psci-suspend-param = <0x40000044>; + local-timer-stop; + }; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <3>; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + qcom,qtee-config-info = "p=7C,8F,97,159,199,7F1;"; + qcom,secdomain-ids = <45>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/trusted-ui"; + vm-guid = "3f4d154a-92d3-54d0-9241-08e34c8bc670"; + qcom,sensitive; + + iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0 + 0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1 + 0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1 + 0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1 + 0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1 + 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; + + gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */ + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + base-address = <0x0 0xe0c00000>; + size-min = <0x0 0x7a00000>; /* 122 MB */ + }; + + segments { + ramdisk = <2>; /* 8MB */ + }; + + vcpus { + config = "/cpus"; + affinity = "static"; + affinity-map = <0x5 0x6>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x11>; + #address-cells = <0x2>; + base = <0x0 0xFFEFC000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x12>; + #address-cells = <0x2>; + base = <0x0 0xFFF00000>; + }; + }; + + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + + display-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/display-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000002>; + }; + + gvsock-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/gvsock-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer = "vm-name:qcom,oemvm"; + qcom,label = <0x0000003>; + }; + + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x3>; + allocate-base; + }; + }; + + gpiomem0 { + vdevice-type = "iomem"; + patch = "/soc/tlmm-vm-mem-access"; + push-compatible = "qcom,tlmm-vm-mem-access"; + peer-default; + memory { + qcom,label = <0x8>; + qcom,mem-info-tag = <0x2>; + allocate-base; + }; + }; + + test-dbl { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl"; + qcom,label = <0x4>; + peer-default; + }; + + test-dbl-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-source"; + qcom,label = <0x4>; + peer-default; + }; + }; + }; + + firmware: firmware { + scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + spmi_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + vm_tlmm_irq: vm-tlmm-irq@0 { + compatible = "qcom,tlmm-vm-irq"; + reg = <0x0 0x0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlmm: pinctrl@f000000 { + reg = <0x0F000000 0x1000000>; + interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* Valid pins */ + gpios = /bits/ 16 <64 65 66 67 0 4 86 87 16 17 18 19 20 21>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x100000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + /* + * QUPv3 Instances + * North 4 : SE 4 + */ + qup_iommu_group: qup_common_iommu_group { + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + }; + + /* GPI */ + gpi_dma0: qcom,gpi-dma@900000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x900000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x5b8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,gpii-mask = <0x80>; + qcom,ev-factor = <2>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_0 wrapper instance: North QUP */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + iommus = <&apps_smmu 0x5b8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + status = "ok"; + + /* I2C SE */ + qupv3_se4_i2c: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + qupv3_se4_spi: spi@990000 { + compatible = "qcom,spi-geni"; + reg = <0x990000 0x4000>; + reg-names = "se_phys"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <512>; + qcom,support-hypervisor; + }; + + qcom,test-dbl { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; +}; + +#include "waipio-vm-dma-heaps.dtsi" +#include "msm-arm-smmu-waipio-vm.dtsi"