From b328de5242e49bf75cfba4124438247578b6fa42 Mon Sep 17 00:00:00 2001
From: Chris Lew <quic_clew@quicinc.com>
Date: Mon, 10 Jul 2023 16:01:14 -0700
Subject: [PATCH] ARM: dts: msm: Add AOSS and TME QMP nodes for sun

Add the nodes to describe the QMP devices to communicate with AOSS and
TME.

Change-Id: Iaac6b401e3554ce696a9faf5abaeb16717ff0907
Signed-off-by: Chris Lew <quic_clew@quicinc.com>
---
 qcom/sun.dtsi | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index cb39047f..035b7837 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -14,8 +14,10 @@
 #include <dt-bindings/clock/qcom,videocc-sun.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interconnect/qcom,sun.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Sun";
@@ -209,6 +211,38 @@
 		interrupt-controller;
 	};
 
+	aoss_qmp: power-controller@c300000 {
+		compatible = "qcom,aoss-qmp";
+		reg = <0xc300000 0x400>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_AOP
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+		#power-domain-cells = <1>;
+		#clock-cells = <0>;
+	};
+
+	qmp_tme: qcom,qmp-tme {
+		compatible = "qcom,qmp-mbox";
+		qcom,remote-pid = <14>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
+			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+		mbox-names = "tme_qmp";
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_TME
+			      IPCC_MPROC_SIGNAL_GLINK_QMP
+			      IRQ_TYPE_EDGE_RISING>;
+
+		label = "tme";
+		qcom,early-boot;
+		priority = <0>;
+		mbox-desc-offset = <0x0>;
+		#mbox-cells = <1>;
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,sun-tlmm";
 		reg = <0xf000000 0x1000000>;