ARM: dts: msm: Add support for Tuna7 GPU
Add initial support for Tuna7 GPU in the devicetree. Change-Id: I66ac7382ce0dfc10291a2318e0da3d9880c24790 Signed-off-by: SIVA MULLATI <quic_smullati@quicinc.com>
This commit is contained in:
SIVA MULLATI
committed by
Gayathri Veeragandam
Gayathri Veeragandam
parent
1f4df4368b
commit
af0e7a0660
3
Kbuild
3
Kbuild
@@ -9,7 +9,8 @@ dtbo-y += gpu/sun-gpu.dtbo \
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endif
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ifeq ($(CONFIG_ARCH_TUNA), y)
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dtbo-y += gpu/tuna-gpu.dtbo
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dtbo-y += gpu/tuna-gpu.dtbo \
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gpu/tuna7-gpu.dtbo
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endif
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always-y := $(dtb-y) $(dtbo-y)
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@@ -5,14 +5,23 @@
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&msm_gpu {
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/* Power levels */
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qcom,initial-pwrlevel = <8>;
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qcom,gpu-pwrlevels {
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compatible="qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel-bins {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels-bins";
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/*
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* The bins need to match based on speed bin first and then SKU.
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* Keep pwrlevel bins sorted in ascending order of the fmax of the bins.
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*/
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qcom,gpu-pwrlevels-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <8>;
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qcom,speed-bin = <0>;
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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@@ -112,4 +121,219 @@
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qcom,bus-max = <3>;
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};
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};
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qcom,gpu-pwrlevels-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <8>;
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qcom,speed-bin = <0xd8>;
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1025000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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};
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/* Turbo */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <937000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <10>;
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};
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/* Nom_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <873000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* Nom */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <763000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <688000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <644000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <510000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <362000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <264000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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};
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qcom,gpu-pwrlevels-2 {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <8>;
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qcom,speed-bin = <0xf2>;
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1050000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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};
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/* Turbo */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <937000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <10>;
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};
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/* Nom_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <873000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* Nom */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <763000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq = <8>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <688000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <644000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <4>;
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qcom,bus-max = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <510000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <362000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq = <3>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <264000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq = <1>;
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qcom,bus-min = <1>;
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qcom,bus-max = <3>;
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};
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};
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};
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};
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@@ -62,6 +62,9 @@
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<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
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<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L2 index=11 */
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nvmem-cells = <&gpu_speed_bin>;
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nvmem-cell-names = "speed_bin";
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zap-shader {
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memory-region = <&gpu_microcode_mem>;
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};
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30
gpu/tuna7-gpu.dts
Normal file
30
gpu/tuna7-gpu.dts
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@@ -0,0 +1,30 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,gcc-tuna.h>
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#include <dt-bindings/clock/qcom,gpucc-tuna.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,tuna.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include "tuna-gpu.dtsi"
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#include "tuna-gpu-pwrlevels.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. tuna7 SoC";
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compatible = "qcom,tuna";
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qcom,msm-id = <0x2a9 0x10000>;
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qcom,board-id = <0 0>;
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};
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&msm_gpu {
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/delete-property/qcom,gpu-model;
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qcom,gpu-model = "Adreno822";
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};
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10
gpu/tuna7-gpu.dtsi
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10
gpu/tuna7-gpu.dtsi
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@@ -0,0 +1,10 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "tuna-gpu.dtsi"
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&msm_gpu {
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qcom,gpu-model = "Adreno822";
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};
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