From b5604a5ff71b24816dff899dcc2e6648887e3693 Mon Sep 17 00:00:00 2001
From: Kunal Singh Ranawat <quic_kranawat@quicinc.com>
Date: Thu, 13 Feb 2025 18:27:16 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add tlmm pinctrl support for SM6150

Add support for TLMM pinctrl on SM6150 platform.

Change-Id: I45dfd3d84900ed4b24ecda47462c2c5178bbb02f
Signed-off-by: Kunal Singh Ranawat <quic_kranawat@quicinc.com>
---
 qcom/qcs610-opk.dtsi     |  4 ++++
 qcom/sm6150-pinctrl.dtsi |  6 ++++++
 qcom/sm6150.dtsi         | 26 ++++++++++++++++++++++++++
 3 files changed, 36 insertions(+)
 create mode 100644 qcom/sm6150-pinctrl.dtsi

diff --git a/qcom/qcs610-opk.dtsi b/qcom/qcs610-opk.dtsi
index 3fda344a..735b5765 100644
--- a/qcom/qcs610-opk.dtsi
+++ b/qcom/qcs610-opk.dtsi
@@ -12,3 +12,7 @@
 	compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
 	qcom,board-id = <32 0>;
 };
+
+&tlmm {
+	qcom,gpios-reserved = <6 7 8 9>;
+};
diff --git a/qcom/sm6150-pinctrl.dtsi b/qcom/sm6150-pinctrl.dtsi
new file mode 100644
index 00000000..f4da9acb
--- /dev/null
+++ b/qcom/sm6150-pinctrl.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {};
diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 72b62dd6..5be3450d 100644
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -566,6 +566,32 @@
 					"l3-scu-errirq",
 					"l3-scu-faultirq";
 	};
+
+	tlmm: pinctrl@03000000 {
+		compatible = "qcom,sm6150-pinctrl";
+		reg = <0x03000000 0xdc2000>, <0x17c000f0 0x50>;
+		reg-names = "pinctrl", "spi_cfg";
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		qcom,gpios-reserved = <0 1 2 3 6 7 8 9>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
+	};
 };
 
 #include "sm6150-regulator.dtsi"
+#include "sm6150-pinctrl.dtsi"
+
+&tlmm {
+	status = "okay";
+};

From 2072106de12854db48955c054fd95c42eb8e639c Mon Sep 17 00:00:00 2001
From: Asit Shah <quic_asitshah@quicinc.com>
Date: Wed, 5 Mar 2025 20:27:45 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add smem and syscon support for SM6150

Added smem, syscon and dependent nodes for SM6150.

Change-Id: Icb9485e46c8720919310bc0e2560bd51b23f5dec
Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
---
 qcom/sm6150.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 5be3450d..a8482041 100644
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -587,6 +587,28 @@
 		#interrupt-cells = <2>;
 		wakeup-parent = <&pdc>;
 	};
+
+	apcs: syscon@17c0000c {
+		compatible = "syscon";
+		reg = <0x17c0000c 0x4>;
+	};
+
+	tcsr_mutex_block: syscon@1f40000 {
+		compatible = "syscon";
+		reg = <0x1f40000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock@1f40000 {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem@8600000 {
+		compatible = "qcom,smem";
+		memory-region = <&smem_region>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
 };
 
 #include "sm6150-regulator.dtsi"