From d5c176fe3b0cd6b8de93d67fbe01a740c7b059ca Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Sun, 29 Dec 2024 01:10:07 -0800 Subject: [PATCH] ARM: dts: msm: Fake UFS Ref clock to run on HS mode Change-Id: I0045b2df13f1d6e6bcf0e4ee5c5553a7c0560807 Signed-off-by: Vishvanath Singh --- qcom/kera_ufs2.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi index 320ed23f..7ebce858 100644 --- a/qcom/kera_ufs2.dtsi +++ b/qcom/kera_ufs2.dtsi @@ -57,5 +57,39 @@ qcom,vccq2-parent-supply = <&S1B>; qcom,vccq2-parent-max-microamp = <210000>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "dev_ref_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "ok"; };