From e9b9d27ee3e2221fc6743736391f2dbf3c435d2a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 18 May 2023 18:19:01 +0530 Subject: [PATCH] ARM: dts: msm: Add snapshot of pineapple device tree Add snapshot of pineapple device tree files as of devicetree/qcom-6.1 commit 8bc1219b2b23 ("Merge "ARM: dts: msm: update memlat tables for pineapple""). Change-Id: If62ee45b1f3e7e8a5744f25b8c67a9768950c960 Signed-off-by: Mukesh Ojha --- qcom/Makefile | 23 + qcom/ipcc-test.dtsi | 36 + qcom/msm-arm-smmu-pineapple.dtsi | 414 +++ qcom/msm-rdbg.dtsi | 31 + qcom/pineapple-atp-overlay.dts | 16 + qcom/pineapple-atp.dtsi | 6 + qcom/pineapple-cdp-nfc-overlay.dts | 16 + qcom/pineapple-cdp-nfc.dtsi | 6 + qcom/pineapple-cdp-overlay.dts | 16 + qcom/pineapple-cdp.dtsi | 293 ++ qcom/pineapple-coresight.dtsi | 4896 ++++++++++++++++++++++++++ qcom/pineapple-debug.dtsi | 4918 +++++++++++++++++++++++++++ qcom/pineapple-dma-heaps.dtsi | 58 + qcom/pineapple-gdsc.dtsi | 315 ++ qcom/pineapple-mtp-nfc-overlay.dts | 16 + qcom/pineapple-mtp-nfc.dtsi | 6 + qcom/pineapple-mtp-overlay.dts | 16 + qcom/pineapple-mtp.dtsi | 320 ++ qcom/pineapple-pcie.dtsi | 626 ++++ qcom/pineapple-pinctrl.dtsi | 3494 +++++++++++++++++++ qcom/pineapple-pmic-overlay.dtsi | 409 +++ qcom/pineapple-qrd-overlay.dts | 16 + qcom/pineapple-qrd-sku2-overlay.dts | 16 + qcom/pineapple-qrd.dtsi | 498 +++ qcom/pineapple-qupv3.dtsi | 1188 +++++++ qcom/pineapple-rcm-overlay.dts | 16 + qcom/pineapple-rcm.dtsi | 37 + qcom/pineapple-regulators.dtsi | 1378 ++++++++ qcom/pineapple-rumi-overlay.dts | 16 + qcom/pineapple-rumi.dtsi | 217 ++ qcom/pineapple-thermal-modem.dtsi | 677 ++++ qcom/pineapple-thermal-overlay.dtsi | 311 ++ qcom/pineapple-thermal.dtsi | 1976 +++++++++++ qcom/pineapple-usb.dtsi | 331 ++ qcom/pineapple-v2.dts | 14 + qcom/pineapple-v2.dtsi | 163 + qcom/pineapple.dts | 14 + qcom/pineapple.dtsi | 3645 ++++++++++++++++++++ qcom/pineapplep-v2.dts | 9 + qcom/pineapplep-v2.dtsi | 7 + qcom/pineapplep.dts | 14 + qcom/pineapplep.dtsi | 12 + qcom/platform_map.bzl | 27 + qcom/pm8010.dtsi | 98 + qcom/pm8550.dtsi | 306 ++ qcom/pm8550b.dtsi | 475 +++ qcom/pm8550ve.dtsi | 66 + qcom/pm8550vs.dtsi | 216 ++ qcom/pmk8550.dtsi | 237 ++ qcom/pmr735d.dtsi | 66 + 50 files changed, 27977 insertions(+) create mode 100644 qcom/ipcc-test.dtsi create mode 100644 qcom/msm-arm-smmu-pineapple.dtsi create mode 100644 qcom/msm-rdbg.dtsi create mode 100644 qcom/pineapple-atp-overlay.dts create mode 100644 qcom/pineapple-atp.dtsi create mode 100644 qcom/pineapple-cdp-nfc-overlay.dts create mode 100644 qcom/pineapple-cdp-nfc.dtsi create mode 100644 qcom/pineapple-cdp-overlay.dts create mode 100644 qcom/pineapple-cdp.dtsi create mode 100644 qcom/pineapple-coresight.dtsi create mode 100644 qcom/pineapple-debug.dtsi create mode 100644 qcom/pineapple-dma-heaps.dtsi create mode 100644 qcom/pineapple-gdsc.dtsi create mode 100644 qcom/pineapple-mtp-nfc-overlay.dts create mode 100644 qcom/pineapple-mtp-nfc.dtsi create mode 100644 qcom/pineapple-mtp-overlay.dts create mode 100644 qcom/pineapple-mtp.dtsi create mode 100644 qcom/pineapple-pcie.dtsi create mode 100644 qcom/pineapple-pinctrl.dtsi create mode 100644 qcom/pineapple-pmic-overlay.dtsi create mode 100644 qcom/pineapple-qrd-overlay.dts create mode 100644 qcom/pineapple-qrd-sku2-overlay.dts create mode 100644 qcom/pineapple-qrd.dtsi create mode 100644 qcom/pineapple-qupv3.dtsi create mode 100644 qcom/pineapple-rcm-overlay.dts create mode 100644 qcom/pineapple-rcm.dtsi create mode 100644 qcom/pineapple-regulators.dtsi create mode 100644 qcom/pineapple-rumi-overlay.dts create mode 100644 qcom/pineapple-rumi.dtsi create mode 100644 qcom/pineapple-thermal-modem.dtsi create mode 100644 qcom/pineapple-thermal-overlay.dtsi create mode 100644 qcom/pineapple-thermal.dtsi create mode 100644 qcom/pineapple-usb.dtsi create mode 100644 qcom/pineapple-v2.dts create mode 100644 qcom/pineapple-v2.dtsi create mode 100644 qcom/pineapple.dts create mode 100644 qcom/pineapple.dtsi create mode 100644 qcom/pineapplep-v2.dts create mode 100644 qcom/pineapplep-v2.dtsi create mode 100644 qcom/pineapplep.dts create mode 100644 qcom/pineapplep.dtsi create mode 100644 qcom/pm8010.dtsi create mode 100644 qcom/pm8550.dtsi create mode 100644 qcom/pm8550b.dtsi create mode 100644 qcom/pm8550ve.dtsi create mode 100644 qcom/pm8550vs.dtsi create mode 100644 qcom/pmk8550.dtsi create mode 100644 qcom/pmr735d.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index d1608b56..4d8219fb 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -30,6 +30,29 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \ $(call add-overlays, $(SUN_BOARDS) $(APQ_SUN_BOARDS),$(SUN_APQ_BASE_DTB)) sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB) dtb-y += $(sun-dtb-y) + +PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb +PINEAPPLE_APQ_BASE_DTB += pineapplep.dtb pineapplep-v2.dtb + +PINEAPPLE_BOARDS += \ + pineapple-mtp-overlay.dtbo \ + pineapple-mtp-nfc-overlay.dtbo \ + pineapple-cdp-overlay.dtbo \ + pineapple-cdp-nfc-overlay.dtbo \ + pineapple-qrd-overlay.dtbo \ + pineapple-qrd-sku2-overlay.dtbo \ + pineapple-rcm-overlay.dtbo \ + pineapple-atp-overlay.dtbo + +NOAPQ_PINEAPPLE_BOARDS += \ + pineapple-rumi-overlay.dtbo + +pineapple-dtb-$(CONFIG_ARCH_PINEAPPLE) += \ + $(call add-overlays, $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS),$(PINEAPPLE_BASE_DTB))\ + $(call add-overlays, $(PINEAPPLE_BOARDS) $(APQ_PINEAPPLE_BOARDS),$(PINEAPPLE_APQ_BASE_DTB)) +pineapple-overlays-dtb-$(CONFIG_ARCH_PINEAPPLE) += $(PINEAPPLE_BOARDS) $(NOAPQ_PINEAPPLE_BOARDS) $(PINEAPPLE_BASE_DTB) $(PINEAPPLE_APQ_BASE_DTB) +dtb-y += $(pineapple-dtb-y) + endif always-y := $(dtb-y) diff --git a/qcom/ipcc-test.dtsi b/qcom/ipcc-test.dtsi new file mode 100644 index 00000000..9db151b7 --- /dev/null +++ b/qcom/ipcc-test.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + ipcc_self_ping_apss: ipcc-self-ping-apss { + compatible = "qcom,ipcc-self-ping"; + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS + IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; + }; + + ipcc_self_ping_cdsp: ipcc-self-ping-cdsp { + compatible = "qcom,ipcc-self-ping"; + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_PING>; + }; + + ipcc_self_ping_adsp: ipcc-self-ping-adsp { + compatible = "qcom,ipcc-self-ping"; + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_PING>; + }; + + ipcc_self_ping_slpi: ipcc-self-ping-slpi { + compatible = "qcom,ipcc-self-ping"; + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_PING>; + }; +}; diff --git a/qcom/msm-arm-smmu-pineapple.dtsi b/qcom/msm-arm-smmu-pineapple.dtsi new file mode 100644 index 00000000..46b84921 --- /dev/null +++ b/qcom/msm-arm-smmu-pineapple.dtsi @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x000 0x3ff 0x32B>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + gpu_qtb: gpu_qtb@3de8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <2>; + }; + }; + + ubwcp_smmu: ubwcp-smmu@179a0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x179a0000 0x10000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,regulator-names = "vdd"; + vdd-supply = <&apss_ubwcp_pwr_ctrl>; + + qcom,actlr = + /* All CBs of UBWC-P: +15 deep PF */ + <0x000 0x3ff 0x32B>; + + qcom,ignore-numpagendxb; + + interrupts = , + , + , + , + ; + + ubwcp_qtb: ubwcp_qtb@179e8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x179e8000 0x1000>; + qcom,stream-id-range = <0x0 0x2>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x1c00 0x2>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,actlr = + /* Camera IFE */ + <0x0800 0x0020 0x00000001>, + + /* Camera SBI */ + <0x0840 0x0000 0x00000103>, + + /* Camera IPE, BPS, CDM and ICP */ + <0x1800 0x0000 0x00000001>, + <0x1820 0x0000 0x00000001>, + <0x1840 0x0000 0x00000001>, + <0x1860 0x0000 0x00000001>, + <0x1880 0x0000 0x00000001>, + <0x18c0 0x0000 0x00000001>, + + /* Camera JPEG */ + <0x18a0 0x0040 0x00000103>, + + /* Compute */ + <0x0c01 0x0020 0x00000303>, + <0x0c02 0x0020 0x00000303>, + <0x0c03 0x0020 0x00000303>, + <0x0c04 0x0020 0x00000303>, + <0x0c05 0x0020 0x00000303>, + <0x0c06 0x0020 0x00000303>, + <0x0c07 0x0020 0x00000303>, + <0x0c08 0x0020 0x00000303>, + <0x0c09 0x0020 0x00000303>, + <0x0c0c 0x0020 0x00000303>, + <0x0c0d 0x0020 0x00000303>, + <0x0c0e 0x0020 0x00000303>, + <0x1961 0x0000 0x00000303>, + <0x1962 0x0000 0x00000303>, + <0x1963 0x0000 0x00000303>, + <0x1964 0x0000 0x00000303>, + <0x1965 0x0000 0x00000303>, + <0x1966 0x0000 0x00000303>, + <0x1967 0x0000 0x00000303>, + <0x1968 0x0000 0x00000303>, + <0x1969 0x0000 0x00000303>, + <0x196c 0x0000 0x00000303>, + <0x196d 0x0000 0x00000303>, + <0x196e 0x0000 0x00000303>, + <0x19c1 0x0000 0x00000303>, + <0x19c2 0x0000 0x00000303>, + <0x19c3 0x0000 0x00000303>, + <0x19c4 0x0000 0x00000303>, + <0x19c5 0x0000 0x00000303>, + <0x19c6 0x0000 0x00000303>, + <0x19c7 0x0000 0x00000303>, + <0x19c8 0x0000 0x00000303>, + <0x19c9 0x0000 0x00000303>, + <0x19cc 0x0000 0x00000303>, + <0x19cd 0x0000 0x00000303>, + <0x19ce 0x0000 0x00000303>, + + /* Display */ + <0x1c00 0x0002 0x00000001>, + <0x1c01 0x0000 0x00000001>, + + /* EVA */ + <0x1920 0x0000 0x00000103>, + <0x1923 0x0000 0x00000103>, + <0x1924 0x0000 0x00000103>, + + /* Video */ + <0x1940 0x0000 0x00000103>, + <0x1941 0x0004 0x00000103>, + <0x1943 0x0000 0x00000103>, + <0x1944 0x0000 0x00000103>, + <0x1947 0x0000 0x00000103>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_qtb: anoc_1_qtb@16f1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f1000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <1>; + }; + + anoc_2_qtb: anoc_2_qtb@171a000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171a000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <1>; + }; + + cam_hf_qtb: cam_hf_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <2>; + }; + + nsp_qtb: nsp_qtb@7d3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7d3000 0x1000>; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <34>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <2>; + }; + + lpass_qtb: lpass_qtb@7b3000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x7b3000 0x1000>; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <1>; + }; + + pcie_qtb: pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000>; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <36>; + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + + sf_qtb: sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000>; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <36>; + interconnects = <&mmss_noc MASTER_VIDEO &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <2>; + }; + + mdp_hf_qtb: mdp_hf_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000>; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>; + qcom,num-qtb-ports = <2>; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + dma-coherent; + }; + + }; +}; diff --git a/qcom/msm-rdbg.dtsi b/qcom/msm-rdbg.dtsi new file mode 100644 index 00000000..ac839354 --- /dev/null +++ b/qcom/msm-rdbg.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* smp2p information */ + qcom,smp2p_interrupt_rdbg_2_out { + compatible = "qcom,smp2p-interrupt-rdbg-2-out"; + qcom,smem-states = <&smp2p_rdbg2_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + + qcom,smp2p_interrupt_rdbg_2_in { + compatible = "qcom,smp2p-interrupt-rdbg-2-in"; + interrupts-extended = <&smp2p_rdbg2_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; + + qcom,smp2p_interrupt_rdbg_5_out { + compatible = "qcom,smp2p-interrupt-rdbg-5-out"; + qcom,smem-states = <&smp2p_rdbg5_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + + qcom,smp2p_interrupt_rdbg_5_in { + compatible = "qcom,smp2p-interrupt-rdbg-5-in"; + interrupts-extended = <&smp2p_rdbg5_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; +}; diff --git a/qcom/pineapple-atp-overlay.dts b/qcom/pineapple-atp-overlay.dts new file mode 100644 index 00000000..e669d1ce --- /dev/null +++ b/qcom/pineapple-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple ATP"; + compatible = "qcom,pineapple-atp", "qcom,pineapple", "qcom,pineapplep-atp", "qcom,pineapple", "qcom,atp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/pineapple-atp.dtsi b/qcom/pineapple-atp.dtsi new file mode 100644 index 00000000..5766f2fe --- /dev/null +++ b/qcom/pineapple-atp.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-mtp.dtsi" diff --git a/qcom/pineapple-cdp-nfc-overlay.dts b/qcom/pineapple-cdp-nfc-overlay.dts new file mode 100644 index 00000000..b59c4e47 --- /dev/null +++ b/qcom/pineapple-cdp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-cdp-nfc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple CDP ST54L NFC"; + compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x50001 0>; +}; diff --git a/qcom/pineapple-cdp-nfc.dtsi b/qcom/pineapple-cdp-nfc.dtsi new file mode 100644 index 00000000..f17be4ec --- /dev/null +++ b/qcom/pineapple-cdp-nfc.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-cdp.dtsi" diff --git a/qcom/pineapple-cdp-overlay.dts b/qcom/pineapple-cdp-overlay.dts new file mode 100644 index 00000000..176c8902 --- /dev/null +++ b/qcom/pineapple-cdp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple CDP"; + compatible = "qcom,pineapple-cdp", "qcom,pineapple", "qcom,pineapplep-cdp", "qcom,pineapplep", "qcom,cdp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/pineapple-cdp.dtsi b/qcom/pineapple-cdp.dtsi new file mode 100644 index 00000000..6bdae2db --- /dev/null +++ b/qcom/pineapple-cdp.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "pineapple-pmic-overlay.dtsi" +#include "pineapple-thermal-overlay.dtsi" + +&sdhc_2 { + status = "ok"; + vdd-supply = <&pm_humu_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm_humu_l8>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>; + pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>; + + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qcom,iommu-dma = "fastmap"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6d_l1>; + vdda-phy-max-microamp = <211000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8_l1>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v6c_l1>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&pm_v6c_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v6c_s1>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; + +&pm8550_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8550_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8550_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8550_flash { + status = "ok"; +}; + +&eusb2_phy0 { + dummy-supply = <&pm8550b_eusb2_repeater>; + usb-repeater = <&pm8550b_eusb2_repeater>; +}; + +&usb0 { + usb-role-switch; + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; + +&qupv3_se4_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L14B>; + iovdd-supply = <&L12B>; + interrupt-parent = <&tlmm>; + interrupts = <162 0x2008>; + goodix,reset-gpio = <&tlmm 161 0x00>; + goodix,irq-gpio = <&tlmm 162 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <598>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0 + &tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>; + }; +}; + +&qupv3_se7_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S2"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S2"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L14B>; + iovdd-supply = <&L12B>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + goodix,reset-gpio = <&tlmm 91 0x00>; + goodix,irq-gpio = <&tlmm 88 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,touch-type = "secondary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "secondary"; + qts,trusted-touch-spi-irq = <657>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 60 0 &tlmm 61 0 &tlmm 62 0 + &tlmm 63 0 &tlmm 91 0 &tlmm 88 0x2008>; + }; +}; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1e4-supply = <&BOB1>; + periph-1e6-supply = <&BOB2>; + periph-29b-supply = <&S1C>; + periph-29e-supply = <&S2C>; + periph-2a1-supply = <&S3C>; + periph-2a4-supply = <&S4C>; + periph-2a7-supply = <&S5C>; + periph-2aa-supply = <&S6C>; + periph-2c1-supply = <&L1C>; + periph-2c2-supply = <&L2C>; + periph-2c3-supply = <&L3C>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a4-supply = <&S4D_LEVEL>; + periph-3a7-supply = <&S5D_LEVEL>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D_LEVEL>; + periph-3c3-supply = <&L3D>; + periph-4c2-supply = <&L2E>; + periph-4c3-supply = <&L3E>; + periph-69b-supply = <&S1G_LEVEL>; + periph-6a1-supply = <&S3G>; + periph-6a4-supply = <&S4G_LEVEL>; + periph-6a7-supply = <&S5G_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-89b-supply = <&S1I_LEVEL>; + periph-8a1-supply = <&S3I_LEVEL>; + periph-8a4-supply = <&S4I>; + periph-8a7-supply = <&S5I>; + periph-8aa-supply = <&S6I_LEVEL>; + periph-8b0-supply = <&S8I_LEVEL>; + periph-8c1-supply = <&L1I>; + periph-8c2-supply = <&L2I>; + periph-8c3-supply = <&L3I>; + periph-ac1-supply = <&L1K>; + periph-ac2-supply = <&L2K>; + periph-ac3-supply = <&L3K>; + periph-ac4-supply = <&L4K>; + periph-ac5-supply = <&L5K>; + periph-ac6-supply = <&L6K>; + periph-ac7-supply = <&L7K>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/pineapple-coresight.dtsi b/qcom/pineapple-coresight.dtsi new file mode 100644 index 00000000..20542d57 --- /dev/null +++ b/qcom/pineapple-coresight.dtsi @@ -0,0 +1,4896 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + stm: stm@10002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb962>; + reg = <0x10002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + atid = <16>; + coresight-name = "coresight-stm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_stm>; + }; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + atid = <40 41>; + + out-ports { + port { + audio_etm0_out_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_in_audio_etm0>; + }; + }; + }; + }; + + tpdm_ddr_lpi: tpdm@10b30000 { + compatible = "qcom,coresight-dummy"; + qcom,dummy-source; + + atid = <27>; + coresight-name = "coresight-tpdm-ddr-lpi"; + + out-ports { + port { + tpdm_ddr_lpi_out_tpda_ddr_lpi: endpoint { + remote-endpoint = + <&tpda_ddr_lpi_in_tpdm_ddr_lpi>; + }; + }; + }; + }; + + tpdm_lpass_lpi: tpdm@10b46000 { + compatible = "qcom,coresight-dummy"; + qcom,dummy-source; + coresight-name = "coresight-tpdm-lpass-lpi"; + + atid = <26>; + out-ports { + port { + tpdm_lpass_lpi_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_tpdm_lpass_lpi>; + }; + }; + }; + }; + + lpass_stm: lpass_stm { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-lpass-stm"; + qcom,dummy-source; + + atid = <25>; + + out-ports { + port { + lpass_stm_out_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_in_lpass_stm>; + }; + }; + }; + }; + + funnel_lpass_lpi_1: funnel@10b50000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi_1"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_1_in_lpass_stm: endpoint { + remote-endpoint = + <&lpass_stm_out_funnel_lpass_lpi_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_lpi_1_in_tpdm_lpass_lpi: endpoint { + remote-endpoint = + <&tpdm_lpass_lpi_out_funnel_lpass_lpi_1>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_1_out_funnel_lpass_lpi_0: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_0_in_funnel_lpass_lpi_1>; + }; + }; + + }; + }; + + funnel_lpass_lpi_0: funnel@10b44000 { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-lpass_lpi_0"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_lpi_in_audio_etm0: endpoint { + remote-endpoint = + <&audio_etm0_out_funnel_lpass_lpi>; + }; + }; + + port@7 { + reg = <7>; + funnel_lpass_lpi_0_in_funnel_lpass_lpi_1: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_1_out_funnel_lpass_lpi_0>; + }; + }; + + }; + + out-ports { + port { + funnel_lpass_lpi_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_lpass_lpi>; + }; + }; + + }; + }; + + tpdm_swao_prio0: tpdm@10b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b09000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <71>; + out-ports { + port { + tpdm_swao_prio0_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio0>; + }; + }; + }; + }; + + tpdm_swao_prio1: tpdm@10b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <71>; + out-ports { + port { + tpdm_swao_prio1_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio1>; + }; + }; + }; + }; + + tpdm_swao_prio2: tpdm@10b0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0b000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <71>; + out-ports { + port { + tpdm_swao_prio2_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio2>; + }; + }; + }; + }; + + tpdm_swao_prio3: tpdm@10b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-prio-3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <71>; + out-ports { + port { + tpdm_swao_prio3_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao_prio3>; + }; + }; + }; + }; + + tpdm_swao: tpdm@10b0d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10b0d000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <71>; + out-ports { + port { + tpdm_swao_out_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_in_tpdm_swao>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@10844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + }; + + tpdm_ddr_ch02: tpdm@10d20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d20000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch02"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ddr_ch02_out_funnel_ddr_ch02: endpoint { + remote-endpoint = + <&funnel_ddr_ch02_in_tpdm_ddr_ch02>; + }; + }; + }; + }; + + tpdm_ddr_ch13: tpdm@10d30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d30000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr-ch13"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ddr_ch13_out_funnel_ddr_ch13: endpoint { + remote-endpoint = + <&funnel_ddr_ch13_in_tpdm_ddr_ch13>; + }; + }; + }; + }; + + tpdm_ddr0: tpdm@10d00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d00000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr0"; + status = "disabled"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ddr0_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_ddr0>; + }; + }; + }; + }; + + tpdm_ddr1: tpdm@10d01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr1"; + status = "disabled"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ddr1_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_tpdm_ddr1>; + }; + }; + }; + }; + + tpdm_video: tpdm@10830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-video"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_video_out_funnel_video: endpoint { + remote-endpoint = + <&funnel_video_in_tpdm_video>; + }; + }; + }; + }; + + tpdm_mdss: tpdm@10c60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c60000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_mdss_out_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_in_tpdm_mdss>; + }; + }; + }; + }; + + tpdm_dl_mm: tpdm@10c08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c08000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-mm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_dl_mm_out_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_in_tpdm_dl_mm>; + }; + }; + }; + }; + + tpdm_rdpm0: tpdm@10c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c38000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-cx"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_rdpm0_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpdm_rdpm0>; + }; + }; + }; + }; + + tpdm_rdpm1: tpdm@10c39000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c39000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-mxc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_rdpm1_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpdm_rdpm1>; + }; + }; + }; + }; + + tpdm_rdpm2: tpdm@10c3a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c3a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-rdpm-mxa"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_rdpm2_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpdm_rdpm2>; + }; + }; + }; + }; + + tpdm_spare: tpdm@10c3b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c3b000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spare"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_spare_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_tpdm_spare>; + }; + }; + }; + }; + + tpdm_gfx: tpdm@10900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10900000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_gfx_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_tpdm_gfx>; + }; + }; + }; + }; + + tpdm_prng: tpdm@10841000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10841000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_prng_out_tpda_dl_center_21: endpoint { + remote-endpoint = + <&tpda_dl_center_21_in_tpdm_prng>; + }; + }; + }; + }; + + tpdm_qm: tpdm@109d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_qm_out_tpda_dl_center_22: endpoint { + remote-endpoint = + <&tpda_dl_center_22_in_tpdm_qm>; + }; + }; + }; + }; + + tpdm_trace_noc: tpdm@10ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10ac0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-trace-noc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <97>; + out-ports { + port { + tpdm_trace_noc_out_trace_noc: endpoint { + remote-endpoint = + <&trace_noc_in_tpdm_trace_noc>; + }; + }; + }; + }; + + tpdm_gcc: tpdm@1082c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1082c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_gcc_out_tpda_dl_center_23: endpoint { + remote-endpoint = + <&tpda_dl_center_23_in_tpdm_gcc>; + }; + }; + }; + }; + + tpdm_vsense: tpdm@10840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10840000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_vsense_out_tpda_dl_center_24: endpoint { + remote-endpoint = + <&tpda_dl_center_24_in_tpdm_vsense>; + }; + }; + }; + }; + + tpdm_ipa: tpdm@10c22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c22000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-ipa"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ipa_out_tpda_dl_center_26: endpoint { + remote-endpoint = + <&tpda_dl_center_26_in_tpdm_ipa>; + }; + }; + }; + }; + + tpdm_dl_ct: tpdm@10c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_dl_ct_out_tpda_dl_center_29: endpoint { + remote-endpoint = + <&tpda_dl_center_29_in_tpdm_dl_ct>; + }; + }; + }; + }; + + tpdm_ipcc: tpdm@10c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c29000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ipcc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <78>; + out-ports { + port { + tpdm_ipcc_out_tpda_dl_center_30: endpoint { + remote-endpoint = + <&tpda_dl_center_30_in_tpdm_ipcc>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@10003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10003000 0x1000>; + reg-names = "tpdm-base"; + + atid = <65>; + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_dcc_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_dcc>; + }; + }; + }; + }; + + tpdm_spdm: tpdm@1000f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x1000f000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spdm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <65>; + out-ports { + port { + tpdm_spdm_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_spdm>; + }; + }; + }; + }; + + tpdm_ddrss_llcc0: tpdm@10d40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d40000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddrss-llcc0"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <80>; + out-ports { + port { + tpdm_ddrss_llcc0_out_tpda_ddr: endpoint { + remote-endpoint = + <&tpda_ddr_in_tpdm_ddrss_llcc0>; + }; + }; + }; + }; + + tpdm_ddrss_llcc1: tpdm@10d41000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d41000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddrss-llcc1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <80>; + out-ports { + port { + tpdm_ddrss_llcc1_out_tpda_ddr: endpoint { + remote-endpoint = + <&tpda_ddr_in_tpdm_ddrss_llcc1>; + }; + }; + }; + }; + + tpdm_ddrss_llcc2: tpdm@10d42000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d42000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddrss-llcc2"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <80>; + out-ports { + port { + tpdm_ddrss_llcc2_out_tpda_ddr: endpoint { + remote-endpoint = + <&tpda_ddr_in_tpdm_ddrss_llcc2>; + }; + }; + }; + }; + + tpdm_ddrss_llcc3: tpdm@10d43000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10d43000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-ddrss-llcc3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <80>; + out-ports { + port { + tpdm_ddrss_llcc3_out_tpda_ddr: endpoint { + remote-endpoint = + <&tpda_ddr_in_tpdm_ddrss_llcc3>; + }; + }; + }; + }; + + tpdm_titan: tpdm@10c16000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c16000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-titan"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <86>; + out-ports { + port { + tpdm_titan_out_tpda_titan: endpoint { + remote-endpoint = + <&tpda_titan_in_tpdm_titan>; + }; + }; + }; + }; + + tpdm_tmess_prng: tpdm@10cc9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc9000 0x1000>; + reg-names = "tpdm-base"; + status = "disabled"; + coresight-name = "coresight-tpdm-tmess-prng"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <100>; + + out-ports { + port { + tpdm_tmess_prng_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess_prng>; + }; + }; + }; + }; + + tpdm_tmess0: tpdm@10cc1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc1000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-tmess0"; + + clocks = <&aoss_qmp>; + status = "disabled"; + clock-names = "apb_pclk"; + qcom,hw-enable-check; + atid = <100>; + + out-ports { + port { + tpdm_tmess0_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess0>; + }; + }; + }; + }; + + tpdm_tmess1: tpdm@10cc0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10cc0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-tmess1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <100>; + qcom,hw-enable-check; + + out-ports { + port { + tpdm_tmess1_out_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_in_tpdm_tmess1>; + }; + }; + }; + }; + + tpdm_turing: tpdm@10980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <87>; + + out-ports { + port { + tpdm_turing_out_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_in_tpdm_turing>; + }; + }; + }; + }; + + tpdm_turing_llm: tpdm@10981000 { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-tpdm-turing-llm"; + qcom,dummy-source; + + atid = <87>; + + out-ports { + port { + tpdm_turing_llm_out_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_in_tpdm_turing_llm>; + }; + }; + }; + }; + + tpdm_turing_llm2: tpdm@10982000 { + compatible = "qcom,coresight-dummy"; + atid = <87>; + coresight-name = "coresight-tpdm-turing-llm2"; + qcom,dummy-source; + + out-ports { + port { + tpdm_turing_llm2_out_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_in_tpdm_turing_llm2>; + }; + }; + }; + }; + + tpdm_dpm1: tpdm@10983000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10983000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dpm1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + atid = <87>; + + out-ports { + port { + tpdm_dpm1_out_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_in_tpdm_dpm1>; + }; + }; + }; + }; + + tpdm_dmp2: tpdm@10984000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10984000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dmp2"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <87>; + out-ports { + port { + tpdm_dmp2_out_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_in_tpdm_dmp2>; + }; + }; + }; + }; + + tpdm_sdcc4: tpdm@10c21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c21000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-sdcc4"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <75>; + out-ports { + port { + tpdm_sdcc4_out_tpda_dl_south: endpoint { + remote-endpoint = + <&tpda_dl_south_in_tpdm_sdcc4>; + }; + }; + }; + }; + + tpdm_ufs: tpdm@10c23000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10c23000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ufs"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <75>; + out-ports { + port { + tpdm_ufs_out_tpda_dl_south: endpoint { + remote-endpoint = + <&tpda_dl_south_in_tpdm_ufs>; + }; + }; + }; + }; + + tpdm_dl_south: tpdm@109c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x109c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <75>; + out-ports { + port { + tpdm_dl_south_out_tpda_dl_south: endpoint { + remote-endpoint = + <&tpda_dl_south_in_tpdm_dl_south>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@138a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_llm_silver_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@138b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_llm_gold_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_gold>; + }; + }; + }; + }; + + tpdm_llm_ext: tpdm@138c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-ext"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_llm_ext_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_ext>; + }; + }; + }; + }; + + tpdm_llm_gold_apc: tpdm@13880000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13880000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold-apc"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_llm_gold_apc_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_llm_gold_apc>; + }; + }; + }; + }; + + tpdm_apss_ubwcp: tpdm@138d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x138d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss-ubwcp"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_apss_ubwcp_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss_ubwcp>; + }; + }; + }; + }; + + tpdm_apss_apc2: tpdm@13890000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13890000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss-apc2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_apss_apc2_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss_apc2>; + }; + }; + }; + }; + + tpdm_apss0: tpdm@13860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_apss_0_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss_0>; + }; + }; + }; + }; + + tpdm_apss1: tpdm@13861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13861000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_apss1_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss1>; + }; + }; + }; + }; + + tpdm_apss2: tpdm@13862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x13862000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <66>; + out-ports { + port { + tpdm_apss2_out_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_in_tpdm_apss2>; + }; + }; + }; + }; + + tpdm_modem0: tpdm@10800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb968>; + reg = <0x10800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + atid = <67>; + out-ports { + port { + tpdm_modem0_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem0>; + }; + }; + }; + }; + + tpdm_modem1: tpdm@10801000 { + compatible = "qcom,coresight-dummy"; + qcom,dummy-source; + coresight-name = "coresight-tpdm-modem-1"; + + atid = <67>; + out-ports { + port { + tpdm_modem1_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem1>; + }; + }; + }; + }; + + tpdm_modem_rscc: tpdm@1080d000 { + compatible = "qcom,coresight-dummy"; + qcom,dummy-source; + coresight-name = "coresight-tpdm-modem-rscc"; + atid = <98>; + out-ports { + port { + tpdm_modem_rscc_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_tpdm_modem_rscc>; + }; + }; + }; + }; + + + trace_noc: traceNoc@10ac1000{ + compatible = "arm,primecell", "qcom,coresight-traceNoc"; + arm,primecell-periphid = <0x000f0c00>; + reg = <0x10ac1000 0x1000>; + reg-names = "traceNoc-base"; + + coresight-name = "coresight-traceNoc"; + atid = <97>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + trace_noc_in_tpdm_trace_noc: endpoint { + remote-endpoint = + <&tpdm_trace_noc_out_trace_noc>; + }; + }; + }; + + out-ports { + port { + trace_noc_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_trace_noc>; + }; + }; + }; + }; + + + tpda_ddr_lpi: tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-ddr_lpi"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_ddr_lpi_in_tpdm_ddr_lpi: endpoint { + remote-endpoint = + <&tpdm_ddr_lpi_out_tpda_ddr_lpi>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_ddr_lpi_out_funnel_ddr_lpi: endpoint { + remote-endpoint = + <&funnel_ddr_lpi_in_tpda_ddr_lpi>; + }; + }; + + }; + }; + + funnel_ddr_lpi: funnel@10b33000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10b33000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_lpi"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_lpi_in_tpda_ddr_lpi: endpoint { + remote-endpoint = + <&tpda_ddr_lpi_out_funnel_ddr_lpi>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_ddr>; + }; + }; + + }; + }; + + funnel_gfx: funnel@10963000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10963000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_gfx_out_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_in_funnel_gfx>; + }; + }; + }; + }; + + funnel_gfx_dl: funnel@10902000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10902000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx_dl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_dl_in_tpdm_gfx: endpoint { + remote-endpoint = + <&tpdm_gfx_out_funnel_gfx_dl>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_dl_in_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_out_funnel_gfx_dl>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_dl_out_tpda_dl_center_19: endpoint { + remote-endpoint = + <&tpda_dl_center_19_in_funnel_gfx_dl>; + source = <&tpdm_gfx>; + }; + }; + + port@1 { + reg = <1>; + funnel_gfx_dl_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_gfx_dl>; + }; + }; + }; + }; + + funnel_video: funnel@10832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10832000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-video"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_video_in_tpdm_video: endpoint { + remote-endpoint = + <&tpdm_video_out_funnel_video>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_video_out_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_in_funnel_video>; + }; + }; + + }; + }; + + tpda_titan: tpda@10c17000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c17000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <86>; + qcom,cmb-elem-size = <0 64>; + coresight-name = "coresight-tpda-titan"; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_titan_in_tpdm_titan: endpoint { + remote-endpoint = + <&tpdm_titan_out_tpda_titan>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_titan_out_funnel_titan: endpoint { + remote-endpoint = + <&funnel_titan_in_tpda_titan>; + }; + }; + + }; + }; + + funnel_titan: funnel@10c14000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c14000 0x1000>; + reg-names = "funnel-base"; + + status = "disabled"; + coresight-name = "coresight-funnel-titan"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_titan_in_tpda_titan: endpoint { + remote-endpoint = + <&tpda_titan_out_funnel_titan>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_titan_out_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_in_funnel_titan>; + }; + }; + + }; + }; + + tpda_tmess: tpda@10cc4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10cc4000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <100>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 64>; + coresight-name = "coresight-tpda-tmess"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_tmess_in_tpdm_tmess_prng: endpoint { + remote-endpoint = + <&tpdm_tmess_prng_out_tpda_tmess>; + }; + }; + + port@1 { + reg = <1>; + tpda_tmess_in_tpdm_tmess0: endpoint { + remote-endpoint = + <&tpdm_tmess0_out_tpda_tmess>; + }; + }; + + port@2 { + reg = <2>; + tpda_tmess_in_tpdm_tmess1: endpoint { + remote-endpoint = + <&tpdm_tmess1_out_tpda_tmess>; + }; + }; + + }; + + out-ports { + + port { + tpda_tmess_out_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_in_tpda_tmess>; + }; + }; + + }; + }; + + funnel_tmess: funnel@10cc5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10cc5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-tmess"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_tmess_in_tpda_tmess: endpoint { + remote-endpoint = + <&tpda_tmess_out_funnel_tmess>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_tmess_out_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_in_funnel_tmess>; + }; + }; + + }; + }; + + funnel_multimedia: funnel@10c0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c0a000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-multimedia"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_multimedia_in_funnel_video: endpoint { + remote-endpoint = + <&funnel_video_out_funnel_multimedia>; + }; + }; + + port@1 { + reg = <1>; + funnel_multimedia_in_tpdm_mdss: endpoint { + remote-endpoint = + <&tpdm_mdss_out_funnel_multimedia>; + }; + }; + + port@3 { + reg = <3>; + funnel_multimedia_in_tpdm_dl_mm: endpoint { + remote-endpoint = + <&tpdm_dl_mm_out_funnel_multimedia>; + }; + }; + + port@5 { + reg = <5>; + funnel_multimedia_in_funnel_titan: endpoint { + remote-endpoint = + <&funnel_titan_out_funnel_multimedia>; + }; + }; + + port@6 { + reg = <6>; + funnel_multimedia_in_funnel_tmess: endpoint { + remote-endpoint = + <&funnel_tmess_out_funnel_multimedia>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_multimedia_out_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_in_funnel_multimedia>; + }; + }; + + }; + }; + + funnel_lpass: funnel@10846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_in_tpdm_lpass: endpoint { + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_out_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_in_funnel_lpass>; + }; + }; + + }; + }; + + funnel_ddr_ch02: funnel@10d22000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d22000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_ch02"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_ch02_in_tpdm_ddr_ch02: endpoint { + remote-endpoint = + <&tpdm_ddr_ch02_out_funnel_ddr_ch02>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_ch02_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_ch02>; + }; + }; + + }; + }; + + funnel_ddr_ch13: funnel@10d32000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d32000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_ch13"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_ch13_in_tpdm_ddr_ch13: endpoint { + remote-endpoint = + <&tpdm_ddr_ch13_out_funnel_ddr_ch13>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_ch13_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_ch13>; + }; + }; + + }; + }; + + tpda_ddr: tpda@10d09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + qcom,tpda-atid = <80>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <2 32>, + <3 32>; + reg = <0x10d09000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-ddr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_ddr_in_tpdm_ddrss_llcc0: endpoint { + remote-endpoint = + <&tpdm_ddrss_llcc0_out_tpda_ddr>; + }; + }; + + port@1 { + reg = <1>; + tpda_ddr_in_tpdm_ddrss_llcc1: endpoint { + remote-endpoint = + <&tpdm_ddrss_llcc1_out_tpda_ddr>; + }; + }; + + port@2 { + reg = <2>; + tpda_ddr_in_tpdm_ddrss_llcc2: endpoint { + remote-endpoint = + <&tpdm_ddrss_llcc2_out_tpda_ddr>; + }; + }; + + port@3 { + reg = <3>; + tpda_ddr_in_tpdm_ddrss_llcc3: endpoint { + remote-endpoint = + <&tpdm_ddrss_llcc3_out_tpda_ddr>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_ddr_out_funnel_ddr_dl1: endpoint { + remote-endpoint = + <&funnel_ddr_dl1_in_tpda_ddr>; + }; + }; + + }; + }; + + gladiator: gladiator { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-gladiator"; + qcom,dummy-source; + + atid = <96>; + + out-ports { + port { + gladiator_out_funnel_ddr_dl1: endpoint { + remote-endpoint = + <&funnel_ddr_dl1_in_gladiator>; + }; + }; + }; + }; + + funnel_ddr_dl1: funnel@10d0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d0a000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_dl1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl1_in_tpda_ddr: endpoint { + remote-endpoint = + <&tpda_ddr_out_funnel_ddr_dl1>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl1_in_gladiator: endpoint { + remote-endpoint = + <&gladiator_out_funnel_ddr_dl1>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl1_out_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_in_funnel_ddr_dl1>; + }; + }; + + }; + }; + + funnel_ddr_dl0: funnel@10d03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10d03000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr_dl0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl0_in_funnel_ddr_ch02: endpoint { + remote-endpoint = + <&funnel_ddr_ch02_out_funnel_ddr_dl0>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_dl0_in_funnel_ddr_ch13: endpoint { + remote-endpoint = + <&funnel_ddr_ch13_out_funnel_ddr_dl0>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_dl0_in_tpdm_ddr0: endpoint { + remote-endpoint = + <&tpdm_ddr0_out_funnel_ddr_dl0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl0_in_tpdm_ddr1: endpoint { + remote-endpoint = + <&tpdm_ddr1_out_funnel_ddr_dl0>; + }; + }; + + port@4 { + reg = <4>; + funnel_ddr_dl0_in_funnel_ddr_dl1: endpoint { + remote-endpoint = + <&funnel_ddr_dl1_out_funnel_ddr_dl0>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_dl0_out_tpda_dl_center_4: endpoint { + remote-endpoint = + <&tpda_dl_center_4_in_funnel_ddr_dl0>; + source = <&tpdm_ddr_ch02>; + }; + }; + + port@1 { + reg = <1>; + funnel_ddr_dl0_out_tpda_dl_center_5: endpoint { + remote-endpoint = + <&tpda_dl_center_5_in_funnel_ddr_dl0>; + source = <&tpdm_ddr_ch13>; + }; + }; + + port@2 { + reg = <2>; + funnel_ddr_dl0_out_tpda_dl_center_6: endpoint { + remote-endpoint = + <&tpda_dl_center_6_in_funnel_ddr_dl0>; + source = <&tpdm_ddr0>; + }; + }; + + port@3 { + reg = <3>; + funnel_ddr_dl0_out_tpda_dl_center_7: endpoint { + remote-endpoint = + <&tpda_dl_center_7_in_funnel_ddr_dl0>; + source = <&tpdm_ddr1>; + }; + }; + + port@4 { + reg = <4>; + funnel_ddr_dl0_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_ddr_dl0>; + }; + }; + }; + }; + + tpda_turing: tpda@10986000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10986000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <87>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <1 32>, + <2 32>, + <3 64>, + <4 64>; + coresight-name = "coresight-tpda-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_turing_in_tpdm_turing: endpoint { + remote-endpoint = + <&tpdm_turing_out_tpda_turing>; + }; + }; + + port@1 { + reg = <1>; + tpda_turing_in_tpdm_turing_llm: endpoint { + remote-endpoint = + <&tpdm_turing_llm_out_tpda_turing>; + }; + }; + + port@2 { + reg = <2>; + tpda_turing_in_tpdm_turing_llm2: endpoint { + remote-endpoint = + <&tpdm_turing_llm2_out_tpda_turing>; + }; + }; + + port@3 { + reg = <3>; + tpda_turing_in_tpdm_dpm1: endpoint { + remote-endpoint = + <&tpdm_dpm1_out_tpda_turing>; + }; + }; + + port@4 { + reg = <4>; + tpda_turing_in_tpdm_dmp2: endpoint { + remote-endpoint = + <&tpdm_dmp2_out_tpda_turing>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpda_turing>; + }; + }; + + }; + }; + + turing_etm0: turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + atid = <38 39>; + + out-ports { + port { + turing_etm0_out_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_in_turing_etm0>; + }; + }; + }; + }; + + funnel_turing_dup: funnel@10940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10940000 0x1000>, + <0x10987000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing_dup"; + + qcom,duplicate-funnel; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@4 { + reg = <3>; + funnel_turing_dup_in_turing_etm0: endpoint { + remote-endpoint = + <&turing_etm0_out_funnel_turing_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_turing_dup_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_funnel_turing_dup>; + }; + }; + + }; + }; + + funnel_turing: funnel@10987000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10987000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_in_tpda_turing: endpoint { + remote-endpoint = + <&tpda_turing_out_funnel_turing>; + }; + }; + + port@4 { + reg = <4>; + funnel_turing_in_funnel_turing_dup: endpoint { + remote-endpoint = + <&funnel_turing_dup_out_funnel_turing>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_turing>; + }; + }; + + }; + }; + + funnel_dl_west: funnel@10c3c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c3c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_west"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_west_in_funnel_multimedia: endpoint { + remote-endpoint = + <&funnel_multimedia_out_funnel_dl_west>; + }; + }; + + port@1 { + reg = <2>; + funnel_dl_west_in_tpdm_rdpm0: endpoint { + remote-endpoint = + <&tpdm_rdpm0_out_funnel_dl_west>; + }; + }; + + port@2 { + reg = <3>; + funnel_dl_west_in_tpdm_rdpm1: endpoint { + remote-endpoint = + <&tpdm_rdpm1_out_funnel_dl_west>; + }; + }; + + port@3 { + reg = <4>; + funnel_dl_west_in_tpdm_rdpm2: endpoint { + remote-endpoint = + <&tpdm_rdpm2_out_funnel_dl_west>; + }; + }; + + port@4 { + reg = <5>; + funnel_dl_west_in_tpdm_spare: endpoint { + remote-endpoint = + <&tpdm_spare_out_funnel_dl_west>; + }; + }; + + }; + + out-ports { + port@0 { + reg = <0>; + funnel_dl_west_out_tpda_dl_center_8: endpoint { + remote-endpoint = + <&tpda_dl_center_8_in_funnel_dl_west>; + source = <&tpdm_video>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_west_out_tpda_dl_center_9: endpoint { + remote-endpoint = + <&tpda_dl_center_9_in_funnel_dl_west>; + source = <&tpdm_mdss>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_west_out_tpda_dl_center_11: endpoint { + remote-endpoint = + <&tpda_dl_center_11_in_funnel_dl_west>; + source = <&tpdm_dl_mm>; + }; + }; + + port@3 { + reg = <3>; + funnel_dl_west_out_tpda_dl_center_13: endpoint { + remote-endpoint = + <&tpda_dl_center_13_in_funnel_dl_west>; + source = <&tpdm_rdpm0>; + }; + }; + + port@4 { + reg = <4>; + funnel_dl_west_out_tpda_dl_center_14: endpoint { + remote-endpoint = + <&tpda_dl_center_14_in_funnel_dl_west>; + source = <&tpdm_rdpm1>; + }; + }; + + port@5 { + reg = <5>; + funnel_dl_west_out_tpda_dl_center_15: endpoint { + remote-endpoint = + <&tpda_dl_center_15_in_funnel_dl_west>; + source = <&tpdm_rdpm2>; + }; + }; + + port@6 { + reg = <6>; + funnel_dl_west_out_tpda_dl_center_16: endpoint { + remote-endpoint = + <&tpda_dl_center_16_in_funnel_dl_west>; + source = <&tpdm_spare>; + }; + }; + + port@7 { + reg = <7>; + funnel_dl_west_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_funnel_dl_west>; + }; + }; + }; + }; + + tpda_dl_south: tpda@109c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x109c1000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <75>; + qcom,dsb-elem-size = <4 32>; + qcom,cmb-elem-size = <1 32>, + <2 32>; + + coresight-name = "coresight-tpda-dl_south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + tpda_dl_south_in_tpdm_sdcc4: endpoint { + remote-endpoint = + <&tpdm_sdcc4_out_tpda_dl_south>; + }; + }; + + port@2 { + reg = <2>; + tpda_dl_south_in_tpdm_ufs: endpoint { + remote-endpoint = + <&tpdm_ufs_out_tpda_dl_south>; + }; + }; + + port@4 { + reg = <4>; + tpda_dl_south_in_tpdm_dl_south: endpoint { + remote-endpoint = + <&tpdm_dl_south_out_tpda_dl_south>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_south_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpda_dl_south>; + }; + }; + + }; + }; + + funnel_dl_south: funnel@109c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x109c2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_south"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_in_tpda_dl_south: endpoint { + remote-endpoint = + <&tpda_dl_south_out_funnel_dl_south>; + }; + }; + + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_south>; + }; + }; + + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + qcom,secure-component; + atid = <36 37>; + out-ports { + port { + modem_etm0_out_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_in_modem_etm0>; + }; + }; + }; + }; + + modem2_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem2-etm0"; + qcom,inst-id = <11>; + + atid = <39>; + out-ports { + port { + modem2_etm0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_modem2_etm0>; + }; + }; + }; + }; + + modem_diag: modem_diag { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-modem-diag"; + qcom,dummy-source; + + atid = <50>; + out-ports { + port { + modem_diag_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_modem_diag>; + }; + }; + }; + }; + + tpda_modem: tpda@10803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10803000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + coresight-name = "coresight-tpda-modem"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_modem_in_tpdm_modem0: endpoint { + remote-endpoint = + <&tpdm_modem0_out_tpda_modem>; + }; + }; + + port@1 { + reg = <1>; + tpda_modem_in_tpdm_modem1: endpoint { + remote-endpoint = + <&tpdm_modem1_out_tpda_modem>; + }; + }; + + }; + + out-ports { + + port { + tpda_modem_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_tpda_modem>; + }; + }; + + }; + }; + + funnel_modem_q6_dup: funnel@1080d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080d000 0x1000>, + <0x1080c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem_q6_dup"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_q6_dup_in_modem_etm0: endpoint { + remote-endpoint = + <&modem_etm0_out_funnel_modem_q6_dup>; + }; + }; + + }; + + out-ports { + port { + funnel_modem_q6_dup_out_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_in_funnel_modem_q6_dup>; + }; + }; + + }; + }; + + funnel_modem_q6: funnel@1080c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x1080c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_q6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_modem_q6_in_funnel_modem_q6_dup: endpoint { + remote-endpoint = + <&funnel_modem_q6_dup_out_funnel_modem_q6>; + }; + }; + + port@2 { + reg = <2>; + funnel_modem_q6_in_modem_diag: endpoint { + remote-endpoint = + <&modem_diag_out_funnel_modem_q6>; + }; + }; + + port@3 { + funnel_modem_q6_in_tpdm_modem_rscc: endpoint { + remote-endpoint = + <&tpdm_modem_rscc_out_funnel_modem_q6>; + }; + }; + + }; + + out-ports { + + port { + funnel_modem_q6_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_funnel_modem_q6>; + }; + }; + + }; + }; + + funnel_modem_dl: funnel@10804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem_dl"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_dl_in_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_out_funnel_modem_dl>; + }; + }; + + port@1 { + reg = <1>; + funnel_modem_in_modem2_etm0: endpoint { + remote-endpoint = + <&modem2_etm0_out_funnel_modem>; + }; + }; + + port@3 { + reg = <3>; + funnel_modem_dl_in_funnel_modem_q6: endpoint { + remote-endpoint = + <&funnel_modem_q6_out_funnel_modem_dl>; + }; + }; + + }; + + out-ports { + + port { + funnel_modem_dl_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem_dl>; + }; + }; + + }; + }; + + tpda_apss: tpda@13864000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x13864000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <2 32>, + <4 32>, + <5 32>, + <8 32>; + qcom,cmb-elem-size = <0 32>, + <1 32>, + <3 32>, + <6 64>, + <7 64>; + coresight-name = "coresight-tpda-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_apss_in_tpdm_llm_silver: endpoint { + remote-endpoint = + <&tpdm_llm_silver_out_tpda_apss>; + }; + }; + + port@1 { + reg = <1>; + tpda_apss_in_tpdm_llm_gold: endpoint { + remote-endpoint = + <&tpdm_llm_gold_out_tpda_apss>; + }; + }; + + port@2 { + reg = <2>; + tpda_apss_in_tpdm_llm_ext: endpoint { + remote-endpoint = + <&tpdm_llm_ext_out_tpda_apss>; + }; + }; + + port@3 { + reg = <3>; + tpda_apss_in_tpdm_llm_gold_apc: endpoint { + remote-endpoint = + <&tpdm_llm_gold_apc_out_tpda_apss>; + }; + }; + + port@4 { + reg = <4>; + tpda_apss_in_tpdm_apss_ubwcp: endpoint { + remote-endpoint = + <&tpdm_apss_ubwcp_out_tpda_apss>; + }; + }; + + port@5 { + reg = <5>; + tpda_apss_in_tpdm_apss_apc2: endpoint { + remote-endpoint = + <&tpdm_apss_apc2_out_tpda_apss>; + }; + }; + + port@6 { + reg = <6>; + tpda_apss_in_tpdm_apss_0: endpoint { + remote-endpoint = + <&tpdm_apss_0_out_tpda_apss>; + }; + }; + + port@7 { + reg = <7>; + tpda_apss_in_tpdm_apss1: endpoint { + remote-endpoint = + <&tpdm_apss1_out_tpda_apss>; + }; + }; + + port@8 { + reg = <8>; + tpda_apss_in_tpdm_apss2: endpoint { + remote-endpoint = + <&tpdm_apss2_out_tpda_apss>; + }; + }; + + }; + + out-ports { + + port { + tpda_apss_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_tpda_apss>; + }; + }; + + }; + }; + + funnel_apss: funnel@13810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x13810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_apss_in_tpda_apss: endpoint { + remote-endpoint = + <&tpda_apss_out_funnel_apss>; + }; + }; + + }; + + out-ports { + + port { + funnel_apss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss>; + }; + }; + + }; + }; + + tpda_dl_center: tpda@10c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10c2c000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <78>; + qcom,dsb-elem-size = <0 32>, + <4 32>, + <5 32>, + <6 32>, + <8 32>, + <11 32>, + <22 32>, + <23 32>, + <29 32>; + + qcom,cmb-elem-size = <7 64>, + <9 32>, + <13 64>, + <14 64>, + <15 64>, + <16 64>, + <21 32>, + <24 32>, + <26 64>, + <30 64>; + coresight-name = "coresight-tpda-dl_center"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_dl_center_in_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_out_tpda_dl_center>; + }; + }; + + port@4 { + reg = <4>; + tpda_dl_center_4_in_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_out_tpda_dl_center_4>; + }; + }; + + port@5 { + reg = <5>; + tpda_dl_center_5_in_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_out_tpda_dl_center_5>; + }; + }; + + port@6 { + reg = <6>; + tpda_dl_center_6_in_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_out_tpda_dl_center_6>; + }; + }; + + port@7 { + reg = <7>; + tpda_dl_center_7_in_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_out_tpda_dl_center_7>; + }; + }; + + port@8 { + reg = <8>; + tpda_dl_center_8_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_8>; + }; + }; + + port@9 { + reg = <9>; + tpda_dl_center_9_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_9>; + }; + }; + + port@11 { + reg = <11>; + tpda_dl_center_11_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_11>; + }; + }; + + port@13 { + reg = <13>; + tpda_dl_center_13_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_13>; + }; + }; + + port@14 { + reg = <14>; + tpda_dl_center_14_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_14>; + }; + }; + + port@15 { + reg = <15>; + tpda_dl_center_15_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_15>; + }; + }; + + port@16 { + reg = <16>; + tpda_dl_center_16_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_tpda_dl_center_16>; + }; + }; + + port@19 { + reg = <19>; + tpda_dl_center_19_in_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_out_tpda_dl_center_19>; + }; + }; + + port@21 { + reg = <21>; + tpda_dl_center_21_in_tpdm_prng: endpoint { + remote-endpoint = + <&tpdm_prng_out_tpda_dl_center_21>; + }; + }; + + port@22 { + reg = <22>; + tpda_dl_center_22_in_tpdm_qm: endpoint { + remote-endpoint = + <&tpdm_qm_out_tpda_dl_center_22>; + }; + }; + + port@23 { + reg = <23>; + tpda_dl_center_23_in_tpdm_gcc: endpoint { + remote-endpoint = + <&tpdm_gcc_out_tpda_dl_center_23>; + }; + }; + + port@24 { + reg = <24>; + tpda_dl_center_24_in_tpdm_vsense: endpoint { + remote-endpoint = + <&tpdm_vsense_out_tpda_dl_center_24>; + }; + }; + + port@26 { + reg = <26>; + tpda_dl_center_26_in_tpdm_ipa: endpoint { + remote-endpoint = + <&tpdm_ipa_out_tpda_dl_center_26>; + }; + }; + + port@29 { + reg = <29>; + tpda_dl_center_29_in_tpdm_dl_ct: endpoint { + remote-endpoint = + <&tpdm_dl_ct_out_tpda_dl_center_29>; + }; + }; + + port@30 { + reg = <30>; + tpda_dl_center_30_in_tpdm_ipcc: endpoint { + remote-endpoint = + <&tpdm_ipcc_out_tpda_dl_center_30>; + }; + }; + }; + + out-ports { + + port { + tpda_dl_center_out_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_in_tpda_dl_center>; + }; + }; + + }; + }; + + funnel_dl_center: funnel@10c2d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10c2d000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl_center"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_center_in_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_out_funnel_dl_center>; + }; + }; + + port@2 { + reg = <2>; + funnel_dl_center_in_funnel_ddr_dl0: endpoint { + remote-endpoint = + <&funnel_ddr_dl0_out_funnel_dl_center>; + }; + }; + + port@3 { + reg = <3>; + funnel_dl_center_in_funnel_dl_west: endpoint { + remote-endpoint = + <&funnel_dl_west_out_funnel_dl_center>; + }; + }; + + port@5 { + reg = <5>; + funnel_dl_center_in_funnel_gfx_dl: endpoint { + remote-endpoint = + <&funnel_gfx_dl_out_funnel_dl_center>; + }; + }; + + port@7 { + reg = <7>; + funnel_dl_center_in_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_out_funnel_dl_center>; + }; + }; + + }; + + out-ports { + + port { + funnel_dl_center_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_center>; + }; + }; + + }; + }; + + tpda_qdss: tpda@10004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10004000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <65>; + qcom,cmb-elem-size = <0 32>, + <1 32>; + coresight-name = "coresight-tpda-qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss>; + }; + }; + + port@1 { + reg = <1>; + tpda_qdss_in_tpdm_spdm: endpoint { + remote-endpoint = + <&tpdm_spdm_out_tpda_qdss>; + }; + }; + + }; + + out-ports { + + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + + }; + }; + + funnel_in0: funnel@10041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel_in0_in_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_out_funnel_in0>; + }; + }; + + port@7 { + reg = <7>; + funnel_in0_in_stm: endpoint { + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in0>; + }; + }; + + }; + }; + + funnel_qdss: funnel@10045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qdss_in_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_out_funnel_qdss>; + }; + }; + + port@1 { + reg = <1>; + funnel_qdss_in_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_out_funnel_qdss>; + }; + }; + + }; + + out-ports { + port { + funnel_qdss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_funnel_qdss>; + }; + }; + + }; + }; + + tpda_aoss: tpda@10b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb969>; + + reg = <0x10b08000 0x1000>; + reg-names = "tpda-base"; + + qcom,tpda-atid = <71>; + qcom,cmb-elem-size = <0 64>, + <1 64>, + <2 64>, + <3 64>; + + qcom,dsb-elem-size = <4 32>; + coresight-name = "coresight-tpda-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_aoss_in_tpdm_swao_prio0: endpoint { + remote-endpoint = + <&tpdm_swao_prio0_out_tpda_aoss>; + }; + }; + + port@1 { + reg = <1>; + tpda_aoss_in_tpdm_swao_prio1: endpoint { + remote-endpoint = + <&tpdm_swao_prio1_out_tpda_aoss>; + }; + }; + + port@2 { + reg = <2>; + tpda_aoss_in_tpdm_swao_prio2: endpoint { + remote-endpoint = + <&tpdm_swao_prio2_out_tpda_aoss>; + }; + }; + + port@3 { + reg = <3>; + tpda_aoss_in_tpdm_swao_prio3: endpoint { + remote-endpoint = + <&tpdm_swao_prio3_out_tpda_aoss>; + }; + }; + + port@4 { + reg = <4>; + tpda_aoss_in_tpdm_swao: endpoint { + remote-endpoint = + <&tpdm_swao_out_tpda_aoss>; + }; + }; + + }; + + out-ports { + + port { + tpda_aoss_out_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_in_tpda_aoss>; + }; + }; + + }; + }; + + funnel_aoss: funnel@10b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-aoss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_aoss_in_funnel_ddr: endpoint { + remote-endpoint = + <&funnel_ddr_out_funnel_aoss>; + }; + }; + + port@5 { + reg = <5>; + funnel_aoss_in_funnel_lpass_lpi: endpoint { + remote-endpoint = + <&funnel_lpass_lpi_out_funnel_aoss>; + }; + }; + + port@6 { + reg = <6>; + funnel_aoss_in_tpda_aoss: endpoint { + remote-endpoint = + <&tpda_aoss_out_funnel_aoss>; + }; + }; + + port@7 { + reg = <7>; + funnel_aoss_in_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_out_funnel_aoss>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_aoss>; + }; + }; + + }; + }; + + tmc_etf: tmc@10b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = + <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + }; + }; + + replicator_swao: replicator@10b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x10b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_swao"; + + qcom,replicator-loses-context; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_swao_in_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + }; + }; + + replicator_qdss: replicator@10046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x10046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_qdss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_qdss_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + replicator_qdss_out_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_in_replicator_qdss>; + }; + }; + }; + }; + + replicator_etr: replicator@1004e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb909>; + reg = <0x1004e000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator_etr"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_etr_in_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_out_replicator_etr>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_etr_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_etr>; + }; + }; + + port@1 { + reg = <1>; + replicator_etr_out_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_in_replicator_etr>; + }; + }; + }; + }; + + dummy_replicator { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-replicator-dummy"; + qcom,dummy-link; + + in-ports { + port { + replicator_dummy_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_replicator_dummy>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_dummy_out_tmc_modem: endpoint { + remote-endpoint = + <&tmc_modem_in_replicator_dummy>; + }; + }; + + port@1 { + reg = <1>; + replicator_dummy_out_tmc_etr1: endpoint { + remote-endpoint = + <&tmc_etr1_in_replicator_dummy>; + }; + }; + }; + + }; + + tmc_modem: tmc_modem { + compatible = "qcom,coresight-secure-etr"; + coresight-name = "coresight-modem-etr1"; + + real-name = "coresight-tmc-etr1"; + qdss,support-remote-etm = <2>; + memory-region = <&qdss_mem>; + qdss,buffer-size = <0x2000000>; + + qcom,secure-component; + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_modem_in_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_out_tmc_modem>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x10048000 0x1000>; + reg-names = "tmc-base"; + + qcom,iommu-dma = "bypass"; + iommus = <&apps_smmu 0x04e0 0>, + <&apps_smmu 0x04c0 0>; + + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + qcom,sw-usb; + dma-coherent; + coresight-name = "coresight-tmc-etr"; + + coresight-csr = <&csr>; + csr-atid-offset = <0xf8>; + csr-irqctrl-offset = <0x6c>; + byte-cntr-name = "byte-cntr"; + byte-cntr-class-name = "coresight-tmc-etr-stream"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr_in_replicator_etr: endpoint { + remote-endpoint = + <&replicator_etr_out_tmc_etr>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + reg = <0x1004f000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etr1"; + + iommus = <&apps_smmu 0x0500 0>; + qcom,iommu-dma-addr-pool = <0x0 0xffc00000>; + + coresight-csr = <&csr>; + csr-atid-offset = <0x108>; + csr-irqctrl-offset = <0x70>; + byte-cntr-name = "byte-cntr1"; + byte-cntr-class-name = "coresight-tmc-etr1-stream"; + memory-region = <&qdss_mem>; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + arm,scatter-gather; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etr1_in_replicator_dummy: endpoint { + remote-endpoint = + <&replicator_dummy_out_tmc_etr1>; + }; + }; + }; + }; + + csr: csr@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0x10001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@10b11000 { + compatible = "qcom,coresight-csr"; + reg = <0x10b11000 0x1000>, + <0x10b110f8 0x70>; + reg-names = "csr-base", "msr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + qcom,msr-support; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU0>; + + coresight-name = "coresight-ete0"; + qcom,skip-power-up; + atid = <1>; + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU1>; + + coresight-name = "coresight-ete1"; + qcom,skip-power-up; + atid = <2>; + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete2 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU2>; + + coresight-name = "coresight-ete2"; + qcom,skip-power-up; + atid = <3>; + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete3 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU3>; + + coresight-name = "coresight-ete3"; + qcom,skip-power-up; + atid = <4>; + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete4 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU4>; + + coresight-name = "coresight-ete4"; + qcom,skip-power-up; + atid = <5>; + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete5 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU5>; + + coresight-name = "coresight-ete5"; + qcom,skip-power-up; + atid = <6>; + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete6 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU6>; + + coresight-name = "coresight-ete6"; + qcom,skip-power-up; + atid = <7>; + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete7 { + compatible = "arm,embedded-trace-extension"; + cpu = <&CPU7>; + + coresight-name = "coresight-ete7"; + qcom,skip-power-up; + atid = <8>; + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel_ete { + compatible = "arm,coresight-static-funnel"; + coresight-name = "coresight-funnel-ete"; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_funnel_ete>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ete_in_ete0: endpoint { + remote-endpoint = + <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + funnel_ete_in_ete1: endpoint { + remote-endpoint = + <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + funnel_ete_in_ete2: endpoint { + remote-endpoint = + <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + funnel_ete_in_ete3: endpoint { + remote-endpoint = + <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + funnel_ete_in_ete4: endpoint { + remote-endpoint = + <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + funnel_ete_in_ete5: endpoint { + remote-endpoint = + <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + funnel_ete_in_ete6: endpoint { + remote-endpoint = + <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + funnel_ete_in_ete7: endpoint { + remote-endpoint = + <&ete7_out_funnel_ete>; + }; + }; + }; + }; + + funnel_in1: funnel@10042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x10042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel_in1_in_funnel_dl_center: endpoint { + remote-endpoint = + <&funnel_dl_center_out_funnel_in1>; + }; + }; + + port@0 { + reg = <0>; + funnel_in1_in_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_out_funnel_in1>; + }; + }; + + port@1 { + reg = <1>; + funnel_in1_in_trace_noc: endpoint { + remote-endpoint = + <&trace_noc_out_funnel_in1>; + }; + }; + + port@4 { + reg = <4>; + funnel_in1_in_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_out_funnel_in1>; + }; + }; + + port@5 { + reg = <5>; + funnel_in1_in_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_out_funnel_in1>; + }; + }; + + }; + + out-ports { + port { + funnel_in1_out_funnel_qdss: endpoint { + remote-endpoint = + <&funnel_qdss_in_funnel_in1>; + }; + }; + + }; + }; + + funnel_apss: funnel@13810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0x13810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = + <&funnel_ete_out_funnel_apss>; + }; + }; + + }; + + out-ports { + port { + funnel_apss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss>; + }; + }; + + }; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + }; + + qdss_cti: cti@10010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-qdss_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <16>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti0: cti@10c2a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c2a000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-cti0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + dlmm_cti0: cti@10c09000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c09000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-dlmm_cti0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_0_cti_0: cti@10d02000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d02000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl_1_cti_0: cti@10d08000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d08000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_ch02_dl_cti_0: cti@10d21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_ch02_dl_cti_0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_ch13_dl_cti_0: cti@10d31000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d31000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_ch13_dl_cti_0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddrss_shrm2: cti@10d11000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10d11000 0x1000>; + + status = "disabled"; + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddrss_shrm2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ddr_dl2_lpi: cti@10b31000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b31000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-ddr_dl2_lpi"; + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_dl_cti: cti@10845000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10845000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_dl_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_lpi_cti1: cti@10b41000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b41000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti1"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_lpi_cti3: cti@10b51000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b51000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_lpi_cti3"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_ssc_sdc: cti@10b42000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b42000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_ssc_sdc"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + lpass_q6_cti: cti@10b4b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b4b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-lpass_q6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe0: cti@12010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12010000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe1: cti@12020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12020000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe2: cti@12030000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12030000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe3: cti@12040000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12040000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe3"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe4: cti@12050000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12050000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe4"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe5: cti@12060000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12060000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe5"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe6: cti@12070000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12070000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe6"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_pe7: cti@12080000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12080000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_pe7"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cluster: cti@12230000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x12230000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cluster"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti0: cti@138e0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138e0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti1: cti@138f0000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x138f0000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_cti2: cti@13900000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x13900000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + riscv_cti: cti@1382b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1382b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-riscv_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + riscv_sifive_cti: cti@1382e000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1382e000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-riscv_sifive_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + apss_atb_cti: cti@13863000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x13863000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-apss_atb_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_isdb_cti: cti@10961000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10961000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_cortex_m3: cti@10962000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10962000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_cortex_m3"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + gpu_dl: cti@10901000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10901000 0x1000>; + + status = "disabled"; + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-gpu_dl"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + iris_dl_cti: cti@10831000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10831000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-iris_dl_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mdss_dl_cti: cti@10c61000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c61000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mdss_dl_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_dl_cti_0: cti@10985000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10985000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_dl_cti_0"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + turing_q6_cti: cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1098b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-turing_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + camera_dl: cti@10c15000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10c15000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-camera_dl"; + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + swao_cti: cti@10b00000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b00000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-swao_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + aop_rvss: cti@10b21000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10b21000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-aop_rvss"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_q6_cti: cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x1080b000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + mss_vq6_cti: cti@10813000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10813000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-mss_vq6_cti"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + modem_tp_cti: cti@10802000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10802000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-modem_tp_cti"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_0: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_0"; + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_1: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_1"; + qcom,extended_cti; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_2: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_2"; + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_3: cti@10cc2000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc2000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_3"; + qcom,extended_cti; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cti_4: cti@10cc3000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cc3000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cti_4"; + qcom,extended_cti; + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tmess_cpu: cti@10cd1000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x10cd1000 0x1000>; + + arm,primecell-periphid = <0x000bb922>; + coresight-name = "coresight-cti-tmess_cpu"; + + status = "disabled"; + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@10b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + reg = <0x10b0e000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu0: tgu@10b0f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b0f000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi0"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + spmi_tgu1: tgu@10b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + + reg = <0x10b10000 0x1000>; + reg-names = "tgu-base"; + + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <9>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-spmi1"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; +}; diff --git a/qcom/pineapple-debug.dtsi b/qcom/pineapple-debug.dtsi new file mode 100644 index 00000000..7b272c0d --- /dev/null +++ b/qcom/pineapple-debug.dtsi @@ -0,0 +1,4918 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0 0x1800000>; + }; +}; + +&soc { + dcc: dcc_v2@100ff000 { + compatible = "qcom,dcc-v2"; + reg = <0x100ff000 0x1000>, + <0x10080000 0x18000>; + + qcom,transaction_timeout = <0>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0>; + + link_list_0 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list_1 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb700 { + qcom,dump-size = <0x600>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb700 { + qcom,dump-size = <0xa00>; + qcom,dump-id = <0x47>; + }; + + l2_cache0 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc0>; + }; + + l2_cache100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc1>; + }; + + l2_cache200 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc2>; + }; + + l2_cache300 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc3>; + }; + + l2_cache400 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x340100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x121>; + }; + + l2_tlb700 { + qcom,dump-size = <0xa900>; + qcom,dump-id = <0x127>; + }; + + l1dcdirty0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x170>; + }; + + l1dcdirty100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x171>; + }; + + l1dcmte0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x180>; + }; + + l1dcmte100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x181>; + }; + + l2dcmte0 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x190>; + }; + + l2dcmte100 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x191>; + }; + + l0mopca700 { + qcom,dump-size = <0x4100>; + qcom,dump-id = <0x1a7>; + }; + + l2victim700 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x1e7>; + }; + + l2tldtcsp200 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x202>; + }; + + l2tldtcsp300 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x203>; + }; + + l2tldtcsp400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x204>; + }; + + l2tldtcsp500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x205>; + }; + + l2tldtcsp600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x206>; + }; + + l2tldtcmp200 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x212>; + }; + + l2tldtcmp300 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x213>; + }; + + l2tldtcmp400 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x214>; + }; + + l2tldtcmp500 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x215>; + }; + + l2tldtcmp600 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x216>; + }; + + cpuss_reg { + qcom,dump-size = <0x36000>; + qcom,dump-id = <0xef>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; + }; +}; diff --git a/qcom/pineapple-dma-heaps.dtsi b/qcom/pineapple-dma-heaps.dtsi new file mode 100644 index 00000000..96792535 --- /dev/null +++ b/qcom/pineapple-dma-heaps.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,sp_hlos { + qcom,dma-heap-name = "qcom,sp-hlos"; + qcom,dma-heap-type = ; + memory-region = <&sp_mem>; + }; + + qcom,secure_sp_modem { + qcom,dma-heap-name = "qcom,secure-sp-modem"; + qcom,dma-heap-type = ; + memory-region = <&spu_modem_shared_mem>; + qcom,token = <0x10800000>; + }; + + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,cma-secure-cdsp"; + qcom,dma-heap-type = ; + memory-region = <&cdsp_secure_heap_cma>; + }; + + qcom,secure_sp_tz { + qcom,dma-heap-name = "qcom,secure-sp-tz"; + qcom,dma-heap-type = ; + memory-region = <&spu_tz_shared_mem>; + qcom,token = <0x01000000>; + }; + + }; +}; diff --git a/qcom/pineapple-gdsc.dtsi b/qcom/pineapple-gdsc.dtsi new file mode 100644 index 00000000..23e8c609 --- /dev/null +++ b/qcom/pineapple-gdsc.dtsi @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* CAM_CC GDSCs */ + cam_cc_bps_gdsc: qcom,gdsc@adf0004 { + compatible = "qcom,gdsc"; + reg = <0xadf0004 0x4>; + regulator-name = "cam_cc_bps_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 { + compatible = "qcom,gdsc"; + reg = <0xadf1004 0x4>; + regulator-name = "cam_cc_ife_0_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 { + compatible = "qcom,gdsc"; + reg = <0xadf2004 0x4>; + regulator-name = "cam_cc_ife_1_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_ife_2_gdsc: qcom,gdsc@adf2054 { + compatible = "qcom,gdsc"; + reg = <0xadf2054 0x4>; + regulator-name = "cam_cc_ife_2_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_ipe_0_gdsc: qcom,gdsc@adf0080 { + compatible = "qcom,gdsc"; + reg = <0xadf0080 0x4>; + regulator-name = "cam_cc_ipe_0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_sbi_gdsc: qcom,gdsc@adf00e4 { + compatible = "qcom,gdsc"; + reg = <0xadf00e4 0x4>; + regulator-name = "cam_cc_sbi_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_sfe_0_gdsc: qcom,gdsc@adf3058 { + compatible = "qcom,gdsc"; + reg = <0xadf3058 0x4>; + regulator-name = "cam_cc_sfe_0_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_sfe_1_gdsc: qcom,gdsc@adf30a8 { + compatible = "qcom,gdsc"; + reg = <0xadf30a8 0x4>; + regulator-name = "cam_cc_sfe_1_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_sfe_2_gdsc: qcom,gdsc@adf30f8 { + compatible = "qcom,gdsc"; + reg = <0xadf30f8 0x4>; + regulator-name = "cam_cc_sfe_2_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + cam_cc_titan_top_gdsc: qcom,gdsc@adf32bc { + compatible = "qcom,gdsc"; + reg = <0xadf32bc 0x4>; + regulator-name = "cam_cc_titan_top_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + /* DISP_CC GDSCs */ + disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 { + compatible = "qcom,gdsc"; + reg = <0xaf09000 0x4>; + regulator-name = "disp_cc_mdss_core_gdsc"; + proxy-supply = <&disp_cc_mdss_core_gdsc>; + qcom,proxy-consumer-enable; + qcom,support-hw-trigger; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 { + compatible = "qcom,gdsc"; + reg = <0xaf0b000 0x4>; + regulator-name = "disp_cc_mdss_core_int2_gdsc"; + qcom,support-hw-trigger; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_apcs_gdsc_vote_ctrl: syscon@15214c { + compatible = "syscon"; + reg = <0x15214c 0x4>; + }; + + apss_ubwcp_pwr_ctrl: qcom,gdsc@17891000 { + compatible = "qcom,gdsc"; + reg = <0x17891000 0x4>; + regulator-name = "apss_ubwcp_pwr_ctrl"; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + /* GCC GDSCs */ + gcc_pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "gcc_pcie_0_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 { + compatible = "qcom,gdsc"; + reg = <0x16c000 0x4>; + regulator-name = "gcc_pcie_0_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_pcie_1_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + reg = <0x18d004 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 { + compatible = "qcom,gdsc"; + reg = <0x18e000 0x4>; + regulator-name = "gcc_pcie_1_phy_gdsc"; + qcom,retain-regs; + qcom,no-status-check-on-disable; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 { + compatible = "qcom,gdsc"; + reg = <0x19e000 0x4>; + regulator-name = "gcc_ufs_mem_phy_gdsc"; + proxy-supply = <&gcc_ufs_mem_phy_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "gcc_ufs_phy_gdsc"; + proxy-supply = <&gcc_ufs_phy_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@139004 { + compatible = "qcom,gdsc"; + reg = <0x139004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + proxy-supply = <&gcc_usb30_prim_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gcc_usb3_phy_gdsc: qcom,gdsc@150018 { + compatible = "qcom,gdsc"; + reg = <0x150018 0x4>; + regulator-name = "gcc_usb3_phy_gdsc"; + proxy-supply = <&gcc_usb3_phy_gdsc>; + qcom,proxy-consumer-enable; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + /* GPU_CC GDSCs */ + gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99168 { + compatible = "syscon"; + reg = <0x3d99168 0x4>; + }; + + gpu_cc_cx_gdsc: qcom,gdsc@3d99108 { + compatible = "qcom,gdsc"; + reg = <0x3d99108 0x4>; + regulator-name = "gpu_cc_cx_gdsc"; + hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,clk-dis-wait-val = <8>; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + gpu_cc_gx_domain_addr: syscon@3d99504 { + compatible = "syscon"; + reg = <0x3d99504 0x4>; + }; + + gpu_cc_gx_sw_reset: syscon@3d99058 { + compatible = "syscon"; + reg = <0x3d99058 0x4>; + }; + + gpu_cc_gx_acd_reset: syscon@3d99358 { + compatible = "syscon"; + reg = <0x3d99358 0x4>; + }; + + gpu_cc_gx_acd_iroot_reset: syscon@3d9958c { + compatible = "syscon"; + reg = <0x3d9958c 0x4>; + }; + + gpu_cc_gx_gdsc: qcom,gdsc@3d9905c { + compatible = "qcom,gdsc"; + reg = <0x3d9905c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + domain-addr = <&gpu_cc_gx_domain_addr>; + sw-reset = <&gpu_cc_gx_sw_reset>, + <&gpu_cc_gx_acd_reset>, + <&gpu_cc_gx_acd_iroot_reset>; + qcom,reset-aon-logic; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + /* VIDEO_CC GDSCs */ + video_cc_mvs0_gdsc: qcom,gdsc@aaf80a4 { + compatible = "qcom,gdsc"; + reg = <0xaaf80a4 0x4>; + regulator-name = "video_cc_mvs0_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + video_cc_mvs0c_gdsc: qcom,gdsc@aaf804c { + compatible = "qcom,gdsc"; + reg = <0xaaf804c 0x4>; + regulator-name = "video_cc_mvs0c_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + video_cc_mvs1_gdsc: qcom,gdsc@aaf80cc { + compatible = "qcom,gdsc"; + reg = <0xaaf80cc 0x4>; + regulator-name = "video_cc_mvs1_gdsc"; + qcom,retain-regs; + qcom,support-hw-trigger; + qcom,support-cfg-gdscr; + status = "disabled"; + }; + + video_cc_mvs1c_gdsc: qcom,gdsc@aaf8078 { + compatible = "qcom,gdsc"; + reg = <0xaaf8078 0x4>; + regulator-name = "video_cc_mvs1c_gdsc"; + qcom,retain-regs; + qcom,support-cfg-gdscr; + status = "disabled"; + }; +}; diff --git a/qcom/pineapple-mtp-nfc-overlay.dts b/qcom/pineapple-mtp-nfc-overlay.dts new file mode 100644 index 00000000..5518e5dd --- /dev/null +++ b/qcom/pineapple-mtp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-mtp-nfc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple MTP ST54L NFC"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x50008 0>; +}; diff --git a/qcom/pineapple-mtp-nfc.dtsi b/qcom/pineapple-mtp-nfc.dtsi new file mode 100644 index 00000000..5766f2fe --- /dev/null +++ b/qcom/pineapple-mtp-nfc.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-mtp.dtsi" diff --git a/qcom/pineapple-mtp-overlay.dts b/qcom/pineapple-mtp-overlay.dts new file mode 100644 index 00000000..eac1deec --- /dev/null +++ b/qcom/pineapple-mtp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple MTP"; + compatible = "qcom,pineapple-mtp", "qcom,pineapple", "qcom,pineapplep-mtp", "qcom,pineapplep", "qcom,mtp"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <8 0>; +}; diff --git a/qcom/pineapple-mtp.dtsi b/qcom/pineapple-mtp.dtsi new file mode 100644 index 00000000..11e08837 --- /dev/null +++ b/qcom/pineapple-mtp.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "pineapple-pmic-overlay.dtsi" +#include "pineapple-thermal-overlay.dtsi" + +&sdhc_2 { + status = "ok"; + vdd-supply = <&pm_humu_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm_humu_l8>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>; + pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>; + + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qcom,iommu-dma = "fastmap"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6d_l1>; + vdda-phy-max-microamp = <211000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8_l1>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v6c_l1>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&pm_v6c_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v6c_s1>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; + +&pm8550_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8550_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8550_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8550_flash { + status = "ok"; +}; + +&battery_charger { + qcom,wireless-fw-name = "idt9418.bin"; + qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + #cooling-cells = <2>; +}; + +&pmic_glink_debug { + i2c@107 { + reg = <0x107>; /* I2C instance 7 in ADSP for SE6 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1502@68 { + compatible = "qcom,i2c-pmic"; + reg = <0x68>; + qcom,can-sleep; + }; + + qcom,smb1502@69 { + compatible = "qcom,i2c-pmic"; + reg = <0x69>; + qcom,can-sleep; + }; + + qcom,idt9418@3b { + compatible = "qcom,i2c-pmic"; + reg = <0x3b>; + qcom,can-sleep; + }; + }; +}; + +&pmic_glink_adc { + status = "ok"; + + smb1502_1_iin { + reg = <0x1076801>; + label = "smb1502_1_iin"; + }; + + smb1502_1_ichg { + reg = <0x1076802>; + label = "smb1502_1_ichg"; + }; + + smb1502_1_die_temp { + reg = <0x1076803>; + label = "smb1502_1_die_temp"; + }; + + smb1502_2_iin { + reg = <0x1076901>; + label = "smb1502_2_iin"; + }; + + smb1502_2_ichg { + reg = <0x1076902>; + label = "smb1502_2_ichg"; + }; + + smb1502_2_die_temp { + reg = <0x1076903>; + label = "smb1502_2_die_temp"; + }; +}; + +&eusb2_phy0 { + dummy-supply = <&pm8550b_eusb2_repeater>; + usb-repeater = <&pm8550b_eusb2_repeater>; +}; + +&usb0 { + usb-role-switch; + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; + +&qupv3_se4_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&tlmm>; + interrupts = <162 0x2008>; + goodix,reset-gpio = <&tlmm 161 0x00>; + goodix,irq-gpio = <&tlmm 162 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L14B>; + iovdd-supply = <&L12B>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <598>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0 + &tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>; + }; +}; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1e4-supply = <&BOB1>; + periph-1e6-supply = <&BOB2>; + periph-29b-supply = <&S1C>; + periph-29e-supply = <&S2C>; + periph-2a1-supply = <&S3C>; + periph-2a4-supply = <&S4C>; + periph-2a7-supply = <&S5C>; + periph-2aa-supply = <&S6C>; + periph-2c1-supply = <&L1C>; + periph-2c2-supply = <&L2C>; + periph-2c3-supply = <&L3C>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a4-supply = <&S4D_LEVEL>; + periph-3a7-supply = <&S5D_LEVEL>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D_LEVEL>; + periph-3c3-supply = <&L3D>; + periph-4c2-supply = <&L2E>; + periph-4c3-supply = <&L3E>; + periph-69b-supply = <&S1G_LEVEL>; + periph-6a1-supply = <&S3G>; + periph-6a4-supply = <&S4G_LEVEL>; + periph-6a7-supply = <&S5G_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-89b-supply = <&S1I_LEVEL>; + periph-8a1-supply = <&S3I_LEVEL>; + periph-8a4-supply = <&S4I>; + periph-8a7-supply = <&S5I>; + periph-8aa-supply = <&S6I_LEVEL>; + periph-8b0-supply = <&S8I_LEVEL>; + periph-8c1-supply = <&L1I>; + periph-8c2-supply = <&L2I>; + periph-8c3-supply = <&L3I>; + periph-ac1-supply = <&L1K>; + periph-ac2-supply = <&L2K>; + periph-ac3-supply = <&L3K>; + periph-ac4-supply = <&L4K>; + periph-ac5-supply = <&L5K>; + periph-ac6-supply = <&L6K>; + periph-ac7-supply = <&L7K>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/pineapple-pcie.dtsi b/qcom/pineapple-pcie.dtsi new file mode 100644 index 00000000..76e8f6b8 --- /dev/null +++ b/qcom/pineapple-pcie.dtsi @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x01D07000 0x7000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", + "pcie_sm"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + + interrupts = ; + + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */ + + qcom,pcie-clkreq-gpio = <95>; + perst-gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0 + &mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>; + + gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>; + clocks = <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "gcc_cnoc_pcie_sf_axi_clk"; + clock-frequency = <0>; + clock-suppressible = <1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1400>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,drv-supported; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,slv-addr-space-size = <0x4000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + qcom,pcie-phy-ver = <104>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x62 0x0 + 0x00d0 0x02 0x0 + 0x0060 0xf8 0x0 + 0x0064 0x01 0x0 + 0x0000 0x93 0x0 + 0x0004 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0a 0x0 + 0x0120 0x42 0x0 + 0x0080 0x04 0x0 + 0x0084 0x0d 0x0 + 0x0020 0x0a 0x0 + 0x0024 0x1a 0x0 + 0x0088 0x41 0x0 + 0x0028 0x34 0x0 + 0x0090 0xab 0x0 + 0x0094 0xaa 0x0 + 0x0098 0x01 0x0 + 0x0030 0x55 0x0 + 0x0034 0x55 0x0 + 0x0038 0x01 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x1600 0x00 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x09 0x0 + 0x0e3c 0x15 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x09 0x0 + 0x163c 0x15 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x06f4 0x27 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500 + 0x04d0 0x04d4 0x03c0 0x0630 0x0230 + 0x0000>; + qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730 + 0x0734 0x0738 0x073c>; + qcom,phy-debug-reg = <0x01cc 0x01d0 0x01d4 0x01d8 0x01dc + 0x01e0 0x01e4 0x01f8 0x0ed0 0x16d0 + 0x0edc 0x16dc 0x11e0 0x19e0 0x0a00 + 0x1200 0x0a04 0x1204 0x0a08 0x1208 + 0x0a0c 0x120c 0x0a10 0x1210 0x0a14 + 0x1214 0x0a18 0x1218 0x0c20 0x1420 + 0x0214 0x0218 0x021c 0x0220 0x0224 + 0x0228 0x022c 0x0230 0x0234 0x0238 + 0x023c 0x0600 0x0604>; + + qcom,pcie-sm-branch-offset = <0x1000>; + qcom,pcie-sm-start-offset = <0x1090>; + + qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>, + <0x28007003>, <0x80804002>, <0x70021c01>, + <0x18001802>, <0x70005000>, <0x10004000>, + <0x80814002>, <0x18001c01>, <0x1c018080>, + <0x0000100>; + + qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>, + <0x0>, <0x0>; + + qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */ + <0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */ + <0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */ + <0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */ + <0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */ + <0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */ + <0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */ + <0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */ + <0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */ + <0x1088>, /* PCIE_SMs_SEQ_PC_VAL */ + <0x1090>, /* PCIE_SMs_SEQ_START */ + <0x1094>, /* PCIE_SMs_CLKREQ_GATE */ + <0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */ + <0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */ + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@0x17110040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17110040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + msi-map = <0x0 &gic_its 0x1480 0x1>, + <0x100 &gic_its 0x1481 0x1>; /* 32 event IDs */ + + perst-gpio = <&tlmm 97 0>; + wake-gpio = <&tlmm 99 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>; + vreg-1p2-supply = <&pm_v8_l3>; + vreg-0p9-supply = <&pm_v6e_l3>; + vreg-qref-supply = <&pm_v8_l1>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>; + qcom,vreg-0p9-voltage-level = <912000 880000 193000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,vreg-qref-voltage-level = <880000 880000 25700>; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&tcsrcc TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie_1_pipe_clk>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_rate_change_clk", + "gcc_ddrss_pcie_sf_qtb_clk", + "pcie_aggre_noc_axi_clk", + "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk"; + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, + <0>, <100000000>, <0>, <0>, <0>, <0>, <0>, <0>; + + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <1>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset", + "pcie_1_link_down_reset", + "pcie_1_phy_nocsr_com_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x1480>; + iommu-map = <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <17>; /* 16.6 MHz */ + qcom,drv-name = "lpass"; + qcom,drv-l1ss-timeout-us = <5000>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,slv-addr-space-size = <0x20000000>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + + qcom,pcie-clkreq-offset = <0x2c48>; + + qcom,pcie-phy-ver = <106>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x0030 0x1d 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x0d 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0x14 0x0 + 0x03f8 0xb3 0x0 + 0x03fc 0x58 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x26 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xdb 0x0 + 0x0414 0xdb 0x0 + 0x0418 0xa0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x0830 0x1d 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x0d 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0x14 0x0 + 0x0bf8 0xb3 0x0 + 0x0bfc 0x58 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x26 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xdb 0x0 + 0x0c14 0xdb 0x0 + 0x0c18 0xa0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x00 0x0 + 0x0ec8 0x1f 0x0 + 0x0ed4 0x12 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x38 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1000 0x26 0x0 + 0x1004 0x03 0x0 + 0x1010 0x06 0x0 + 0x1014 0x16 0x0 + 0x1018 0x36 0x0 + 0x101c 0x04 0x0 + 0x1020 0x0a 0x0 + 0x1024 0x1a 0x0 + 0x1028 0x68 0x0 + 0x1030 0xab 0x0 + 0x1034 0xaa 0x0 + 0x1038 0x02 0x0 + 0x103c 0x12 0x0 + 0x1060 0xf8 0x0 + 0x1064 0x01 0x0 + 0x1070 0x06 0x0 + 0x1074 0x16 0x0 + 0x1078 0x36 0x0 + 0x107c 0x0a 0x0 + 0x1080 0x04 0x0 + 0x1084 0x0d 0x0 + 0x1088 0x41 0x0 + 0x1090 0xab 0x0 + 0x1094 0xaa 0x0 + 0x1098 0x01 0x0 + 0x109c 0x00 0x0 + 0x10bc 0x0a 0x0 + 0x10c0 0x01 0x0 + 0x10cc 0x62 0x0 + 0x10d0 0x02 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e0 0x90 0x0 + 0x10e4 0x82 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x08 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1164 0x34 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x129c 0x87 0x0 + 0x12a0 0x05 0x0 + 0x12a4 0xa1 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x141c 0xc1 0x0 + 0x1450 0x0f 0x0 + 0x1490 0x00 0x0 + 0x14a0 0x16 0x0 + 0x14f0 0x27 0x0 + 0x14f4 0x27 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x140c 0x1d 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1370 0x17 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500 + 0x04d0 0x04d4 0x03c0 0x0630 0x0230 + 0x0000>; + qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730 + 0x0734 0x0738 0x073c>; + qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc + 0x11e0 0x11e4 0x11f8 0x00b8 0x08b8 + 0x00c4 0x08c4 0x0464 0x0c64 0x1800 + 0x1c00 0x1804 0x1c04 0x1808 0x1c08 + 0x180c 0x1c0c 0x1810 0x1c10 0x1814 + 0x1c14 0x1818 0x1c18 0x1a20 0x1e20 + 0x1214 0x1218 0x121c 0x1220 0x1224 + 0x1228 0x122c 0x1230 0x1234 0x1238 + 0x123c 0x1400 0x1404>; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; +}; diff --git a/qcom/pineapple-pinctrl.dtsi b/qcom/pineapple-pinctrl.dtsi new file mode 100644 index 00000000..67ccadf1 --- /dev/null +++ b/qcom/pineapple-pinctrl.dtsi @@ -0,0 +1,3494 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + qupv3_se15_2uart_pins: qupv3_se15_2uart_pins { + qupv3_se15_2uart_tx_active: qupv3_se15_2uart_tx_active { + mux { + pins = "gpio30"; + function = "qup2_se7_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_2uart_rx_active: qupv3_se15_2uart_rx_active { + mux { + pins = "gpio31"; + function = "qup2_se7_l3"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_2uart_sleep: qupv3_se15_2uart_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio78"; + function = "qdss_cti"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio94"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio95"; + function = "pcie0_clk_req_n"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio98"; + function = "pcie1_clk_req_n"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_4uart_pins: qupv3_se14_4uart_pins { + qupv3_se14_default_cts: qupv3_se14_default_cts { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_default_rts: qupv3_se14_default_rts { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_default_tx: qupv3_se14_default_tx { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_default_rx: qupv3_se14_default_rx { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_cts: qupv3_se14_cts { + mux { + pins = "gpio24"; + function = "qup2_se6_l0"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_rts: qupv3_se14_rts { + mux { + pins = "gpio25"; + function = "qup2_se6_l1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se14_tx: qupv3_se14_tx { + mux { + pins = "gpio26"; + function = "qup2_se6_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se14_rx: qupv3_se14_rx { + mux { + pins = "gpio27"; + function = "qup2_se6_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio32"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio33"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_i3c_pins: qupv3_se0_i3c_pins { + qupv3_se0_i3c_sda_active: qupv3_se0_i3c_sda_active { + mux { + pins = "gpio32"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_scl_active: qupv3_se0_i3c_scl_active { + mux { + pins = "gpio33"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_sda_sleep: qupv3_se0_i3c_sda_sleep { + mux { + pins = "gpio32"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio32"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_scl_sleep: qupv3_se0_i3c_scl_sleep { + mux { + pins = "gpio33"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio33"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se0_i3c_disable: qupv3_se0_i3c_disable { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio32"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio33"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio36"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio37"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio36"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio37"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio38"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio38"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio39"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio39"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio40"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio41"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio41"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio40", "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio40"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio41"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio42"; + function = "qup1_se2_l2"; + }; + + config { + pins = "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio43"; + function = "qup1_se2_l3"; + }; + + config { + pins = "gpio43"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio46"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio47"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio49"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se4_i3c_pins: qupv3_se4_i3c_pins { + qupv3_se4_i3c_sda_active: qupv3_se4_i3c_sda_active { + mux { + pins = "gpio48"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio48"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_scl_active: qupv3_se4_i3c_scl_active { + mux { + pins = "gpio49"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio49"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_sda_sleep: qupv3_se4_i3c_sda_sleep { + mux { + pins = "gpio48"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio48"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_scl_sleep: qupv3_se4_i3c_scl_sleep { + mux { + pins = "gpio49"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio49"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se4_i3c_disable: qupv3_se4_i3c_disable { + mux { + pins = "gpio48", "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { + mux { + pins = "gpio48"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio48"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { + mux { + pins = "gpio49"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio49"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active { + mux { + pins = "gpio50"; + function = "qup1_se4_l2"; + }; + + config { + pins = "gpio50"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active { + mux { + pins = "gpio51"; + function = "qup1_se4_l3"; + }; + + config { + pins = "gpio51"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup1_se5_l2"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup1_se5_l3"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio56"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio57"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio56"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio57"; + function = "qup1_se6_l1"; + }; + + config { + pins = "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio58"; + function = "qup1_se6_l2"; + }; + + config { + pins = "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio59"; + function = "qup1_se6_l3"; + }; + + config { + pins = "gpio59"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio60"; + function = "qup1_se7_l0"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio61"; + function = "qup1_se7_l1"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio60", "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio60"; + function = "qup1_se7_l0"; + }; + + config { + pins = "gpio60"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio61"; + function = "qup1_se7_l1"; + }; + + config { + pins = "gpio61"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio62"; + function = "qup1_se7_l2"; + }; + + config { + pins = "gpio62"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio63"; + function = "qup1_se7_l3"; + }; + + config { + pins = "gpio63"; + drive-strength = <6>; + bias-pull-down; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup2_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup2_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i3c_pins: qupv3_se8_i3c_pins { + qupv3_se8_i3c_sda_active: qupv3_se8_i3c_sda_active { + mux { + pins = "gpio0"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio0"; + drive-strength = <16>; + bias-pull-up; + qcom,apps; + }; + }; + + qupv3_se8_i3c_scl_active: qupv3_se8_i3c_scl_active { + mux { + pins = "gpio1"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio1"; + drive-strength = <16>; + bias-pull-up; + qcom,apps; + }; + }; + + qupv3_se8_i3c_sda_sleep: qupv3_se8_i3c_sda_sleep { + mux { + pins = "gpio0"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio0"; + drive-strength = <16>; + bias-pull-up; + qcom,remote; + }; + }; + + qupv3_se8_i3c_scl_sleep: qupv3_se8_i3c_scl_sleep { + mux { + pins = "gpio1"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio1"; + drive-strength = <16>; + bias-pull-up; + qcom,remote; + }; + }; + + qupv3_se8_i3c_disable: qupv3_se8_i3c_disable { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + qcom,apps; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + qcom,apps; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + qcom,remote; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup2_se1_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup2_se1_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup2_se2_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup2_se2_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_i3c_pins: qupv3_se10_i3c_pins { + qupv3_se10_i3c_sda_active: qupv3_se10_i3c_sda_active { + mux { + pins = "gpio8"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio8"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_scl_active: qupv3_se10_i3c_scl_active { + mux { + pins = "gpio9"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio9"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_sda_sleep: qupv3_se10_i3c_sda_sleep { + mux { + pins = "gpio8"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio8"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_scl_sleep: qupv3_se10_i3c_scl_sleep { + mux { + pins = "gpio9"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio9"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se10_i3c_disable: qupv3_se10_i3c_disable { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active { + mux { + pins = "gpio12"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active { + mux { + pins = "gpio13"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active { + mux { + pins = "gpio12"; + function = "qup2_se3_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active { + mux { + pins = "gpio13"; + function = "qup2_se3_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active { + mux { + pins = "gpio14"; + function = "qup2_se3_l2"; + }; + + config { + pins = "gpio14"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active { + mux { + pins = "gpio15"; + function = "qup2_se3_l3"; + }; + + config { + pins = "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i3c_pins: qupv3_se11_i3c_pins { + qupv3_se11_i3c_sda_active: qupv3_se11_i3c_sda_active { + mux { + pins = "gpio12"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_scl_active: qupv3_se11_i3c_scl_active { + mux { + pins = "gpio13"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio13"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_sda_sleep: qupv3_se11_i3c_sda_sleep { + mux { + pins = "gpio12"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_scl_sleep: qupv3_se11_i3c_scl_sleep { + mux { + pins = "gpio13"; + function = "ibi_i3c"; + }; + + config { + pins = "gpio13"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qupv3_se11_i3c_disable: qupv3_se11_i3c_disable { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active { + mux { + pins = "gpio16"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active { + mux { + pins = "gpio17"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active { + mux { + pins = "gpio16"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active { + mux { + pins = "gpio17"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active { + mux { + pins = "gpio18"; + function = "qup2_se4_l2"; + }; + + config { + pins = "gpio18"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active { + mux { + pins = "gpio19"; + function = "qup2_se4_l3"; + }; + + config { + pins = "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_sda_active: qupv3_se13_i2c_sda_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_scl_active: qupv3_se13_i2c_scl_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_miso_active: qupv3_se13_spi_miso_active { + mux { + pins = "gpio20"; + function = "qup2_se5_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_mosi_active: qupv3_se13_spi_mosi_active { + mux { + pins = "gpio21"; + function = "qup2_se5_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_clk_active: qupv3_se13_spi_clk_active { + mux { + pins = "gpio22"; + function = "qup2_se5_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_cs_active: qupv3_se13_spi_cs_active { + mux { + pins = "gpio23"; + function = "qup2_se5_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_hub_i2c0_pins: qupv3_hub_i2c0_pins { + qupv3_hub_i2c0_sda_active: qupv3_hub_i2c0_sda_active { + mux { + pins = "gpio64"; + function = "i2chub0_se0_l0"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c0_scl_active: qupv3_hub_i2c0_scl_active { + mux { + pins = "gpio65"; + function = "i2chub0_se0_l1"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c0_sleep: qupv3_hub_i2c0_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c1_pins: qupv3_hub_i2c1_pins { + qupv3_hub_i2c1_sda_active: qupv3_hub_i2c1_sda_active { + mux { + pins = "gpio66"; + function = "i2chub0_se1_l0"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c1_scl_active: qupv3_hub_i2c1_scl_active { + mux { + pins = "gpio67"; + function = "i2chub0_se1_l1"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c1_sleep: qupv3_hub_i2c1_sleep { + mux { + pins = "gpio66", "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio66", "gpio67"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c2_pins: qupv3_hub_i2c2_pins { + qupv3_hub_i2c2_sda_active: qupv3_hub_i2c2_sda_active { + mux { + pins = "gpio68"; + function = "i2chub0_se2_l0"; + }; + + config { + pins = "gpio68"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c2_scl_active: qupv3_hub_i2c2_scl_active { + mux { + pins = "gpio69"; + function = "i2chub0_se2_l1"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c2_sleep: qupv3_hub_i2c2_sleep { + mux { + pins = "gpio68", "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio68", "gpio69"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c3_pins: qupv3_hub_i2c3_pins { + qupv3_hub_i2c3_sda_active: qupv3_hub_i2c3_sda_active { + mux { + pins = "gpio70"; + function = "i2chub0_se3_l0"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c3_scl_active: qupv3_hub_i2c3_scl_active { + mux { + pins = "gpio71"; + function = "i2chub0_se3_l1"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c3_sleep: qupv3_hub_i2c3_sleep { + mux { + pins = "gpio70", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio70", "gpio71"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c4_pins: qupv3_hub_i2c4_pins { + qupv3_hub_i2c4_sda_active: qupv3_hub_i2c4_sda_active { + mux { + pins = "gpio72"; + function = "i2chub0_se4_l0"; + }; + + config { + pins = "gpio72"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c4_scl_active: qupv3_hub_i2c4_scl_active { + mux { + pins = "gpio73"; + function = "i2chub0_se4_l1"; + }; + + config { + pins = "gpio73"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c4_sleep: qupv3_hub_i2c4_sleep { + mux { + pins = "gpio72", "gpio73"; + function = "gpio"; + }; + + config { + pins = "gpio72", "gpio73"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c5_pins: qupv3_hub_i2c5_pins { + qupv3_hub_i2c5_sda_active: qupv3_hub_i2c5_sda_active { + mux { + pins = "gpio74"; + function = "i2chub0_se5_l0"; + }; + + config { + pins = "gpio74"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c5_scl_active: qupv3_hub_i2c5_scl_active { + mux { + pins = "gpio75"; + function = "i2chub0_se5_l1"; + }; + + config { + pins = "gpio75"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c5_sleep: qupv3_hub_i2c5_sleep { + mux { + pins = "gpio74", "gpio75"; + function = "gpio"; + }; + + config { + pins = "gpio74", "gpio75"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c6_pins: qupv3_hub_i2c6_pins { + qupv3_hub_i2c6_sda_active: qupv3_hub_i2c6_sda_active { + mux { + pins = "gpio76"; + function = "i2chub0_se6_l0"; + }; + + config { + pins = "gpio76"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c6_scl_active: qupv3_hub_i2c6_scl_active { + mux { + pins = "gpio77"; + function = "i2chub0_se6_l1"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c6_sleep: qupv3_hub_i2c6_sleep { + mux { + pins = "gpio76", "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio76", "gpio77"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c7_pins: qupv3_hub_i2c7_pins { + qupv3_hub_i2c7_sda_active: qupv3_hub_i2c7_sda_active { + mux { + pins = "gpio78"; + function = "i2chub0_se7_l0"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c7_scl_active: qupv3_hub_i2c7_scl_active { + mux { + pins = "gpio79"; + function = "i2chub0_se7_l1"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c7_sleep: qupv3_hub_i2c7_sleep { + mux { + pins = "gpio78", "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio78", "gpio79"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + qupv3_hub_i2c8_pins: qupv3_hub_i2c8_pins { + qupv3_hub_i2c8_sda_active: qupv3_hub_i2c8_sda_active { + mux { + pins = "gpio206"; + function = "i2chub0_se8_l0"; + }; + + config { + pins = "gpio206"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_hub_i2c8_scl_active: qupv3_hub_i2c8_scl_active { + mux { + pins = "gpio207"; + function = "i2chub0_se8_l1"; + }; + + config { + pins = "gpio207"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_hub_i2c8_sleep: qupv3_hub_i2c8_sleep { + mux { + pins = "gpio206", "gpio207"; + function = "gpio"; + }; + + config { + pins = "gpio206", "gpio207"; + drive-strength = <2>; + }; + }; + }; + + qupv3_hub_i2c9_pins: qupv3_hub_i2c9_pins { + qupv3_hub_i2c9_sda_active: qupv3_hub_i2c9_sda_active { + mux { + pins = "gpio80"; + function = "i2chub0_se9_l0"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c9_scl_active: qupv3_hub_i2c9_scl_active { + mux { + pins = "gpio81"; + function = "i2chub0_se9_l1"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_hub_i2c9_sleep: qupv3_hub_i2c9_sleep { + mux { + pins = "gpio80", "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81"; + drive-strength = <2>; + //bias-disable; - Has strong PU + }; + }; + }; + + aux0_pcm_clk { + aux0_pcm_clk_sleep: aux0_pcm_clk_sleep { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux0_pcm_clk_active: aux0_pcm_clk_active { + mux { + pins = "gpio126"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + aux0_pcm_ws { + aux0_pcm_ws_sleep: aux0_pcm_ws_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux0_pcm_ws_active: aux0_pcm_ws_active { + mux { + pins = "gpio129"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + aux0_pcm_din { + aux0_pcm_din_sleep: aux0_pcm_din_sleep { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux0_pcm_din_active: aux0_pcm_din_active { + mux { + pins = "gpio127"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + aux0_pcm_dout { + aux0_pcm_dout_sleep: aux0_pcm_dout_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux0_pcm_dout_active: aux0_pcm_dout_active { + mux { + pins = "gpio128"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + aux1_pcm_clk { + aux1_pcm_clk_sleep: aux1_pcm_clk_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux1_pcm_clk_active: aux1_pcm_clk_active { + mux { + pins = "gpio121"; + function = "i2s1_sck"; + }; + + config { + pins = "gpio121"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + aux1_pcm_ws { + aux1_pcm_ws_sleep: aux1_pcm_ws_sleep { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux1_pcm_ws_active: aux1_pcm_ws_active { + mux { + pins = "gpio123"; + function = "i2s1_ws"; + }; + + config { + pins = "gpio123"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + aux1_pcm_din { + aux1_pcm_din_sleep: aux1_pcm_din_sleep { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux1_pcm_din_active: aux1_pcm_din_active { + mux { + pins = "gpio122"; + function = "i2s1_data0"; + }; + + config { + pins = "gpio122"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + aux1_pcm_dout { + aux1_pcm_dout_sleep: aux1_pcm_dout_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + aux1_pcm_dout_active: aux1_pcm_dout_active { + mux { + pins = "gpio124"; + function = "i2s1_data1"; + }; + + config { + pins = "gpio124"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tdm0_clk { + tdm0_clk_sleep: tdm0_clk_sleep { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm0_clk_active: tdm0_clk_active { + mux { + pins = "gpio126"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tdm0_ws { + tdm0_ws_sleep: tdm0_ws_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm0_ws_active: tdm0_ws_active { + mux { + pins = "gpio129"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tdm0_din { + tdm0_din_sleep: tdm0_din_sleep { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm0_din_active: tdm0_din_active { + mux { + pins = "gpio127"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tdm0_dout { + tdm0_dout_sleep: tdm0_dout_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm0_dout_active: tdm0_dout_active { + mux { + pins = "gpio128"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tdm1_clk { + tdm1_clk_sleep: tdm1_clk_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm1_clk_active: tdm1_clk_active { + mux { + pins = "gpio121"; + function = "i2s1_sck"; + }; + + config { + pins = "gpio121"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tdm1_ws { + tdm1_ws_sleep: tdm1_ws_sleep { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm1_ws_active: tdm1_ws_active { + mux { + pins = "gpio123"; + function = "i2s1_ws"; + }; + + config { + pins = "gpio123"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tdm1_din { + tdm1_din_sleep: tdm1_din_sleep { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm1_din_active: tdm1_din_active { + mux { + pins = "gpio122"; + function = "i2s1_data0"; + }; + + config { + pins = "gpio122"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tdm1_dout { + tdm1_dout_sleep: tdm1_dout_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tdm1_dout_active: tdm1_dout_active { + mux { + pins = "gpio124"; + function = "i2s1_data1"; + }; + + config { + pins = "gpio124"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + i2s0_sck { + i2s0_sck_sleep: i2s0_sck_sleep { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sck_active: i2s0_sck_active { + mux { + pins = "gpio126"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_ws { + i2s0_ws_sleep: i2s0_ws_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_ws_active: i2s0_ws_active { + mux { + pins = "gpio129"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_sd0 { + i2s0_sd0_sleep: i2s0_sd0_sleep { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sd0_active: i2s0_sd0_active { + mux { + pins = "gpio127"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_sd1 { + i2s0_sd1_sleep: i2s0_sd1_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sd1_active: i2s0_sd1_active { + mux { + pins = "gpio128"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s1_sck { + i2s1_sck_sleep: i2s1_sck_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s1_sck_active: i2s1_sck_active { + mux { + pins = "gpio121"; + function = "i2s1_sck"; + }; + + config { + pins = "gpio121"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + i2s1_ws { + i2s1_ws_sleep: i2s1_ws_sleep { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s1_ws_active: i2s1_ws_active { + mux { + pins = "gpio123"; + function = "i2s1_ws"; + }; + + config { + pins = "gpio123"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + i2s1_sd0 { + i2s1_sd0_sleep: i2s1_sd0_sleep { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s1_sd0_active: i2s1_sd0_active { + mux { + pins = "gpio122"; + function = "i2s1_data0"; + }; + + config { + pins = "gpio122"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + i2s1_sd1 { + i2s1_sd1_sleep: i2s1_sd1_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s1_sd1_active: i2s1_sd1_active { + mux { + pins = "gpio124"; + function = "i2s1_data1"; + }; + + config { + pins = "gpio124"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + /* WCD reset pin */ + wcd939x_reset_active: wcd939x_reset_active { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <16>; + output-high; + }; + }; + + wcd939x_reset_sleep: wcd939x_reset_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + /* WSA speaker reset pins (south), north reset gpio in LPI LPASS */ + spkr_13_sd_n { + spkr_13_sd_n_sleep: spkr_13_sd_n_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_13_sd_n_active: spkr_13_sd_n_active { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + usb_phy_ps: usb_phy_ps { + usb3phy_portselect_default: usb3phy_portselect_default { + mux { + pins = "gpio29"; + function = "usb_phy"; + }; + + config { + pins = "gpio29"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + usb3phy_portselect_gpio: usb3phy_portselect_gpio { + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + /* touchscreen pins */ + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio161", "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio161", "gpio162"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio161"; + function = "gpio"; + }; + + config { + pins = "gpio161"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio162"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio161", "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio161", "gpio162"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; diff --git a/qcom/pineapple-pmic-overlay.dtsi b/qcom/pineapple-pmic-overlay.dtsi new file mode 100644 index 00000000..e57c2657 --- /dev/null +++ b/qcom/pineapple-pmic-overlay.dtsi @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +&pm8550_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + + sd_card_det { + sd_card_det_default: sd_card_det_default { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; + }; +}; + +&pm8550_tz { + io-channels = <&pmk8550_vadc PM8550_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550b_tz { + io-channels = <&pmk8550_vadc PM8550B_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550b_lite_tz { + io-channels = <&pmk8550_vadc PM8550B_ADC5_GEN3_TEMP_ALARM_LITE>; + io-channel-names = "thermal"; +}; + +&pm8550vs_c_tz { + io-channels = <&pmk8550_vadc PM8550VS_C_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550vs_d_tz { + io-channels = <&pmk8550_vadc PM8550VS_D_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550vs_e_tz { + io-channels = <&pmk8550_vadc PM8550VS_E_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550vs_g_tz { + io-channels = <&pmk8550_vadc PM8550VS_G_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pm8550ve_tz { + io-channels = <&pmk8550_vadc PM8550VE_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + pmk8550_xo_therm { + reg = ; + label = "pmk8550_xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550_msm_therm { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550_cam_flash_therm { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550_wlan_therm { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550_pa_therm1 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550_rear_tof_therm { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550b_usb_therm { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550b_wls_therm { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,pre-scaling = <1 1>; + qcom,adc-tm-type = <1>; + }; + + pm8550b_chg_temp { + reg = ; + label = "pm8550b_chg_temp"; + }; + + pm8550b_iin_fb { + reg = ; + label = "pm8550b_iin_fb"; + }; + + pm8550b_ichg_fb { + reg = ; + label = "pm8550b_ichg_fb"; + }; +}; + +&pmk8550_gpios { + pinctrl-0 = <&alt_sleep_clk_default>; + pinctrl-names = "default"; + + alt_sleep_clk { + alt_sleep_clk_default: alt_sleep_clk_default { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&thermal_zones { + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM2_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM3_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM4_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550_ADC5_GEN3_AMUX_THM5_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + xo_config0: xo-config0 { + temperature = <78000>; + hysteresis = <8000>; + type = "passive"; + }; + + xo_config1: xo-config1 { + temperature = <80000>; + hysteresis = <10000>; + type = "passive"; + }; + + display_test_config1: display-test-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config2: display-test-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config3: display-test-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config4: display-test-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&pm_humu_l15>; + vdd3-supply = <&pm_humu_l5>; +}; + +&soc { + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; + + DBO3: regulator-dbo3 { + compatible = "qti-regulator-fixed"; + regulator-name = "dbo3"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + gpio = <&pm8550_gpios 9 GPIO_ACTIVE_HIGH>; + regulator-enable-ramp-delay = <1500>; + enable-active-high; + }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>; + nvmem-names = "pon_log0", "pon_log1"; + }; + + regulator_ocp_notifier: regulator-ocp-notifier { + compatible = "qcom,regulator-ocp-notifier"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0x71 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x85 0x1 IRQ_TYPE_EDGE_RISING>; + nvmem-cells = <&ocp_log>, <&alarm_log>; + nvmem-cell-names = "ocp_log", "alarm_log"; + }; +}; diff --git a/qcom/pineapple-qrd-overlay.dts b/qcom/pineapple-qrd-overlay.dts new file mode 100644 index 00000000..37162fab --- /dev/null +++ b/qcom/pineapple-qrd-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple QRD"; + compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,pineapplep-qrd", "qcom,pineapplep", "qcom,qrd"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x1000B 0>, <0xB 0>; +}; diff --git a/qcom/pineapple-qrd-sku2-overlay.dts b/qcom/pineapple-qrd-sku2-overlay.dts new file mode 100644 index 00000000..fac2243f --- /dev/null +++ b/qcom/pineapple-qrd-sku2-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple QRD"; + compatible = "qcom,pineapple-qrd", "qcom,pineapple", "qcom,pineapplep-qrd", "qcom,pineapplep", "qcom,qrd"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x5000B 0>; +}; diff --git a/qcom/pineapple-qrd.dtsi b/qcom/pineapple-qrd.dtsi new file mode 100644 index 00000000..fda4b756 --- /dev/null +++ b/qcom/pineapple-qrd.dtsi @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include "pineapple-pmic-overlay.dtsi" +#include "pineapple-thermal-overlay.dtsi" + +&sdhc_2 { + status = "ok"; + vdd-supply = <&pm_humu_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm_humu_l8>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>, <&sd_card_det_default>; + pinctrl-1 = <&sdc2_off>, <&sd_card_det_default>; + + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qcom,iommu-dma = "fastmap"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6d_l1>; + vdda-phy-max-microamp = <211000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8_l1>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v6c_l1>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&pm_v6c_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v6c_s1>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; + +&pm8550_switch0 { + qcom,led-mask = <9>; /* Channels 1 & 4 */ + qcom,symmetry-en; +}; + +&pm8550_switch1 { + qcom,led-mask = <6>; /* Channels 2 & 3 */ + qcom,symmetry-en; +}; + +&pm8550_switch2 { + qcom,led-mask = <15>; /* All Channels */ + qcom,symmetry-en; +}; + +&pm8550_flash { + status = "ok"; +}; + +&pmic_glink_debug { + i2c@107 { + reg = <0x107>; /* I2C instance 7 in ADSP for SE6 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1396@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + qcom,can-sleep; + }; + + qcom,smb1396@35 { + compatible = "qcom,i2c-pmic"; + reg = <0x35>; + qcom,can-sleep; + }; + + qcom,idt9418@3b { + compatible = "qcom,i2c-pmic"; + reg = <0x3b>; + qcom,can-sleep; + }; + }; + + /* SPMI bridge bus 0 with SMB1510 device */ + spmi@200 { + reg = <0x200>; + #address-cells = <2>; + #size-cells = <0>; + qcom,bus-type = "spmi"; + + qcom,smb1510@d { + compatible = "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + qcom,can-sleep; + }; + }; +}; + +&pmic_glink_adc { + status = "ok"; + + smb1396_1_iin { + reg = <0x1073401>; + label = "smb1396_1_iin"; + }; + + smb1396_1_ichg { + reg = <0x1073402>; + label = "smb1396_1_ichg"; + }; + + smb1396_1_die_temp { + reg = <0x1073403>; + label = "smb1396_1_die_temp"; + }; + + smb1396_2_iin { + reg = <0x1073501>; + label = "smb1396_2_iin"; + }; + + smb1396_2_ichg { + reg = <0x1073502>; + label = "smb1396_2_ichg"; + }; + + smb1396_2_die_temp { + reg = <0x1073503>; + label = "smb1396_2_die_temp"; + }; +}; + +&qupv3_se4_spi { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + + goodix,avdd-name = "avdd"; + avdd-supply = <&L14B>; + + interrupt-parent = <&tlmm>; + interrupts = <162 0x2008>; + goodix,reset-gpio = <&tlmm 161 0x00>; + goodix,irq-gpio = <&tlmm 162 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <598>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 48 0 &tlmm 49 0 &tlmm 50 0 + &tlmm 51 0 &tlmm 161 0 &tlmm 162 0x2008>; + }; +}; + +&pm8550b_haptics { + qcom,vmax-mv = <1700>; + qcom,lra-period-us = <5880>; + + effect_0 { + /* CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_1 { + /* DOUBLE_CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_2 { + /* TICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_3 { + /* THUD */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_4 { + /* POP */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + effect_5 { + /* HEAVY CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_0 { + /* NOOP */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_1 { + /* CLICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_2 { + /* THUD */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_3 { + /* SPIN */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_4 { + /* QUICK_RISE */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_5 { + /* SLOW_RISE */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_6 { + /* QUICK_FALL */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_7 { + /* LIGHT_TICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; + + primitive_8 { + /* LOW_TICK */ + qcom,wf-vmax-mv = <1800>; + qcom,wf-pattern-period-us = <5880>; + }; +}; + +&battery_charger { + qcom,wireless-fw-name = "idt9418.bin"; + qcom,thermal-mitigation-step = <500000>; + #cooling-cells = <2>; +}; + +&eusb2_phy0 { + dummy-supply = <&pm8550b_eusb2_repeater>; + usb-repeater = <&pm8550b_eusb2_repeater>; +}; + +&pm8550b_eusb2_repeater { + qcom,param-override-seq = + /* */ + /* Adjust HS trasmit amplitude */ + <0xd 0x51 + /* Squelch detection threshold */ + 0x3 0x54 + /* Tx pre-emphasis tuning */ + 0x7 0x57 + /* HS disconnect threshold */ + 0x6 0x53 + /* slew rate */ + 0x00 0x59>; +}; + +&usb0 { + qcom,wcd_usbss = <&wcd_usbss>; + usb-role-switch; + port { + usb_port0: endpoint { + remote-endpoint = <&usb_port0_connector>; + }; + }; +}; + +&ucsi { + connector { + port { + usb_port0_connector: endpoint { + remote-endpoint = <&usb_port0>; + }; + }; + }; +}; + +&qupv3_se6_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + + vdd-supply = <&L15B>; + + lane-channel-swap; + + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x4 0x6 0x6 0x4>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x0 0x3 0x3 0x0>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; + +&usb_qmp_dp_phy { + pinctrl-names = "unused"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_gpio>; + gpios = <&tlmm 29 0>; + + ssusb_redriver = <&redriver>; +}; + +®ulator_ocp_notifier { + periph-1c1-supply = <&L1B>; + periph-1c2-supply = <&L2B>; + periph-1c5-supply = <&L5B>; + periph-1c6-supply = <&L6B>; + periph-1c7-supply = <&L7B>; + periph-1c8-supply = <&L8B>; + periph-1c9-supply = <&L9B>; + periph-1ca-supply = <&L10B>; + periph-1cb-supply = <&L11B>; + periph-1cc-supply = <&L12B>; + periph-1cd-supply = <&L13B>; + periph-1ce-supply = <&L14B>; + periph-1cf-supply = <&L15B>; + periph-1d0-supply = <&L16B>; + periph-1d1-supply = <&L17B>; + periph-1e4-supply = <&BOB1>; + periph-1e6-supply = <&BOB2>; + periph-29b-supply = <&S1C>; + periph-29e-supply = <&S2C>; + periph-2a1-supply = <&S3C>; + periph-2a4-supply = <&S4C>; + periph-2a7-supply = <&S5C>; + periph-2aa-supply = <&S6C>; + periph-2c1-supply = <&L1C>; + periph-2c2-supply = <&L2C>; + periph-2c3-supply = <&L3C>; + periph-3a1-supply = <&S3D_LEVEL>; + periph-3a4-supply = <&S4D_LEVEL>; + periph-3a7-supply = <&S5D_LEVEL>; + periph-3c1-supply = <&L1D>; + periph-3c2-supply = <&L2D_LEVEL>; + periph-3c3-supply = <&L3D>; + periph-4c2-supply = <&L2E>; + periph-4c3-supply = <&L3E>; + periph-69b-supply = <&S1G_LEVEL>; + periph-6a1-supply = <&S3G>; + periph-6a4-supply = <&S4G_LEVEL>; + periph-6a7-supply = <&S5G_LEVEL>; + periph-6c1-supply = <&L1G>; + periph-6c2-supply = <&L2G>; + periph-6c3-supply = <&L3G>; + periph-89b-supply = <&S1I_LEVEL>; + periph-8a1-supply = <&S3I_LEVEL>; + periph-8a4-supply = <&S4I>; + periph-8a7-supply = <&S5I>; + periph-8aa-supply = <&S6I_LEVEL>; + periph-8b0-supply = <&S8I_LEVEL>; + periph-8c1-supply = <&L1I>; + periph-8c2-supply = <&L2I>; + periph-8c3-supply = <&L3I>; + periph-ac1-supply = <&L1K>; + periph-ac2-supply = <&L2K>; + periph-ac3-supply = <&L3K>; + periph-ac4-supply = <&L4K>; + periph-ac5-supply = <&L5K>; + periph-ac6-supply = <&L6K>; + periph-ac7-supply = <&L7K>; + periph-c40-supply = <&L1M>; + periph-c41-supply = <&L2M>; + periph-c42-supply = <&L3M>; + periph-c43-supply = <&L4M>; + periph-c44-supply = <&L5M>; + periph-c45-supply = <&L6M>; + periph-c46-supply = <&L7M>; + periph-d40-supply = <&L1N>; + periph-d41-supply = <&L2N>; + periph-d42-supply = <&L3N>; + periph-d43-supply = <&L4N>; + periph-d44-supply = <&L5N>; + periph-d45-supply = <&L6N>; + periph-d46-supply = <&L7N>; +}; diff --git a/qcom/pineapple-qupv3.dtsi b/qcom/pineapple-qupv3.dtsi new file mode 100644 index 00000000..7a19bbca --- /dev/null +++ b/qcom/pineapple-qupv3.dtsi @@ -0,0 +1,1188 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup2 0: SE 8 + * Qup2 1: SE 9 + * Qup2 2: SE 10 + * Qup2 3: SE 11 + * Qup2 4: SE 12 + * Qup2 5: SE 13 + * Qup2 6: SE 14 + * Qup2 7: SE 15 + */ + + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x3>; + qcom,gpii-mask = <0xc>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* NFC I3C Instance */ + i3c0: i3c-master@a80000 { + compatible = "qcom,geni-i3c"; + reg = <0xa80000 0x4000>, + <0xec90000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>; + pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se0_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 31 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 2>, + <&gpi_dma1 1 4 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, + <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + dmas = <&gpi_dma1 0 4 1 64 2>, + <&gpi_dma1 1 4 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Touch I3C Instance */ + i3c1: i3c-master@a90000 { + compatible = "qcom,geni-i3c"; + reg = <0xa90000 0x4000>, + <0xecb0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se4_i3c_sda_active>, <&qupv3_se4_i3c_scl_active>; + pinctrl-1 = <&qupv3_se4_i3c_sda_sleep>, <&qupv3_se4_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se4_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 35 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 34 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <4>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + reg = <0xa94000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>, + <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma1 0 7 3 64 4>, + <&gpi_dma1 1 7 3 64 4>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma1 0 7 1 64 4>, + <&gpi_dma1 1 7 1 64 4>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x436 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x3f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma2 0 0 3 64 0>, + <&gpi_dma2 1 0 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma2 0 0 1 64 0>, + <&gpi_dma2 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* Camera I3C Instance */ + i3c2: i3c-master@880000 { + compatible = "qcom,geni-i3c"; + reg = <0x880000 0x4000>, + <0xecd0000 0x10000>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se8_i3c_sda_active>, <&qupv3_se8_i3c_scl_active>; + pinctrl-1 = <&qupv3_se8_i3c_sda_sleep>, <&qupv3_se8_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se8_i3c_disable>; + interrupts-extended = <&intc GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 48 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <0>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma2 0 1 3 64 0>, + <&gpi_dma2 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma2 0 1 1 64 0>, + <&gpi_dma2 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma2 0 2 3 64 0>, + <&gpi_dma2 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>, + <&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma2 0 2 1 64 0>, + <&gpi_dma2 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + i3c3: i3c-master@888000 { /* QUPV3_2, SE2: NAON */ + compatible = "qcom,geni-i3c"; + reg = <0x888000 0x4000>, + <0xb00000 0x10000>; + clock-names = "se-clk", + "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK>, + <&gcc GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC>; + qcom,ibic-naon; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se10_i3c_sda_active>, <&qupv3_se10_i3c_scl_active>; + pinctrl-1 = <&qupv3_se10_i3c_sda_sleep>, <&qupv3_se10_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se10_i3c_disable>; + interrupts = , + , + ; + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <7>; + status = "disabled"; + }; + + i3c4: i3c-master@88c000 { /* QUPV3_2, SE3: NAON */ + compatible = "qcom,geni-i3c"; + reg = <0x888c00 0x4000>, + <0xb10000 0x10000>; + clock-names = "se-clk", + "ibic-core-clk", "ibic-ahb-clk", "ibic-src-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC>; + qcom,ibic-naon; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep", "disable"; + pinctrl-0 = <&qupv3_se11_i3c_sda_active>, <&qupv3_se11_i3c_scl_active>; + pinctrl-1 = <&qupv3_se11_i3c_sda_sleep>, <&qupv3_se11_i3c_scl_sleep>; + pinctrl-2 = <&qupv3_se11_i3c_disable>; + interrupts = , + , + ; + + #address-cells = <3>; + #size-cells = <0>; + qcom,ibi-ctrl-id = <8>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma2 0 3 3 64 0>, + <&gpi_dma2 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>, + <&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma2 0 3 1 64 0>, + <&gpi_dma2 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma2 0 4 3 64 0>, + <&gpi_dma2 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>, + <&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma2 0 4 1 64 0>, + <&gpi_dma2 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + dmas = <&gpi_dma2 0 5 3 64 0>, + <&gpi_dma2 1 5 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se13_spi: spi@894000 { + compatible = "qcom,spi-geni"; + reg = <0x894000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>, + <&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + dmas = <&gpi_dma2 0 5 1 64 0>, + <&gpi_dma2 1 5 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se14_4uart: qcom,qup_uart@898000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 27 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_rx>; + pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>, + <&qupv3_se14_tx>, <&qupv3_se14_default_rx>; + pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>, + <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* Debug UART Instance */ + qupv3_se15_2uart: qcom,qup_uart@89c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_2uart_tx_active>, <&qupv3_se15_2uart_rx_active>; + pinctrl-1 = <&qupv3_se15_2uart_sleep>; + status = "disabled"; + }; + + }; + + /* QUPv3_0 I2C master hub */ + qupv3_0_i2c_hub: qcom,qupv3_i2c_geni_se@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x9c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + /* Upstream common driver using m-ahb and s-ahb clocks, for i2c-hub HW + * supports only s-ahb clock. To support upstream model we are using both + * the clocks, but for m-ahb clock we defined s-ahb clock node only. + */ + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>, + <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + ranges; + status = "ok"; + + qupv3_hub_i2c0: i2c@980000 { + compatible = "qcom,i2c-geni"; + reg = <0x980000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c0_sda_active>, <&qupv3_hub_i2c0_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c0_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c1: i2c@984000 { + compatible = "qcom,i2c-geni"; + reg = <0x984000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c1_sda_active>, <&qupv3_hub_i2c1_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c1_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c2: i2c@988000 { + compatible = "qcom,i2c-geni"; + reg = <0x988000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c2_sda_active>, <&qupv3_hub_i2c2_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c2_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c3: i2c@98c000 { + compatible = "qcom,i2c-geni"; + reg = <0x98c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c3_sda_active>, <&qupv3_hub_i2c3_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c3_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c4: i2c@990000 { + compatible = "qcom,i2c-geni"; + reg = <0x990000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c4_sda_active>, <&qupv3_hub_i2c4_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c4_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c5: i2c@994000 { + compatible = "qcom,i2c-geni"; + reg = <0x994000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c5_sda_active>, <&qupv3_hub_i2c5_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c5_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c6: i2c@998000 { + compatible = "qcom,i2c-geni"; + reg = <0x998000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c6_sda_active>, <&qupv3_hub_i2c6_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c6_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c7: i2c@99c000 { + compatible = "qcom,i2c-geni"; + reg = <0x99c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c7_sda_active>, <&qupv3_hub_i2c7_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c7_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c8: i2c@9a0000 { + compatible = "qcom,i2c-geni"; + reg = <0x9a0000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c8_sda_active>, <&qupv3_hub_i2c8_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c8_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + qupv3_hub_i2c9: i2c@9a4000 { + compatible = "qcom,i2c-geni"; + reg = <0x9a4000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "core-clk"; + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = + <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_I2C>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_hub_i2c9_sda_active>, <&qupv3_hub_i2c9_scl_active>; + pinctrl-1 = <&qupv3_hub_i2c9_sleep>; + qcom,i2c-hub; + qcom,rtl_se; + status = "disabled"; + }; + + }; +}; diff --git a/qcom/pineapple-rcm-overlay.dts b/qcom/pineapple-rcm-overlay.dts new file mode 100644 index 00000000..208d876f --- /dev/null +++ b/qcom/pineapple-rcm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple RCM"; + compatible = "qcom,pineapple-rcm", "qcom,pineapple", "qcom,pineapplep-rcm", "qcom,pineapplep", "qcom,rcm"; + qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>; + qcom,board-id = <0x15 0>; +}; diff --git a/qcom/pineapple-rcm.dtsi b/qcom/pineapple-rcm.dtsi new file mode 100644 index 00000000..5be846d6 --- /dev/null +++ b/qcom/pineapple-rcm.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple-cdp.dtsi" + +&qupv3_se4_spi { + status = "disabled"; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,i2c-touch-active = "atmel,maxtouch"; + qcom,la-vm; + + atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&tlmm>; + interrupts = <162 0x2008>; + avdd-supply = <&L14B>; + vdd-supply = <&L12B>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + atmel,xy_switch; + atmel,inverty; + atmel,invertx; + reset-gpios = <&tlmm 161 0x00>; + irq-gpios = <&tlmm 162 0x2008>; + atmel,panel-coords = <0 0 479 799>; + atmel,display-coords = <0 0 339 729>; + }; +}; diff --git a/qcom/pineapple-regulators.dtsi b/qcom/pineapple-regulators.dtsi new file mode 100644 index 00000000..78a38b0d --- /dev/null +++ b/qcom/pineapple-regulators.dtsi @@ -0,0 +1,1378 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + + VDD_LPI_CX_LEVEL: S4D_LEVEL: + pm_v6d_s4_level: regulator-pm-v6d-s4-level { + regulator-name = "pm_v6d_s4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + + VDD_GFX_LEVEL: S5D_LEVEL: + pm_v6d_s5_level: regulator-pm-v6d-s5-level { + regulator-name = "pm_v6d_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + + VDD_LPI_MX_LEVEL: L2D_LEVEL: + pm_v6d_l2_level: regulator-pm-v6d-l2-level { + regulator-name = "pm_v6d_l2_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-nsp2lvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "nsp2.lvl"; + + VDD_NSP2_LEVEL: S1G_LEVEL: + pm_v6g_s1_level: regulator-pm-v6g-s1-level { + regulator-name = "pm_v6g_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + + VDD_EBI_LEVEL: S4G_LEVEL: + pm_v6g_s4_level: regulator-pm-v6g-s4-level { + regulator-name = "pm_v6g_s4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + + VDD_MODEM_LEVEL: S5G_LEVEL: + pm_v6g_s5_level: regulator-pm-v6g-s5-level { + regulator-name = "pm_v6g_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: S8I_LEVEL: + pm_v8_s8_level: regulator-pm-v8-s8-level { + regulator-name = "pm_v8_s8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: S8I_LEVEL_AO: + pm_v8_s8_level_ao: regulator-pm-v8-s8-level-ao { + regulator-name = "pm_v8_s8_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm-v8-s8-mmcx-sup-level { + regulator-name = "pm_v8_s8_mmcx_sup_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mmcx.lvl"; + proxy-supply = <&VDD_MMCX_LEVEL>; + + VDD_MMCX_LEVEL: VDD_MM_LEVEL: S1I_LEVEL: + pm_v8_s1_level: regulator-pm-v8-s1-level { + regulator-name = "pm_v8_s1_level"; + qcom,set = ; + pm_v8_s1_level-parent-supply = + <&VDD_CX_MMCX_SUPPLY_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MMCX_LEVEL_AO: VDD_MM_LEVEL_AO: S1I_LEVEL_AO: + pm_v8_s1_level_ao: regulator-pm-v8-s1-level-ao { + regulator-name = "pm_v8_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + regulator-pm-v8-s1-level-so { + regulator-name = "pm_v8_s1_level_so"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: S3I_LEVEL: + pm_v8_s3_level: regulator-pm-v8-s3-level { + regulator-name = "pm_v8_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: S3I_LEVEL_AO: + pm_v8_s3_level_ao: regulator-pm-v8-s3-level-ao { + regulator-name = "pm_v8_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + proxy-supply = <&VDD_MXC_LEVEL>; + + VDD_MXC_LEVEL: S3D_LEVEL: + pm_v6d_s3_level: regulator-pm-v6d-s3-level { + regulator-name = "pm_v6d_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXC_LEVEL_AO: S3D_LEVEL_AO: + pm_v6d_s3_level_ao: regulator-pm-v6d-s3-level-ao { + regulator-name = "pm_v6d_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MXC_MMCX_VOTER_LEVEL: VDD_MXC_MM_VOTER_LEVEL: + VDD_MM_MXC_VOTER_LEVEL: + regulator-pm-v6d-s3-mmcx-voter-level { + regulator-name = "pm_v6d_s3_mmcx_voter_level"; + pm_v6d_s3_mmcx_voter_level-parent-supply = + <&VDD_MMCX_LEVEL>; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MXC_GFX_VOTER_LEVEL: VDD_GFX_MXC_VOTER_LEVEL: + regulator-pm-v6d-s3-gfx-voter-level { + regulator-name = "pm_v6d_s3_gfx_voter_level"; + pm_v6d_s3_gfx_voter_level-parent-supply = + <&VDD_GFX_LEVEL>; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-nsplvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "nsp.lvl"; + + VDD_NSP1_LEVEL: S6I_LEVEL: + pm_v8_s6_level: regulator-pm-v8-s6-level { + regulator-name = "pm_v8_s6_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1B: pm_humu_l1: regulator-pm-humu-l1 { + regulator-name = "pm_humu_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L2B: pm_humu_l2: regulator-pm-humu-l2 { + regulator-name = "pm_humu_l2"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <3008000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L5B: pm_humu_l5: regulator-pm-humu-l5 { + regulator-name = "pm_humu_l5"; + qcom,set = ; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <3104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L6B: pm_humu_l6: regulator-pm-humu-l6 { + regulator-name = "pm_humu_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L7B: pm_humu_l7: regulator-pm-humu-l7 { + regulator-name = "pm_humu_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L8B: pm_humu_l8: regulator-pm-humu-l8 { + regulator-name = "pm_humu_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L9B: pm_humu_l9: regulator-pm-humu-l9 { + regulator-name = "pm_humu_l9"; + qcom,set = ; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2960000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L10B: pm_humu_l10: regulator-pm-humu-l10 { + regulator-name = "pm_humu_l10"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&L11B>; + + L11B: pm_humu_l11: regulator-pm-humu-l11 { + regulator-name = "pm_humu_l11"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&L12B>; + + L12B: pm_humu_l12: regulator-pm-humu-l12 { + regulator-name = "pm_humu_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + proxy-supply = <&L13B>; + + L13B: pm_humu_l13: regulator-pm-humu-l13 { + regulator-name = "pm_humu_l13"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L14B: pm_humu_l14: regulator-pm-humu-l14 { + regulator-name = "pm_humu_l14"; + qcom,set = ; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + qcom,init-voltage = <3200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L15B: pm_humu_l15: regulator-pm-humu-l15 { + regulator-name = "pm_humu_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L16B: pm_humu_l16: regulator-pm-humu-l16 { + regulator-name = "pm_humu_l16"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L17B: pm_humu_l17: regulator-pm-humu-l17 { + regulator-name = "pm_humu_l17"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobb1"; + + BOB1: pm_humu_bob1: regulator-pm-humu-bob1 { + regulator-name = "pm_humu_bob1"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + }; + }; + + rpmh-regulator-bobb2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobb2"; + + BOB2: pm_humu_bob2: regulator-pm-humu-bob2 { + regulator-name = "pm_humu_bob2"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2720000>; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc1"; + + S1C: pm_v6c_s1: regulator-pm-v6c-s1 { + regulator-name = "pm_v6c_s1"; + qcom,set = ; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1348000>; + qcom,init-voltage = <1256000>; + }; + }; + + rpmh-regulator-smpc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc2"; + + S2C: pm_v6c_s2: regulator-pm-v6c-s2 { + regulator-name = "pm_v6c_s2"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + qcom,init-voltage = <852000>; + }; + }; + + rpmh-regulator-smpc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc3"; + + S3C: pm_v6c_s3: regulator-pm-v6c-s3 { + regulator-name = "pm_v6c_s3"; + qcom,set = ; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <1064000>; + qcom,init-voltage = <976000>; + }; + }; + + rpmh-regulator-smpc4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc4"; + + S4C: pm_v6c_s4: regulator-pm-v6c-s4 { + regulator-name = "pm_v6c_s4"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1280000>; + qcom,init-voltage = <1224000>; + }; + }; + + rpmh-regulator-smpc5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc5"; + + S5C: pm_v6c_s5: regulator-pm-v6c-s5 { + regulator-name = "pm_v6c_s5"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <900000>; + qcom,init-voltage = <752000>; + }; + }; + + rpmh-regulator-smpc6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpc6"; + + S6C: pm_v6c_s6: regulator-pm-v6c-s6 { + regulator-name = "pm_v6c_s6"; + qcom,set = ; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1856000>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1C: pm_v6c_l1: regulator-pm-v6c-l1 { + regulator-name = "pm_v6c_l1"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2C: pm_v6c_l2: regulator-pm-v6c-l2 { + regulator-name = "pm_v6c_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3C: pm_v6c_l3: regulator-pm-v6c-l3 { + regulator-name = "pm_v6c_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1D: pm_v6d_l1: regulator-pm-v6d-l1 { + regulator-name = "pm_v6d_l1"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldod3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3D: pm_v6d_l3: regulator-pm-v6d-l3 { + regulator-name = "pm_v6d_l3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + qcom,init-voltage = <832000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2E: pm_v6e_l2: regulator-pm-v6e-l2 { + regulator-name = "pm_v6e_l2"; + qcom,set = ; + regulator-min-microvolt = <864000>; + regulator-max-microvolt = <972000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoe3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3E: pm_v6e_l3: regulator-pm-v6e-l3 { + regulator-name = "pm_v6e_l3"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpg3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg3"; + + S3G: pm_v6g_s3: regulator-pm-v6g-s3 { + regulator-name = "pm_v6g_s3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + qcom,init-voltage = <1080000>; + }; + }; + + rpmh-regulator-ldog1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1G: pm_v6g_l1: regulator-pm-v6g-l1 { + regulator-name = "pm_v6g_l1"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2G: pm_v6g_l2: regulator-pm-v6g-l2 { + regulator-name = "pm_v6g_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3G: pm_v6g_l3: regulator-pm-v6g-l3 { + regulator-name = "pm_v6g_l3"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpi4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpi4"; + + S4I: pm_v8_s4: regulator-pm-v8-s4 { + regulator-name = "pm_v8_s4"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + qcom,init-voltage = <852000>; + }; + }; + + rpmh-regulator-smpi5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpi5"; + + S5I: pm_v8_s5: regulator-pm-v8-s5 { + regulator-name = "pm_v8_s5"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <700000>; + qcom,init-voltage = <500000>; + }; + }; + + rpmh-regulator-ldoi1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoi1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&L1I>; + + L1I: pm_v8_l1: regulator-pm-v8-l1 { + regulator-name = "pm_v8_l1"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + }; + + L1I_AO: pm_v8_l1_ao: regulator-pm-v8-l1-ao { + regulator-name = "pm_v8_l1_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm-v8-l1-so { + regulator-name = "pm_v8_l1_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoi2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoi2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2I: pm_v8_l2: regulator-pm-v8-l2 { + regulator-name = "pm_v8_l2"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoi3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldoi3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&L3I>; + + L3I: pm_v8_l3: regulator-pm-v8-l3 { + regulator-name = "pm_v8_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + }; + + L3I_AO: pm_v8_l3_ao: regulator-pm-v8-l3-ao { + regulator-name = "pm_v8_l3_ao"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + + regulator-pm-v8-l3-so { + regulator-name = "pm_v8_l3_so"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldok1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1K: pmr_nalojr_l1: regulator-pmr-nalojr-l1 { + regulator-name = "pmr_nalojr_l1"; + qcom,set = ; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2K: pmr_nalojr_l2: regulator-pmr-nalojr-l2 { + regulator-name = "pmr_nalojr_l2"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3K: pmr_nalojr_l3: regulator-pmr-nalojr-l3 { + regulator-name = "pmr_nalojr_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L4K: pmr_nalojr_l4: regulator-pmr-nalojr-l4 { + regulator-name = "pmr_nalojr_l4"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L5K: pmr_nalojr_l5: regulator-pmr-nalojr-l5 { + regulator-name = "pmr_nalojr_l5"; + qcom,set = ; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <976000>; + qcom,init-voltage = <952000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L6K: pmr_nalojr_l6: regulator-pmr-nalojr-l6 { + regulator-name = "pmr_nalojr_l6"; + qcom,set = ; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1860000>; + qcom,init-voltage = <1776000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L7K: pmr_nalojr_l7: regulator-pmr-nalojr-l7 { + regulator-name = "pmr_nalojr_l7"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1M: pm8010m_l1: regulator-pm8010m-l1 { + regulator-name = "pm8010m_l1"; + qcom,set = ; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + qcom,init-voltage = <1104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2M: pm8010m_l2: regulator-pm8010m-l2 { + regulator-name = "pm8010m_l2"; + qcom,set = ; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + qcom,init-voltage = <1056000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom3"; + + L3M: pm8010m_l3: regulator-pm8010m-l3 { + regulator-name = "pm8010m_l3"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + }; + + rpmh-regulator-ldom4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom4"; + + L4M: pm8010m_l4: regulator-pm8010m-l4 { + regulator-name = "pm8010m_l4"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + }; + + rpmh-regulator-ldom5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom5"; + + L5M: pm8010m_l5: regulator-pm8010m-l5 { + regulator-name = "pm8010m_l5"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldom6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom6"; + + L6M: pm8010m_l6: regulator-pm8010m-l6 { + regulator-name = "pm8010m_l6"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + }; + + rpmh-regulator-ldom7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom7"; + + L7M: pm8010m_l7: regulator-pm8010m-l7 { + regulator-name = "pm8010m_l7"; + qcom,set = ; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2960000>; + }; + }; + + rpmh-regulator-ldon1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1N: pm8010n_l1: regulator-pm8010n-l1 { + regulator-name = "pm8010n_l1"; + qcom,set = ; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + qcom,init-voltage = <1104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldon2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2N: pm8010n_l2: regulator-pm8010n-l2 { + regulator-name = "pm8010n_l2"; + qcom,set = ; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + qcom,init-voltage = <1056000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldon3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon3"; + + L3N: pm8010n_l3: regulator-pm8010n-l3 { + regulator-name = "pm8010n_l3"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldon4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon4"; + + L4N: pm8010n_l4: regulator-pm8010n-l4 { + regulator-name = "pm8010n_l4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldon5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon5"; + + L5N: pm8010n_l5: regulator-pm8010n-l5 { + regulator-name = "pm8010n_l5"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + }; + + rpmh-regulator-ldon6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon6"; + + L6N: pm8010n_l6: regulator-pm8010n-l6 { + regulator-name = "pm8010n_l6"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + }; + }; + + rpmh-regulator-ldon7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon7"; + + L7N: pm8010n_l7: regulator-pm8010n-l7 { + regulator-name = "pm8010n_l7"; + qcom,set = ; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3304000>; + }; + }; +}; diff --git a/qcom/pineapple-rumi-overlay.dts b/qcom/pineapple-rumi-overlay.dts new file mode 100644 index 00000000..8d65afb8 --- /dev/null +++ b/qcom/pineapple-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "pineapple-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple RUMI"; + compatible = "qcom,pineapple-rumi", "qcom,pineapple", "qcom,rumi"; + qcom,msm-id = <557 0x10000>, <557 0x20000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/pineapple-rumi.dtsi b/qcom/pineapple-rumi.dtsi new file mode 100644 index 00000000..fbe0a08a --- /dev/null +++ b/qcom/pineapple-rumi.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +#include "pineapple-pmic-overlay.dtsi" + +&chosen { +}; + +&reserved_memory { + spintable: spintable_region@e3940000 { + no-map; + reg = <0x0 0xe3940000 0x0 0x100000>; + }; +}; + +&arch_timer { + clock-frequency = <192000>; +}; + +&memtimer { + clock-frequency = <192000>; +}; + +&qupv3_se15_2uart { + qcom,rumi_platform; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&pm_humu_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm_humu_l8>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qcom,iommu-dma = "fastmap"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-max-microamp = <150000>; + vdda-pll-max-microamp = <19200>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v6c_l1>; + vccq-max-microamp = <1200000>; + + qcom,vddp-ref-clk-supply = <&pm_v6c_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v6c_s1>; + qcom,vccq-parent-max-microamp = <210000>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + qcom,iommu-dma = "bypass"; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "ok"; +}; + +&SILVER_OFF_CL0 { + status = "nok"; +}; + +&GOLD_OFF_CL1 { + status = "nok"; +}; + +&GOLD_OFF_CL2 { + status = "nok"; +}; + +&GOLD_OFF_CL3 { + status = "nok"; +}; + +&CLUSTER_PWR_DN { + status = "nok"; +}; + +&APSS_OFF { + status = "nok"; +}; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; + +&tsens2 { + status = "disabled"; +}; + +&soc { + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_emuphy: phy@a784000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a784000 0x9500>; + + qcom,emu-init-seq = <0xfffff 0x4 + 0xffff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x000101F0 0x20 + 0x00100000 0x3c + 0x0 0x3c + 0x0 0x4>; + }; + + pcie0: qcom,pcie@1c00000 { + reg = <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x01c05000 0x1000>, + <0x01D07000 0x7000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", + "rumi", "pcie_sm"; + linux,pci-domain = <0>; + qcom,target-link-speed = <0x1>; + qcom,link-check-max-count = <200>; /* 1 sec */ + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + /* + * Comment out ICC and SMMU properties in main PCIe node + * if any issue in PCIe probe in RUMI + */ + status = "ok"; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emuphy>, <&usb_nop_phy>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + }; +}; + +&bwmon_ddr { + qcom,hw-timer-hz = <192000>; +}; + +&bwmon_llcc { + qcom,hw-timer-hz = <192000>; +}; diff --git a/qcom/pineapple-thermal-modem.dtsi b/qcom/pineapple-thermal-modem.dtsi new file mode 100644 index 00000000..bc1ee3e4 --- /dev/null +++ b/qcom/pineapple-thermal-modem.dtsi @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_lte_dsc: modem_lte_dsc { + qcom,qmi-dev-name = "modem_lte_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_dsc: modem_nr_dsc { + qcom,qmi-dev-name = "modem_nr_dsc"; + #cooling-cells = <2>; + }; + + modem_nr_scg_dsc: modem_nr_scg_dsc { + qcom,qmi-dev-name = "modem_nr_scg_dsc"; + #cooling-cells = <2>; + }; + + sdr0_lte_dsc: sdr0_lte_dsc { + qcom,qmi-dev-name = "sdr0_lte_dsc"; + #cooling-cells = <2>; + }; + + sdr0_nr_dsc: sdr0_nr_dsc { + qcom,qmi-dev-name = "sdr0_nr_dsc"; + #cooling-cells = <2>; + }; + + pa_lte_sdr0_dsc: pa_lte_sdr0_dsc { + qcom,qmi-dev-name = "pa_lte_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_dsc: pa_nr_sdr0_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_dsc"; + #cooling-cells = <2>; + }; + + pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg_dsc { + qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc"; + #cooling-cells = <2>; + }; + + mmw0_dsc: mmw0_dsc { + qcom,qmi-dev-name = "mmw0_dsc"; + #cooling-cells = <2>; + }; + + mmw1_dsc: mmw1_dsc { + qcom,qmi-dev-name = "mmw1_dsc"; + #cooling-cells = <2>; + }; + + mmw2_dsc: mmw2_dsc { + qcom,qmi-dev-name = "mmw2_dsc"; + #cooling-cells = <2>; + }; + + mmw3_dsc: mmw3_dsc { + qcom,qmi-dev-name = "mmw3_dsc"; + #cooling-cells = <2>; + }; + + qmi_wlan: wlan { + qcom,qmi-dev-name = "wlan"; + #cooling-cells = <2>; + }; + + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "modem_tsens", + "modem_tsens1", + "pa", + "pa_1", + "modem_bcl_warn", + "sdr0_pa", + "sdr0", + "mmw0", + "mmw1", + "mmw2", + "mmw3", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", + "mmw_ific0", + "epm0", + "epm1", + "epm2", + "epm3", + "epm4", + "epm5", + "epm6", + "epm7", + "sys_therm1", + "sys_therm2", + "sys_therm3", + "sys_therm4", + "sys_therm5", + "sys_therm6", + "sub0_sdr0_pa", + "sdr_mmw_therm", + "sub1_modem_cfg", + "sub1_lte_cc", + "sub1_mcg_fr1_cc", + "sub1_mcg_fr2_cc", + "sub1_scg_fr1_cc", + "sub1_scg_fr2_cc"; + }; + }; +}; + +&thermal_zones { + pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_PA_1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + bcl_warn { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BCL_WARN)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0_pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_pa3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_PA3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw_ific0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM0)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM1)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM2)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm4 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM4)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm5 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM5)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM6)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + epm7 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_EPM7)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdr_mmw_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR_MMW)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_modem_cfg { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MODEM_CFG)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_lte_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_LTE_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_mcg_fr2_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_MCG_FR2_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr1_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR1_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sub1_scg_fr2_cc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SUB1_SCG_FR2_CC)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2-sys3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SYS_THERM_3)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pineapple-thermal-overlay.dtsi b/qcom/pineapple-thermal-overlay.dtsi new file mode 100644 index 00000000..9eb5b324 --- /dev/null +++ b/qcom/pineapple-thermal-overlay.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_pause 1 1>; + }; + + socd_apc2 { + trip = <&socd_trip>; + cooling-device = <&APC2_pause 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8550b-bcl-lvl0 { + cooling-maps { + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 8 8>; + }; + + lbat_cpu_5_6_7 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cpu_5_6_7_pause 1 1>; + }; + + lbat_cdsp0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + lbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8550b-bcl-lvl1 { + cooling-maps { + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 12 12>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 11 11>; + }; + + lbat_cpu_2_3_4 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cpu_2_3_4_pause 1 1>; + }; + + lbat_cdsp1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + lbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8550b-bcl-lvl2 { + cooling-maps { + lbat_cdsp2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + lbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm8550-bcl-lvl0 { + cooling-maps { + vph_lte0 { + trip = <&bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vph_nr0_scg { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vph_nr0 { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_dsc 8 8>; + }; + + vph_cpu_5_6_7 { + trip = <&bcl_lvl0>; + cooling-device = <&cpu_5_6_7_pause 1 1>; + }; + + vph_cdsp0 { + trip = <&bcl_lvl0>; + cooling-device = <&cdsp_sw 2 2>; + }; + + vph_gpu0 { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8550-bcl-lvl1 { + cooling-maps { + vph_lte1 { + trip = <&bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vph_nr1_scg { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 12 12>; + }; + + vph_nr1 { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_dsc 11 11>; + }; + + vph_cpu_2_3_4 { + trip = <&bcl_lvl1>; + cooling-device = <&cpu_2_3_4_pause 1 1>; + }; + + vph_cdsp1 { + trip = <&bcl_lvl1>; + cooling-device = <&cdsp_sw 4 4>; + }; + + vph_gpu1 { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8550-bcl-lvl2 { + cooling-maps { + vph_cdsp2 { + trip = <&bcl_lvl2>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + vph_gpu2 { + trip = <&bcl_lvl2>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm8550vs_e_tz { + cooling-maps { + pm8550vs_e_apc1 { + trip = <&pm8550vs_e_trip0>; + cooling-device = <&APC1_pause 1 1>; + }; + + pm8550vs_e_apc2 { + trip = <&pm8550vs_e_trip0>; + cooling-device = <&APC2_pause 1 1>; + }; + }; + }; + + pm8550vs_d_tz { + cooling-maps { + pm8550vs_d_gpu { + trip = <&pm8550vs_d_trip0>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm8550vs_g_tz { + cooling-maps { + pm8550vs_g_nsp { + trip = <&pm8550vs_g_trip0>; + cooling-device = <&cdsp_sw_hmx 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + pm8550ve_tz { + cooling-maps { + pm8550ve_nsp { + trip = <&pm8550ve_trip0>; + cooling-device = <&cdsp_sw_hvx 5 THERMAL_NO_LIMIT>; + }; + }; + }; + + xo-therm { + cooling-maps { + apc1_cdev { + trip = <&xo_config0>; + cooling-device = <&APC1_pause 1 1>; + }; + + cdsp_cdev { + trip = <&xo_config0>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + gpu_cdev { + trip = <&xo_config0>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + + cpu3_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + + cpu4_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + + cpu5_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + + cpu6_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + + cpu7_hot_cdev { + trip = <&xo_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + + lte_cdev { + trip = <&xo_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev { + trip = <&xo_config1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + display_cdev1 { + trip = <&display_test_config1>; + cooling-device = <&display_fps 1 1>; + }; + + display_cdev2 { + trip = <&display_test_config2>; + cooling-device = <&display_fps 2 2>; + }; + + display_cdev3 { + trip = <&display_test_config3>; + cooling-device = <&display_fps 3 3>; + }; + + display_cdev4 { + trip = <&display_test_config4>; + cooling-device = <&display_fps 4 4>; + }; + }; + }; +}; diff --git a/qcom/pineapple-thermal.dtsi b/qcom/pineapple-thermal.dtsi new file mode 100644 index 00000000..496d9851 --- /dev/null +++ b/qcom/pineapple-thermal.dtsi @@ -0,0 +1,1976 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&msm_gpu { + #cooling-cells = <2>; +}; + +&soc { + tsens0: tsens0@c228000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c228000 0x1ff>, /* TM */ + <0x0c222000 0x1ff>; /* SROT */ + #qcom,sensors = <15>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens1@c229000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c229000 0x1ff>, /* TM */ + <0x0c223000 0x1ff>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2: tsens2@c22a000 { + compatible = "qcom,tsens-v2"; + reg = <0x0c22a000 0x1ff>, /* TM */ + <0x0c224000 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_pause: cpu4-pause { + qcom,cpus = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + #cooling-cells = <2>; + }; + + APC2_pause: apc2-pause { + qcom,cpus = <&CPU2 &CPU3 &CPU4>; + #cooling-cells = <2>; + }; + + APC1_pause: apc1-pause { + qcom,cpus = <&CPU5 &CPU6 &CPU7>; + #cooling-cells = <2>; + }; + + cpu_2_3_4_pause: cpu-2-3-4-pause { + qcom,cpus = <&CPU2 &CPU3 &CPU4>; + #cooling-cells = <2>; + }; + + cpu_5_6_7_pause: cpu-5-6-7-pause { + qcom,cpus = <&CPU5 &CPU6 &CPU7>; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu4 { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "pause-cpu4"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + + qcom,cpu-voltage-cdev { + compatible = "qcom,cc-cooling-devices"; + apc1_cluster: qcom,apc1-cluster { + qcom,cpus = <&CPU5 &CPU7>; + #cooling-cells = <2>; + }; + }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,bus-width = <4>; + qcom,freq-table = + < 547200 >, + < 768000 >, + < 1555200 >, + < 1708800 >, + < 2092800 >, + < 2736000 >, + < 3187200 >, + < 3686400 >, + < 4224000 >; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; + + qcom,limits-dcvs { + compatible = "qcom,msm-hw-limits"; + isens_vref_0p8-supply = <&pm_v8_l1_ao>; + isens-vref-0p8-settings = <880000 880000 30000>; + isens_vref_1p8-supply = <&pm_v8_l3_ao>; + isens-vref-1p8-settings = <1200000 1200000 8000>; + }; + + qmi_tmd: qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_sw_hvx: cdsp_hvx { + qcom,qmi-dev-name = "cdsp_sw_hvx"; + #cooling-cells = <2>; + }; + + cdsp_sw_hmx: cdsp_hmx { + qcom,qmi-dev-name = "cdsp_sw_hmx"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <16>; + #cooling-cells = <2>; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0 &CPU2 &CPU5 &CPU7>; + }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + limits_stat: limits-stat { + compatible = "qcom,limits-stat"; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", + "cpuss-2", "cpuss-3", "cpu-2-0-0", + "cpu-2-0-1", "cpu-2-1-0", "cpu-2-1-1", + "cpu-2-2-0", "cpu-2-2-1", "cpu-1-0-0", + "cpu-1-0-1", "cpu-1-1-0", "cpu-1-1-1", + "aoss-1", "cpu-1-2-0", "cpu-1-2-1", + "cpu-1-2-2", "cpu-0-0-0", "cpu-0-1-0", + "nsphvx-0", "nsphvx-1", "nsphmx-0", + "nsphmx-1", "nsphmx-2", "nsphmx-3", + "video", "ddr", "camera-0", + "camera-1", "aoss-2", "gpuss-0", + "gpuss-1", "gpuss-2", "gpuss-3", + "gpuss-4", "gpuss-5", "gpuss-6", + "gpuss-7", "mdmss-0", "mdmss-1", + "mdmss-2", "mdmss-3", + "pm8550b-ibat-lvl0", "vbat"; + }; +}; + +#include "pineapple-thermal-modem.dtsi" + +&thermal_zones { + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-2-0-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_emerg0: cpu2-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu2_emerg0_1: cpu2-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu200_cdev { + trip = <&cpu2_emerg0>; + cooling-device = <&cpu2_pause 1 1>; + }; + + cpu200_cdev1 { + trip = <&cpu2_emerg0_1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; + }; + }; + + cpu-2-0-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_emerg1: cpu2-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu2_emerg1_1: cpu2-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu201_cdev { + trip = <&cpu2_emerg1>; + cooling-device = <&cpu2_pause 1 1>; + }; + + cpu201_cdev1 { + trip = <&cpu2_emerg1_1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; + }; + }; + + cpu-2-1-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_emerg0: cpu3-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu3_emerg0_1: cpu3-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu210_cdev { + trip = <&cpu3_emerg0>; + cooling-device = <&cpu3_pause 1 1>; + }; + + cpu210_cdev1 { + trip = <&cpu3_emerg0_1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + }; + }; + + cpu-2-1-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_emerg1: cpu3-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu3_emerg1_1: cpu3-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu211_cdev { + trip = <&cpu3_emerg1>; + cooling-device = <&cpu3_pause 1 1>; + }; + + cpu211_cdev1 { + trip = <&cpu3_emerg1_1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + }; + }; + + cpu-2-2-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu4_emerg0: cpu4-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu4_emerg0_1: cpu4-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu220_cdev { + trip = <&cpu4_emerg0>; + cooling-device = <&cpu4_pause 1 1>; + }; + + cpu220_cdev1 { + trip = <&cpu4_emerg0_1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-2-2-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu4_emerg1: cpu4-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu4_emerg1_1: cpu4-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu221_cdev { + trip = <&cpu4_emerg1>; + cooling-device = <&cpu4_pause 1 1>; + }; + + cpu221_cdev1 { + trip = <&cpu4_emerg1_1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + }; + }; + + cpu-1-0-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu5_emerg0: cpu5-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu5_emerg0_1: cpu5-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu100_cdev { + trip = <&cpu5_emerg0>; + cooling-device = <&cpu5_pause 1 1>; + }; + + cpu100_cdev1 { + trip = <&cpu5_emerg0_1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-0-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu5_emerg1: cpu5-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu5_emerg1_1: cpu5-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu101_cdev { + trip = <&cpu5_emerg1>; + cooling-device = <&cpu5_pause 1 1>; + }; + + cpu101_cdev1 { + trip = <&cpu5_emerg1_1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + }; + }; + + cpu-1-1-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu6_emerg0: cpu6-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu6_emerg0_1: cpu6-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu110_cdev { + trip = <&cpu6_emerg0>; + cooling-device = <&cpu6_pause 1 1>; + }; + + cpu110_cdev1 { + trip = <&cpu6_emerg0_1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + cpu-1-1-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu6_emerg1: cpu6-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu6_emerg1_1: cpu6-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu111_cdev { + trip = <&cpu6_emerg1>; + cooling-device = <&cpu6_pause 1 1>; + }; + + cpu111_cdev1 { + trip = <&cpu6_emerg1_1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_emerg0: cpu7-emerg0-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu7_emerg0_1: cpu7-emerg0-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu120_cdev { + trip = <&cpu7_emerg0>; + cooling-device = <&cpu7_pause 1 1>; + }; + + cpu120_cdev1 { + trip = <&cpu7_emerg0_1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + cpu-1-2-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_emerg1: cpu7-emerg1-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu7_emerg1_1: cpu7-emerg1-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu121_cdev { + trip = <&cpu7_emerg1>; + cooling-device = <&cpu7_pause 1 1>; + }; + + cpu121_cdev1 { + trip = <&cpu7_emerg1_1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + cpu-1-2-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_emerg2: cpu7-emerg2-cfg { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu7_emerg2_1: cpu7-emerg2-1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu122_cdev { + trip = <&cpu7_emerg2>; + cooling-device = <&cpu7_pause 1 1>; + }; + + cpu122_cdev1 { + trip = <&cpu7_emerg2_1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + }; + }; + + cpu-0-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_emerg: cpu0-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu0_emerg1: cpu0-emerg1-cfg { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu000_cdev { + trip = <&cpu0_emerg>; + cooling-device = <&cpu0_pause 1 1>; + }; + + cpu000_cdev1 { + trip = <&cpu0_emerg1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; + }; + }; + + cpu-0-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_emerg: cpu1-emerg-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu1_emerg1: cpu1-emerg1-cfg { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu010_cdev { + trip = <&cpu1_emerg>; + cooling-device = <&cpu1_pause 1 1>; + }; + + cpu010_cdev1 { + trip = <&cpu1_emerg1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; + }; + }; + + nsphvx-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsphvx-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsphmx-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsphmx-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsphmx-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + nsphmx-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gold_cdev { + trip = <&ddr_config0>; + cooling-device = <&CPU2 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + gold_plus_cdev { + trip = <&ddr_config0>; + cooling-device = <&CPU7 + THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + ddr_cdev { + trip = <&ddr_config0>; + cooling-device = <&ddr_cdev 5 5>; + }; + }; + }; + + camera-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu2_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu2_cdev { + trip = <&gpu2_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu3_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu3_cdev { + trip = <&gpu3_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-4 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu4_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu4_cdev { + trip = <&gpu4_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-5 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu5_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu5_cdev { + trip = <&gpu5_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-6 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu6_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu6_cdev { + trip = <&gpu6_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-7 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu7_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu7_cdev { + trip = <&gpu7_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; + }; + + mdmss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 10>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 11>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + nr_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lte_cdev2 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 12>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_scg_dsc 12 12>; + }; + + nr_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_dsc 8 8>; + }; + + lte_cdev2 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; +}; diff --git a/qcom/pineapple-usb.dtsi b/qcom/pineapple-usb.dtsi new file mode 100644 index 00000000..bf0aff64 --- /dev/null +++ b/qcom/pineapple-usb.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>, + <0x1fc6000 0x4>; + reg-names = "core_base", + "tcsr_dyn_en_dis"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,use-pdc-interrupts; + qcom,use-eusb2-phy; + + qcom,dis-sending-cm-l1-quirk; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + extcon = <&eud>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xd93c>; + + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + + interrupts = ; + usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + dr_mode = "otg"; + maximum-speed = "super-speed-plus"; + usb-role-switch; + }; + }; + + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-snps-eusb2-phy"; + reg = <0x88e3000 0x154>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&pm_v8_l1>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&pm_v8_l3>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm_v6g_l3>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm_v8_l3>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100b 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xb>; + qcom,usb-audio-intr-num = <2>; + }; +}; + diff --git a/qcom/pineapple-v2.dts b/qcom/pineapple-v2.dts new file mode 100644 index 00000000..1b6726e9 --- /dev/null +++ b/qcom/pineapple-v2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "pineapple-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple v2 SoC"; + compatible = "qcom,pineapple"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/pineapple-v2.dtsi b/qcom/pineapple-v2.dtsi new file mode 100644 index 00000000..f635d762 --- /dev/null +++ b/qcom/pineapple-v2.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple v2 SoC"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x20000>; +}; + +&camcc { + compatible = "qcom,pineapple-camcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,pineapple-videocc-v2", "syscon"; +}; + +&qcom_memlat { + ddr { + silver { + qcom,cpufreq-memfreq-tbl = + < 1132800 547000 >, + < 1574400 768000 >, + < 2265600 1555000 >; + }; + + gold { + qcom,cpufreq-memfreq-tbl = + < 614400 547000 >, + < 960000 768000 >, + < 1190400 1555000 >, + < 1401600 2092000 >, + < 1920000 2736000 >, + < 2764800 3686000 >, + < 3187200 4224000 >; + }; + + prime { + qcom,cpufreq-memfreq-tbl = + < 614400 547000 >, + < 960000 768000 >, + < 1190400 1555000 >, + < 1401600 2092000 >, + < 1920000 2736000 >, + < 2764800 3686000 >, + < 3187200 4224000 >; + }; + + gold-compute { + qcom,cpufreq-memfreq-tbl = + < 2131200 547000 >, + < 3187200 2092000 >; + }; + + prime-latfloor { + qcom,cpufreq-memfreq-tbl = + < 2764800 547000 >, + < 3187200 4224000 >; + }; + }; + + llcc { + silver { + qcom,cpufreq-memfreq-tbl = + < 902400 300000 >, + < 1574400 466000 >, + < 2265600 600000 >; + }; + + gold { + qcom,cpufreq-memfreq-tbl = + < 614400 300000 >, + < 1190400 466000 >, + < 1401600 600000 >, + < 1920000 806000 >, + < 2764800 933000 >, + < 3187200 1066000 >; + }; + + gold-compute { + qcom,cpufreq-memfreq-tbl = + < 2131200 300000 >, + < 3187200 600000 >; + }; + + }; + + l3 { + silver { + qcom,cpufreq-memfreq-tbl = + < 307200 307200 >, + < 460800 384000 >, + < 556800 499200 >, + < 787200 729600 >, + < 902400 844800 >, + < 1017600 940800 >, + < 1132800 1036800 >, + < 1248000 1132800 >, + < 1344000 1248000 >, + < 1574400 1440000 >, + < 1804800 1555200 >, + < 1920000 1651200 >, + < 2035200 1843200 >, + < 2265600 2035200 >; + }; + + gold { + qcom,cpufreq-memfreq-tbl = + < 499200 307200 >, + < 614400 499200 >, + < 960000 844800 >, + < 1190400 1036800 >, + < 1401600 1248000 >, + < 1920000 1440000 >, + < 2572800 1651200 >, + < 2764800 1843200 >, + < 3187200 2035200 >; + }; + + prime { + qcom,cpufreq-memfreq-tbl = + < 499200 307200 >, + < 614400 499200 >, + < 960000 844800 >, + < 1190400 1036800 >, + < 1401600 1248000 >, + < 1920000 1440000 >, + < 2572800 1651200 >, + < 2764800 1843200 >, + < 3187200 2035200 >; + }; + + prime-compute { + qcom,cpufreq-memfreq-tbl = + < 2131200 307200 >, + < 3187200 2035200 >; + }; + }; + + ddrqos { + gold { + qcom,cpufreq-memfreq-tbl = + < 1920000 0 >, + < 3187200 1 >; + }; + + prime { + qcom,cpufreq-memfreq-tbl = + < 1401600 0 >, + < 3187200 1 >; + }; + + prime-latfloor { + qcom,cpufreq-memfreq-tbl = + < 2131200 0 >, + < 3187200 1 >; + }; + }; +}; diff --git a/qcom/pineapple.dts b/qcom/pineapple.dts new file mode 100644 index 00000000..69d2077b --- /dev/null +++ b/qcom/pineapple.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "pineapple.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Pineapple SoC"; + compatible = "qcom,pineapple"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi new file mode 100644 index 00000000..bbc26e73 --- /dev/null +++ b/qcom/pineapple.dtsi @@ -0,0 +1,3645 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. Pineapple"; + compatible = "qcom,pineapple"; + qcom,msm-id = <557 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + + chosen: chosen { + bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=y ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2"; + stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8"; + }; + + aliases: aliases { + serial0 = &qupv3_se15_2uart; + hsuart0 = &qupv3_se14_4uart; + sdhc2 = &sdhc_2; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + + firmware: firmware { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF_CL0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF_CL0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + qcom,freq-domain = <&cpufreq_hw 3>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 3>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + next-level-cache = <&L2_2>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL1>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 3>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL2>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL2>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF_CL3>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + core2 { + cpu = <&CPU4>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU5>; + }; + core1 { + cpu = <&CPU6>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + SILVER_OFF_CL0: silver-cluster0-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF_CL1: gold-cluster1-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF_CL2: gold-cluster2-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF_CL3: gold-plus-cluster3-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x41000044>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + arm,psci-suspend-param = <0x4100c344>; + }; +}; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + disp_rdump_region { + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>; + }; + }; + + slimbam: bamdma@6C04000 { + compatible = "qcom,bam-v1.7.0"; + qcom,controlled-remotely; + reg = <0x6C04000 0x20000>, <0x6C8F000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + num-channels = <31>; + interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@6C40000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x6C40000 0x2C000>, <0x6C8E000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x490>; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + ranges; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + interrupts = ; + + #address-cells = <1>; + #size-cells = <1>; + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17140000 0x20000>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + pcie_crm_hw_0_bcm_voter: bcm_voter@0 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "pcie_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <5>; + }; + + pcie_crm_hw_1_bcm_voter: bcm_voter@1 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "pcie_crm"; + qcom,crm-client-idx = <1>; + qcom,crm-pwr-states = <5>; + }; + + clk_virt: interconnect@0 { + compatible = "qcom,pineapple-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&pcie_crm_hw_1_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,pineapple-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", + "disp", + "cam_ife_0", + "cam_ife_1", + "cam_ife_2", + "pcie_crm_hw_0", + "pcie_crm_hw_1"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&disp_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>, + <&pcie_crm_hw_0_bcm_voter>, + <&pcie_crm_hw_1_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,pineapple-cnoc_cfg"; + reg = <0x1600000 0x6200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,pineapple-cnoc_main"; + reg = <0x1500000 0x14080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,pineapple-system_noc"; + reg = <0x1680000 0x1D080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,pineapple-pcie_anoc"; + reg = <0x16c0000 0x12200>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>, + <&pcie_crm_hw_1_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,pineapple-aggre1_noc"; + reg = <0x16E0000 0x16400>; + #interconnect-cells = <1>; + clocks = + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,pineapple-aggre2_noc"; + reg = <0x1700000 0x1E400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,pineapple-mmss_noc"; + reg = <0x1780000 0x5B800>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&disp_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,pineapple-gem_noc"; + reg = <0x24100000 0xC5080>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_CPUSS_UBWCP_CLK_SRC>; + clock-names = "gcc_ddrss_ubwcp_clk"; + qcom,bcm-voter-names = "hlos", + "disp", + "cam_ife_0", + "cam_ife_1", + "cam_ife_2", + "pcie_crm_hw_0", + "pcie_crm_hw_1"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&disp_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>, + <&pcie_crm_hw_0_bcm_voter>, + <&pcie_crm_hw_1_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,pineapple-nsp_noc"; + reg = <0x320C0000 0xF080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,pineapple-lpass_ag_noc"; + reg = <0x7e40000 0xE080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,pineapple-lpass_lpiaon_noc"; + reg = <0x7400000 0x19080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible = "qcom,pineapple-lpass_lpicx_noc"; + reg = <0x7430000 0x3A200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pineapple-pdc", "qcom,pdc"; + reg = <0xb220000 0x30000>, <0x174000f0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>, <143 244 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + pcie_pdc: pdc@b350000 { + compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc"; + reg = <0xb350000 0x20000>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,pineapple-pinctrl"; + reg = <0x0F000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + qcom,gpios-reserved = <36 37 38 39>; + }; + + show_resume_irqs@17100000 { + compatible = "qcom,show-resume-irqs"; + reg = <0x17100000 0x290000>; + }; + + dload_mode { + compatible = "qcom,dload-mode"; + }; + + mini_dump_mode { + compatible = "qcom,minidump"; + status = "ok"; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + + logbuf: qcom,logbuf-vendor-hooks { + compatible = "qcom,logbuf-vendor-hooks"; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x17a00000 0x10000>, + <0x17a10000 0x10000>, + <0x17a20000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + interrupts = , + , + ; + power-domains = <&CLUSTER_PD>; + + apps_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0xd00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,pineapple-rpmh-clk"; + #clock-cells = <1>; + }; + + dcvs_fp: qcom,dcvs-fp { + compatible = "qcom,dcvs-fp"; + qcom,ddr-bcm-name = "MC4"; + qcom,llcc-bcm-name = "SH5"; + }; + }; + }; + + cam_rsc: rsc@add9000 { + label = "cam_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xadd4000 0x1000>, + <0xadd5000 0x1000>, + <0xadd6000 0x1000>; + reg-names = "drv-0", "drv-1", "drv-2"; + qcom,drv-count = <3>; + qcom,hw-channel; + interrupts = , + , + ; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + + cam_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x520>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + + cam_bcm_voter0: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; + }; + + cam_rsc_drv1: drv@1 { + qcom,drv-id = <1>; + qcom,tcs-offset = <0x520>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + + cam_bcm_voter1: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; + }; + + cam_rsc_drv2: drv@2 { + qcom,drv-id = <2>; + qcom,tcs-offset = <0x520>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + channel@1 { + qcom,tcs-config = , + , + , + , + ; + }; + + cam_bcm_voter2: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + qcom,drv-count = <1>; + interrupts = ; + clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + + disp_rsc_drv0: drv@0 { + qcom,drv-id = <0>; + qcom,tcs-offset = <0x1c00>; + channel@0 { + qcom,tcs-config = , + , + , + , + ; + }; + + disp_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,tcs-wait = ; + qcom,no-amc; + }; + }; + }; + + cam_crm: crm@add7000 { + label = "cam_crm"; + compatible = "qcom,cam-crm"; + reg = <0xadd7000 0x2000>; + reg-names = "base"; + interrupts = ; + interrupt-names = "cam_crm"; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2>; + qcom,sw-drv-ids = <0>; + }; + + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm"; + reg = <0x1d01000 0x3000>; + reg-names = "base"; + interrupts = ; + interrupt-names = "pcie_crm"; + clocks = <&pcie_0_pipe_clk>; + qcom,hw-drv-ids = <0 1>; + qcom,sw-drv-ids = <0>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x14680000 0x1000>; + ranges = <0x0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + /* PIL spss node - for loading Secure Processor */ + spss_pas: remoteproc-spss@1880000 { + compatible = "qcom,pineapple-spss-pas"; + ranges; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1881100 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", + "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; + interrupts = <0 352 1>; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + status = "ok"; + + memory-region = <&spss_region_mem>; + qcom,spss-scsr-bits = <24 25>; + qcom,extra-size = <4096>; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + glink-edge { + qcom,remote-pid = <8>; + mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "spss_spss"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + }; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + qcom,rproc-handle = <&spss_pas>; + qcom,boot-enabled; + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; + /* sp2soc rmb shared register physical address and bmsk */ + qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>; + qcom,spcom-sp2soc-rmb-initdone-bit = <24>; + qcom,spcom-sp2soc-rmb-pbldone-bit = <25>; + /* soc2sp rmb shared register physical address */ + qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>; + qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>; + status = "ok"; + }; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss fuses physical address */ + qcom,rproc-handle = <&spss_pas>; + qcom,spss-fuse1-addr = <0x221C8214>; + qcom,spss-fuse1-bit = <8>; + qcom,spss-fuse2-addr = <0x221C8214>; + qcom,spss-fuse2-bit = <7>; + qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-debug-reg-addr1 = <0x01888020>; + qcom,spss-debug-reg-addr3 = <0x0188C020>; + qcom,spss-emul-type-reg-addr = <0x01fc8004>; + pil-mem = <&spss_region_mem>; + qcom,pil-size = <0x0F0000>; // padding to 960KB + status = "ok"; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + + qcom,client_4 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x1000000>; + qcom,client-id = <5>; + qcom,allocate-on-request; + qcom,shared; + memory-region = <&qmc_dma_mem>; + label = "modem"; + }; + + qcom,client_5 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x400000>; + qcom,client-id = <6>; + qcom,allocate-on-request; + qcom,shared; + label = "modem"; + }; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "sleep_clk"; + #clock-cells = <0>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_phy_aux_clk: pcie_1_phy_aux_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_phy_aux_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_0_clk"; + #clock-cells = <0>; + }; + + ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_rx_symbol_1_clk"; + #clock-cells = <0>; + }; + + ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "ufs_phy_tx_symbol_0_clk"; + #clock-cells = <0>; + }; + + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <0>; + }; + }; + + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>, + <0x178c0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v3"; + reg = <0x0c3f0000 0x400>; + qcom,qmp = <&aoss_qmp>; + ss-name = "modem", "adsp", "adsp_island", + "cdsp", "apss"; + }; + + camcc_crmc: syscon@adda000 { + compatible = "syscon"; + reg = <0xadda000 0x2000>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,pineapple-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; + qcom,cam_crm-crmc = <&camcc_crmc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,pineapple-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@100000 { + compatible = "qcom,pineapple-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mxa-supply = <&VDD_MXA_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&pcie_0_pipe_clk>, + <&pcie_1_phy_aux_clk>, + <&pcie_1_pipe_clk>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "pcie_0_pipe_clk", + "pcie_1_phy_aux_clk", + "pcie_1_pipe_clk", + "sleep_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,pineapple-gpucc", "syscon"; + reg = <0x3d90000 0x9800>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gpll0_out_main", + "gpll0_out_main_div"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsrcc: clock-controller@1f40000 { + compatible = "qcom,pineapple-tcsrcc", "syscon"; + reg = <0x1f40000 0xc0000>; + reg-name = "cc_base"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,pineapple-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_MM_LEVEL>; + vdd_mxc-supply = <&VDD_MXC_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apsscc: syscon@17a80000 { + compatible = "syscon"; + reg = <0x17a80000 0x21000>; + }; + + mccc: syscon@240ba000 { + compatible = "syscon"; + reg = <0x240ba000 0x54>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,pineapple-debugcc"; + qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; + qcom,videocc = <&videocc>; + qcom,dispcc = <&dispcc>; + qcom,camcc = <&camcc>; + qcom,apsscc = <&apsscc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-epss"; + reg = <0x17D91000 0x1000>, + <0x17D92000 0x1000>, + <0x17D93000 0x1000>, + <0x17D94000 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2", + "freq-domain3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + , + , + ; + interrupt-names = "dcvsh0_int", + "dcvsh1_int", + "dcvsh2_int", + "dcvsh3_int"; + #freq-domain-cells = <1>; + }; + + qcom,cpufreq-hw-debug { + compatible = "qcom,cpufreq-hw-epss-debug"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, + <&cpufreq_hw 1>, + <&cpufreq_hw 2>, + <&cpufreq_hw 3>; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <80000 50000>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <80000 50000>; + }; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* + * DLL HSR settings. Refer go/hsr - DLL settings. + * Note that the DLL_CONFIG_2 value is not passed from the + * device tree, but it is calculated in the driver. + */ + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 + 0x090106C0 0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc + SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ice_cfg: shared_ice { + alg1 { + alg-name = "alg1"; + rx-alloc-percent = <60>; + status = "disabled"; + }; + + alg2 { + alg-name = "alg2"; + status = "disabled"; + + }; + + alg3 { + alg-name = "alg3"; + num-core = <28 28 15 13>; + status = "ok"; + }; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>, + <0x1d90000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x0f>; + qcom,esi-affinity-mask = <0xf0>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <30>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <14752 0>, <1000 0>, /* PWM G5 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <29504 0>, <1000 0>, /* PWM G5 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <5836800 0>, <819200 0>, /* HS G5 RA L2*/ + <5836800 0>, <819200 0>, /* HS G5 RB L2 */ + <7643136 0>, <819200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "HS_RA_G5_L2", "HS_RB_G5_L2", + "MAX"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "fastmap"; + shared-ice-cfg = <&ice_cfg>; + dma-coherent; + + qcom,bypass-pbl-rst-wa; + + status = "disabled"; + + qos0 { + mask = <0xfc>; + vote = <44>; + perf; + cpu_freq_vote = <2 5 7>; + }; + + qos1 { + mask = <0x03>; + vote = <44>; + cpu_freq_vote = <0>; + }; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x400000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + thermal_zones: thermal-zones { + }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi1_bus: qcom,spmi@c432000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc432000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4d0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <1>; + depends-on-supply = <&spmi0_bus>; + status = "disabled"; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + depends-on2-supply = <&pm8550b_glink_debug>; + + qcom,pmk8550-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550vs-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550vs-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550vs-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550vs-debug@6 { + compatible = "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550b-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8550ve-debug@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmr735d-debug@a { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8010-debug@c { + compatible = "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8010-debug@d { + compatible = "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + qcom_tzlog: tz-log@14680720 { + compatible = "qcom,tz-log"; + reg = <0x14680720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x28000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,offload-ops-support; + qcom,bam-pipe-offload-cpb-hlos = <1>; + qcom,bam-pipe-offload-hlos-cpb = <3>; + qcom,bam-pipe-offload-hlos-hlos = <4>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0480 0x0>, + <&apps_smmu 0x0481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0481 0x0>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x0483 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + dma-coherent; + }; + }; + + qcom_rng: qrng@10c3000 { + compatible = "qcom,msm-rng"; + reg = <0x10c3000 0x1000>; + qcom,no-qrng-config; + qcom,no-clock-support; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + cache-controller@25000000 { + compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; + reg = <0x25000000 0x800000> , <0x25800000 0x200000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + cap-based-alloc-and-pwr-collapse; + + llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupt-parent = <&pdc>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x088E0000 0x2000>, + <0x088E2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-utmi-delay = /bits/ 16 <255>; + status = "ok"; + }; + + ipcc_mproc: qcom,ipcc@406000 { + compatible = "qcom,ipcc"; + reg = <0x406000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + aoss_qmp: power-controller@c300000 { + compatible = "qcom,aoss-qmp"; + reg = <0xc300000 0x400>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + qmp_aop: qcom,qmp-aop { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qmp_tme: qcom,qmp-tme { + compatible = "qcom,qmp-mbox"; + qcom,remote-pid = <14>; + mboxes = <&ipcc_mproc IPCC_CLIENT_TME + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "tme_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "tme"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-qmc-dma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_dma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-qmc-cma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_cma"; + qcom,glinkpkt-enable-ch-close; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + label = "spss"; + }; + }; + + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple"; + reg = <0xc320000 0x0400>; + qcom,qmp = <&aoss_qmp>; + }; + + adsp_sleepmon: adsp-sleepmon { + compatible = "qcom,adsp-sleepmon"; + qcom,rproc-handle = <&adsp_pas>; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 + 0x17840058 0x17850058 0x17860058 0x17870058>; + qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 + 0x17840060 0x17850060 0x17860060 0x17870060>; + }; + + adsp_pas: remoteproc-adsp@03000000 { + compatible = "qcom,pineapple-adsp-pas"; + reg = <0x03000000 0x10000>; + status = "ok"; + + cx-supply = <&VDD_LPI_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_LPI_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + memory-region = <&adsp_slpi_mem &q6_adsp_dtb_mem>; + + /* Inputs from ssc */ + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + }; + + modem_pas: remoteproc-mss@04080000 { + compatible = "qcom,pineapple-modem-pas"; + reg = <0x4080000 0x10000>; + status = "ok"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MODEM_LEVEL>; + mx-uV-uA = ; + reg-names = "cx", "mx"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma>; + mpss_dsm_mem_reg = <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; + }; + + cdsp_pas: remoteproc-cdsp@32300000 { + compatible = "qcom,pineapple-cdsp-pas"; + reg = <0x32300000 0x10000>; + status = "ok"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MXC_LEVEL>; + mx-uV-uA = ; + nsp-supply = <&VDD_NSP1_LEVEL>; + nsp-uV-uA = ; + reg-names = "cx","mx","nsp"; + + memory-region = <&cdsp_mem &q6_cdsp_dtb_mem>; + global-sync-mem-reg = <&global_sync_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,signal-aop; + qcom,qmp = <&aoss_qmp>; + + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "rproc_ddr", "crypto_ddr"; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1>; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + }; + + spss_pas: remoteproc-spss@1880000 { + compatible = "qcom,pineapple-spss-pas"; + ranges; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1881100 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask", + "rmb_err", "rmb_general_purpose", "rmb_err_spare2"; + interrupts = <0 352 1>; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + status = "ok"; + + memory-region = <&spss_region_mem>; + qcom,spss-scsr-bits = <24 25>; + qcom,extra-size = <4096>; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + glink-edge { + qcom,remote-pid = <8>; + mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "spss_spss"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + }; + }; + + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + /* keep silver core only to avoid wakeup of gold cores */ + qcom,gic-class0-cpus = <0 1>; + /* keep gold and gold+ cores in class1 */ + qcom,gic-class1-cpus = <2 3 4 5 6 7>; + }; + + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + + qti,smmu-proxy { + compatible = "smmu-proxy-sender"; + }; + + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + qcom,master; + tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0 &tlmm 49 0 + &tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0 &tlmm 91 0 + &tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0 &tlmm 88 0>; + }; + + tlmm-vm-test { + compatible = "qcom,tlmm-vm-test"; + qcom,master; + tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0 &tlmm 49 0 + &tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0 &tlmm 91 0 + &tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0 &tlmm 88 0>; + }; + + cpusys-vm-shmem-access { + compatible = "qcom,cpusys-vm-shmem-access"; + gunyah-label = <5>; + peer-name = <3>; + shared-buffer = <&hwfence_shbuf>; + }; + + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x10>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb { + size = <0x100000>; + gunyah-label = <0x12>; + }; + + trust_ui_vm: qcom,trust_ui_vm { + vm_name = "trustedvm"; + shared-buffers-size = <0x108000>; + shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_vblk1_ring &trust_ui_vm_swiotlb>; + }; + + oem_vm_vblk0_ring: oem_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x13>; + }; + + oem_vm_swiotlb: oem_vm_swiotlb { + size = <0x100000>; + gunyah-label = <0x14>; + }; + + oem_vm: qcom,oem_vm { + vm_name = "oemvm"; + shared-buffers-size = <0x104000>; + shared-buffers = <&oem_vm_vblk0_ring &oem_vm_swiotlb>; + }; + + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x10>; + }; + + gh-rm-booster { + compatible = "qcom,gh-rm-booster"; + qcom,rm-vmid = <255>; + qcom,rm-affinity-default = <0>; + }; + + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + memory-region = <&trust_ui_vm_mem &vm_comm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0 &trust_ui_vm_virt_be1>; + }; + + oem_vm_virt_be0: oem_vm_virt_be0@13 { + qcom,vm = <&oem_vm>; + qcom,label = <0x13>; + }; + + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <34>; + qcom,vmid = <49>; + qcom,firmware-name = "oemvm"; + memory-region = <&oem_vm_mem &vm_comm_mem>; + virtio-backends = <&oem_vm_virt_be0>; + }; + + gh-secure-vm-loader@2 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + qcom,rproc-handle = <&cdsp_pas>; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + + qcom,test-dbl { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,pmic_glink { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + /* Primary SPMI bus */ + spmi@0 { + reg = <0>; + #address-cells = <2>; + #size-cells = <0>; + + pm8550b_glink_debug: qcom,pm8550b-debug@7 { + compatible = "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + qcom,can-sleep; + }; + }; + }; + + pmic_glink_adc: qcom,glink-adc { + compatible = "qcom,glink-adc"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; + + qcom,test-msgq { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <4>; + qcom,primary; + }; + + qcom,gh-qtimer@17425000 { + compatible = "qcom,gh-qtmr"; + reg = <0x17425000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,primary; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { }; + + mmio_sram: mmio-sram@17D09400 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09400 0x0 0x400>; + ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>; + + cpu_scp_lpri: scmi-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x17D09400 0x0 0x400>; + }; + }; + + cpucp: qcom,cpucp@17400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,cpucp"; + reg = <0x17400000 0x10>, + <0x17d90000 0x2000>; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_memlat: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + + scmi_plh: protocol@81 { + reg = <0x81>; + #clock-cells = <1>; + }; + + scmi_pmu: protocol@86 { + reg = <0x86>; + #clock-cells = <1>; + }; + + scmi_c1dcvs: protocol@87 { + reg = <0x87>; + #clock-cells = <1>; + }; + + }; + + cpucp_log: qcom,cpucp_log@d8140000 { + compatible = "qcom,cpucp-log"; + reg = <0xd8040000 0x10000>, <0xd8050000 0x10000>; + mboxes = <&cpucp 1>; + }; + + qcom_c1dcvs: qcom,c1dcvs { + compatible = "qcom,c1dcvs-v2"; + }; + + qcom_mpam: qcom,mpam { + compatible = "qcom,mpam"; + }; + + qcom_cpufreq_stats: qcom,cpufreq_stats { + compatible = "qcom,cpufreq-stats-v2"; + }; + + llcc_pmu: llcc-pmu@24095000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x24095000 0x300>; + reg-names = "lagg-base"; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + qcom,long-counter; + reg = <0x17d09880 0x380>; + reg-names = "pmu-base"; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0x02 0x02 >, + < 0x0011 0xFF 0x01 0x00 >, + < 0x0017 0xFF 0xFF 0x04 >, + < 0x0037 0xFF 0xFF 0x06 >, + < 0x1000 0xFF 0xFF 0x08 >; + }; + + ddr_freq_table: ddr-freq-table { + qcom,freq-tbl = + < 547000 >, + < 768000 >, + < 1555000 >, + < 1708000 >, + < 2092000 >, + < 2736000 >, + < 3187000 >, + < 3686000 >, + < 4224000 >; + }; + + llcc_freq_table: llcc-freq-table { + qcom,freq-tbl = + < 300000 >, + < 466000 >, + < 600000 >, + < 806000 >, + < 933000 >, + < 1066000 >; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>; + }; + + ddr_dcvs_fp: fp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <1>; + qcom,fp-voter = <&dcvs_fp>; + }; + }; + + qcom_llcc_dcvs_hw: llcc { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <1>; + qcom,bus-width = <16>; + qcom,freq-tbl = <&llcc_freq_table>; + + llcc_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + }; + + llcc_dcvs_fp: fp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <1>; + qcom,fp-voter = <&dcvs_fp>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>; + }; + }; + + qcom_ubwcp_dcvs_hw: ubwcp { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <4>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ubwcp_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_UBWC_P + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_fp>; + qcom,miss-ev = <0x1000>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,cpufreq-memfreq-tbl = + < 1132800 547000 >, + < 1536000 768000 >, + < 2131200 1555000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>; + qcom,cpufreq-memfreq-tbl = + < 576000 547000 >, + < 902400 768000 >, + < 1152000 1555000 >, + < 1382400 2092000 >, + < 1958400 2736000 >, + < 2515200 3686000 >, + < 3187200 4224000 >; + qcom,sampling-enabled; + }; + + prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 576000 547000 >, + < 902400 768000 >, + < 1152000 1555000 >, + < 1382400 2092000 >, + < 1958400 2736000 >, + < 2515200 3686000 >, + < 3187200 4224000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2073600 547000 >, + < 3187200 2092000 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + + prime-latfloor { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2515200 547000 >, + < 3187200 4224000 >; + qcom,sampling-enabled; + }; + }; + + llcc { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + qcom,sampling-path = <&llcc_dcvs_fp>; + qcom,miss-ev = <0x37>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,cpufreq-memfreq-tbl = + < 902400 300000 >, + < 1536000 466000 >, + < 2131200 600000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 576000 300000 >, + < 1152000 466000 >, + < 1382400 600000 >, + < 1958400 806000 >, + < 2515200 933000 >, + < 3187200 1066000 >; + qcom,sampling-enabled; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2073600 300000 >, + < 3187200 600000 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,cpufreq-memfreq-tbl = + < 307200 307200 >, + < 460800 384000 >, + < 556800 595200 >, + < 787200 710400 >, + < 902400 806400 >, + < 1017600 921600 >, + < 1132800 1017600 >, + < 1344000 1132800 >, + < 1536000 1363200 >, + < 1651200 1459200 >, + < 1747200 1555200 >, + < 1939200 1651200 >, + < 2131200 1728000 >; + qcom,sampling-enabled; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>; + qcom,cpufreq-memfreq-tbl = + < 460800 307200 >, + < 576000 595200 >, + < 902400 806400 >, + < 1152000 1017600 >, + < 1382400 1132800 >, + < 1843200 1363200 >, + < 2073600 1459200 >, + < 2515200 1555200 >, + < 3187200 1728000 >; + qcom,sampling-enabled; + }; + + prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 460800 307200 >, + < 576000 595200 >, + < 902400 806400 >, + < 1152000 1017600 >, + < 1382400 1132800 >, + < 1843200 1363200 >, + < 2073600 1459200 >, + < 2515200 1555200 >, + < 3187200 1728000 >; + qcom,sampling-enabled; + }; + + prime-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2073600 307200 >, + < 3187200 1728000 >; + qcom,sampling-enabled; + qcom,compute-mon; + }; + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x1000>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,cpufreq-memfreq-tbl = + < 1958400 0 >, + < 3187200 1 >; + qcom,sampling-enabled; + }; + + ddrqos_prime_lat: prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 1382400 0 >, + < 3187200 1 >; + qcom,sampling-enabled; + }; + + ddrqos_prime_latfloor: prime-latfloor { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,cpufreq-memfreq-tbl = + < 2073600 0 >, + < 3187200 1 >; + qcom,sampling-enabled; + }; + }; + }; + + bwmon_llcc: qcom,bwmon-llcc@240B7300 { + compatible = "qcom,bwmon4"; + reg = <0x240B7400 0x300>, <0x240B7300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + }; + + bwmon_ddr: qcom,bwmon-ddr@24091000 { + compatible = "qcom,bwmon5"; + reg = <0x24091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + }; + + bwmon_ubwcp: qcom,bwmon-ubwcp@240B5200 { + compatible = "qcom,bwmon4"; + reg = <0x240B5300 0x300>, <0x240B5200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ubwcp_dcvs_hw>; + }; + + google,debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&kinfo_mem>; + }; + + dmesg-dump { + compatible = "qcom,dmesg-dump"; + qcom,primary-vm; + gunyah-label = <7>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + + qcom,qrtr-mhi-cnss { + compatible = "qcom,qrtr-mhi"; + qcom,dev-id = <0x1107>; + qcom,net-id = <0>; + qcom,low-latency; + }; + + qcom,qrtr-gunyah-tuivm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; + }; + + qcom,qrtr-gunyah-oemvm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <8>; + peer-name = <4>; + }; + + qcom,health_monitor { + compatible = "qcom,system-health-monitor"; + + qcom,modem { + qcom,subsys-name = "msm_mpss"; + qcom,ssrestart-string = "mpss"; + qcom,rproc_phandle = <&modem_pas>; + }; + }; + + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + qcom,primary-vm; + gunyah-label = <9>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + + qfprom: qfprom@221c2000 { + compatible = "qcom,qfprom"; + reg = <0x221c2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@9b { + reg = <0x9b 0x1>; + bits = <4 3>; + }; + }; +}; + +&firmware { + qcom_scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah_hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0xe00000>; + }; + + cpusys_vm_mem: cpusys_vm_region@80e00000 { + no-map; + reg = <0x0 0x80e00000 0x0 0x400000>; + }; + + /* + * hyp_tags_mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + /* hyp_reserved_mem doesn't correspond to an actual region. */ + + /* merged xbl_dtlog, xbl_ramdump and aop_image regions */ + xbl_aop_merged_mem: xbl_aop_merged_region@81a00000 { + no-map; + reg = <0x0 0x81a00000 0x0 0x260000>; + }; + + aop_cmd_db_mem: aop_cmd_db_region@81c60000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x81c60000 0x0 0x20000>; + }; + + /* merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + aop_tme_uefi_merged_mem: aop_tme_uefi_merged_region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x74000>; + }; + + /* secdata region can be reused by apps */ + + smem_mem: smem_region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp_mhi_region@81f00000 { + no-map; + reg = <0x0 0x81f00000 0x0 0x20000>; + }; + + pvmfw_mem: pvmfw_region@0x824a0000 { + no-map; + reg = <0x0 0x824a0000 0x0 0x100000>; + }; + + /* hyp_mem_database_mem is removed by HYP in the RAM partition table */ + + global_sync_mem: global_sync_region@82600000 { + no-map; + reg = <0x0 0x82600000 0x0 0x100000>; + }; + + tz_stat_mem: tz_stat_region@82700000 { + no-map; + reg = <0x0 0x82700000 0x0 0x100000>; + }; + + qdss_mem: qdss_region@82800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_dsm_mem: mpss_dsm_region@86b00000 { + no-map; + reg = <0x0 0x86b00000 0x0 0x4900000>; + }; + + mpss_dsm_mem_2: mpss_dsm_region_2@8b400000 { + no-map; + reg = <0x0 0x8b400000 0x0 0x800000>; + }; + + mpss_mem: mpss_region@8bc00000 { + no-map; + reg = <0x0 0x8bc00000 0x0 0xf400000>; + }; + + q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 { + no-map; + reg = <0x0 0x9b000000 0x0 0x80000>; + }; + + ipa_fw_mem: ipa_fw_region@9b080000 { + no-map; + reg = <0x0 0x9b080000 0x0 0x10000>; + }; + + ipa_gsi_mem: ipa_gsi_region@9b090000 { + no-map; + reg = <0x0 0x9b090000 0x0 0xa000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qmc_dma_mem: qmc_dma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0xa400000>; + alignment = <0x0 0x400000>; + }; + + gpu_micro_code_mem: gpu_microcode_region@9b09a000 { + no-map; + reg = <0x0 0x9b09a000 0x0 0x2000>; + }; + + spss_region_mem: spss_region_region@9b100000 { + no-map; + reg = <0x0 0x9b100000 0x0 0x180000>; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu_secure_shared_memory_region@9b280000 { + no-map; + reg = <0x0 0x9b280000 0x0 0x60000>; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu_secure_shared_memory_region@9b2e0000 { + no-map; + reg = <0x0 0x9b2e0000 0x0 0x20000>; + }; + + camera_mem: camera_region@9b300000 { + no-map; + reg = <0x0 0x9b300000 0x0 0x800000>; + }; + + video_mem: video_region@9bb00000 { + no-map; + reg = <0x0 0x9bb00000 0x0 0x800000>; + }; + + cvp_mem: cvp_region@9c300000 { + no-map; + reg = <0x0 0x9c300000 0x0 0x700000>; + }; + + cdsp_mem: cdsp_region@9ca00000 { + no-map; + reg = <0x0 0x9ca00000 0x0 0x2000000>; + }; + + q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9ea00000 { + no-map; + reg = <0x0 0x9ea00000 0x0 0x80000>; + }; + + q6_adsp_dtb_mem: q6_adsp_dtb_region@9ea80000 { + no-map; + reg = <0x0 0x9ea80000 0x0 0x80000>; + }; + + adsp_slpi_mem: adspslpi_region@9eb00000 { + no-map; + reg = <0x0 0x9eb00000 0x0 0x4080000>; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + /* merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ + tz_merged_mem: tz_merged_region@d8000000 { + no-map; + reg = <0x0 0xd8000000 0x0 0x800000>; + }; + + /* + * ta/tags mem is dynamically removed from the RAM + * partition tables before boot occurs. Size of region + * varies. + */ + + hwfence_shbuf: hwfence-shmem { + no-map; + reg = <0x0 0xe6440000 0x0 0x2dd000>; + }; + + vm_comm_mem: vm_comm_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + trust_ui_vm_mem: trust_ui_vm_region@f3800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf3800000 0x0 0x4400000>; + reusable; + alignment = <0x0 0x400000>; + }; + + oem_vm_mem: oem_vm_region@f7c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + reusable; + alignment = <0x0 0x400000>; + }; + + llcc_lpi_mem: llcc_lpi_region@ff800000 { + no-map; + reg = <0x0 0xff800000 0x0 0x600000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_eva_mem: cdsp_eva_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x4800000>; + }; + + kinfo_mem: debug_kinfo_region { + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x1000>; + no-map; + }; + + ramoops_mem: ramoops_region { + compatible = "ramoops"; + alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>; + size = <0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; +}; + +#include "ipcc-test.dtsi" +#include "pineapple-gdsc.dtsi" +#include "pineapple-pinctrl.dtsi" +#include "pineapple-regulators.dtsi" +#include "msm-arm-smmu-pineapple.dtsi" +#include "pineapple-debug.dtsi" +//#include "pineapple-dma-heaps.dtsi" +#include "pineapple-qupv3.dtsi" +#include "pineapple-usb.dtsi" +#include "pineapple-coresight.dtsi" +#include "pineapple-pcie.dtsi" +#include "msm-rdbg.dtsi" +#include "pineapple-thermal.dtsi" + +&qupv3_se15_2uart { + status = "ok"; +}; + +&qupv3_se3_i2c { + status = "ok"; + wcd_usbss: wcd939x_i2c@e { + compatible = "qcom,wcd939x-i2c"; + reg = <0xe>; + vdd-usb-cp-supply = <&L15B>; + }; +}; + +&cam_cc_bps_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_ife_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_ife_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_ife_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_sbi_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_sfe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_sfe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_sfe_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&cam_cc_titan_top_gdsc>; + status = "ok"; +}; + +&cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + interconnect-names = "mmnoc"; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; + status = "ok"; +}; + +&disp_cc_mdss_core_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MM_LEVEL>; + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + clocks = <&gcc GCC_DISP_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_MM_LEVEL>; + status = "ok"; +}; + +&apss_ubwcp_pwr_ctrl { + status = "ok"; +}; + +&gcc_pcie_0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_pcie_0_phy_gdsc { + parent-supply = <&VDD_MXA_LEVEL>; + status = "ok"; +}; + +&gcc_pcie_1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_pcie_1_phy_gdsc { + parent-supply = <&VDD_MXA_LEVEL>; + status = "ok"; +}; + +&gcc_ufs_mem_phy_gdsc { + parent-supply = <&VDD_MXA_LEVEL>; + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_usb3_phy_gdsc { + parent-supply = <&VDD_MXA_LEVEL>; + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; + status = "ok"; +}; + +&video_cc_mvs1_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; + status = "ok"; +}; + +&video_cc_mvs1c_gdsc { + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; + status = "ok"; +}; diff --git a/qcom/pineapplep-v2.dts b/qcom/pineapplep-v2.dts new file mode 100644 index 00000000..65d2a070 --- /dev/null +++ b/qcom/pineapplep-v2.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "pineapplep-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. PineappleP v2 SoC"; + compatible = "qcom,pineapplep"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/pineapplep-v2.dtsi b/qcom/pineapplep-v2.dtsi new file mode 100644 index 00000000..4359d671 --- /dev/null +++ b/qcom/pineapplep-v2.dtsi @@ -0,0 +1,7 @@ +#include "pineapple-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. PineappleP v2 SoC"; + compatible = "qcom,pineapplep"; + qcom,msm-id = <577 0x20000>; +}; diff --git a/qcom/pineapplep.dts b/qcom/pineapplep.dts new file mode 100644 index 00000000..46677ba3 --- /dev/null +++ b/qcom/pineapplep.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "pineapplep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. PineappleP SoC"; + compatible = "qcom,pineapplep"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/pineapplep.dtsi b/qcom/pineapplep.dtsi new file mode 100644 index 00000000..9e790611 --- /dev/null +++ b/qcom/pineapplep.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "pineapple.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. PineappleP SoC"; + compatible = "qcom,pineapplep"; + qcom,msm-id = <577 0x10000>; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 8e427ad3..472a9388 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -12,6 +12,33 @@ _platform_map = { {"name": "sun-rumi-overlay.dtbo"}, ], }, + "pineapple": { + "dtb_list": [ + {"name": "pineapple.dtb"}, + {"name": "pineapple-v2.dtb"}, + { + "name": "pineapplep.dtb", + "apq": True, + }, + { + "name": "pineapplep-v2.dtb", + "apq": True, + }, + ], + "dtbo_list": [ + {"name": "pineapple-atp-overlay.dtbo"}, + {"name": "pineapple-cdp-nfc-overlay.dtbo"}, + {"name": "pineapple-cdp-overlay.dtbo"}, + {"name": "pineapple-mtp-nfc-overlay.dtbo"}, + {"name": "pineapple-mtp-overlay.dtbo"}, + {"name": "pineapple-qrd-overlay.dtbo"}, + {"name": "pineapple-rcm-overlay.dtbo"}, + { + "name": "pineapple-rumi-overlay.dtbo", + "apq": False, + }, + ], + }, } def _get_dtb_lists(target, dt_overlay_supported): diff --git a/qcom/pm8010.dtsi b/qcom/pm8010.dtsi new file mode 100644 index 00000000..555932f6 --- /dev/null +++ b/qcom/pm8010.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8010_m: qcom,pm8010@c { + compatible = "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010m_tz: pm8010m-temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n: qcom,pm8010@d { + compatible = "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010n_tz: pm8010n-temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; + +&thermal_zones { + pm8010m_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8010m_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8010n_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8010n_tz>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pm8550.dtsi b/qcom/pm8550.dtsi new file mode 100644 index 00000000..78eb9cb3 --- /dev/null +++ b/qcom/pm8550.dtsi @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8550@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_tz: pm8550-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: pinctrl@8800 { + compatible = "qcom,pm8550-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8550_pwm_1: pwms@e800 { + compatible = "qcom,pwm-lpg"; + reg = <0xe800>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <3>; + nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>; + nvmem-names = "lpg_chan_sdam", "lut_sdam"; + qcom,lut-sdam-base = <0x45>; + qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 + 90 80 70 60 50 40 30 20 10 0>; + qcom,tick-duration-us = <7800>; + + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <100>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pm8550_pwm_2: pwms@eb00 { + compatible = "qcom,pwm-lpg"; + reg = <0xeb00>; + reg-names = "lpg-base"; + pwm-cells = <2>; + qcom,num-lpg-channels = <1>; + }; + + pm8550_rgb: qcom,leds@ef00 { + compatible = "qcom,tri-led"; + reg = <0xef00>; + + red { + label = "red"; + pwms = <&pm8550_pwm_1 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + + green { + label = "green"; + pwms = <&pm8550_pwm_1 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + + blue { + label = "blue"; + pwms = <&pm8550_pwm_1 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pm8550_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>, + <0x1 0x47 0x1 IRQ_TYPE_NONE>, + <0x1 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + pm8550_flash: qcom,flash_led@ee00 { + compatible = "qcom,pm8350c-flash-led"; + reg = <0xee00>; + interrupts = <0x1 0xee 0x0 IRQ_TYPE_EDGE_RISING>, + <0x1 0xee 0x3 IRQ_TYPE_EDGE_RISING>, + <0x1 0xee 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,thermal-derate-current = <200 500>; + status = "disabled"; + + pm8550_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pm8550_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pm8550_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pm8550_flash3: qcom,flash_3 { + label = "flash"; + qcom,led-name = "led:flash_3"; + qcom,max-current-ma = <1500>; + qcom,default-led-trigger = "flash3_trigger"; + qcom,id = <3>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + }; + + pm8550_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,ires-ua = <12500>; + }; + + pm8550_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,ires-ua = <12500>; + }; + + pm8550_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,ires-ua = <12500>; + }; + + pm8550_torch3: qcom,torch_3 { + label = "torch"; + qcom,led-name = "led:torch_3"; + qcom,max-current-ma = <500>; + qcom,default-led-trigger = "torch3_trigger"; + qcom,id = <3>; + qcom,ires-ua = <12500>; + }; + + pm8550_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pm8550_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,default-led-trigger = "switch1_trigger"; + }; + + pm8550_switch2: qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,default-led-trigger = "switch2_trigger"; + }; + }; + }; +}; + +&thermal_zones { + pm8550_temp_alarm: pm8550_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550_tz>; + + trips { + pm8550_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550_bcl 5>; + + trips { + bcl_lvl0: bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8550-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550_bcl 6>; + + trips { + bcl_lvl1: bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8550-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550_bcl 7>; + + trips { + bcl_lvl2: bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8550b.dtsi b/qcom/pm8550b.dtsi new file mode 100644 index 00000000..43f8efaf --- /dev/null +++ b/qcom/pm8550b.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8550b@7 { + compatible = "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_tz: pm8550b-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550b_lite_tz: pm8550b-temp-alarm-lite@c00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xc00>; + interrupts = <0x7 0xc 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550b_gpios: pinctrl@8800 { + compatible = "qcom,pm8550b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8550b_haptics: qcom,hv-haptics@f000 { + compatible = "qcom,hv-haptics"; + reg = <0xf000>, <0xf100>, <0xf200>; + interrupts = <0x7 0xf0 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "fifo-empty"; + qcom,vmax-mv = <3600>; + qcom,brake-mode = ; + qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>; + qcom,lra-period-us = <6667>; + qcom,drv-sig-shape = ; + qcom,brake-sig-shape = ; + + hap_swr_slave_reg: qcom,hap-swr-slave-reg { + regulator-name = "hap-swr-slave-reg"; + }; + + effect_0 { + /* CLICK */ + qcom,effect-id = <0>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-pattern-preload; + qcom,wf-auto-res-disable; + }; + + effect_1 { + /* DOUBLE_CLICK */ + qcom,effect-id = <1>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_2 { + /* TICK */ + qcom,effect-id = <2>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_3 { + /* THUD */ + qcom,effect-id = <3>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_4 { + /* POP */ + qcom,effect-id = <4>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + effect_5 { + /* HEAVY CLICK */ + qcom,effect-id = <5>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>, + <0x03f S_PERIOD_T_LRA 0>, + <0x05f S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>, + <0x17f S_PERIOD_T_LRA 0>, + <0x15f S_PERIOD_T_LRA 0>, + <0x13f S_PERIOD_T_LRA 0>, + <0x11f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_0 { + /* NOOP */ + qcom,primitive-id = <0>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0 S_PERIOD_T_LRA 0>, + <0 S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_1 { + /* CLICK */ + qcom,primitive-id = <1>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_2 { + /* THUD */ + qcom,primitive-id = <2>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_3 { + /* SPIN */ + qcom,primitive-id = <3>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_4 { + /* QUICK_RISE */ + qcom,primitive-id = <4>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_5 { + /* SLOW_RISE */ + qcom,primitive-id = <5>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_6 { + /* QUICK_FALL */ + qcom,primitive-id = <6>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_7 { + /* LIGHT_TICK */ + qcom,primitive-id = <7>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + + primitive_8 { + /* LOW_TICK */ + qcom,primitive-id = <8>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <6667>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; + }; + + pm8550b_bcl: bcl@4700 { + compatible = "qcom,bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>, + <0x7 0x47 0x1 IRQ_TYPE_NONE>, + <0x7 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc: bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + + pm8550b_eusb2_repeater: qcom,eusb2-repeater@fd00 { + compatible = "qcom,pmic-eusb2-repeater"; + reg = <0xfd00>; + }; + }; +}; + +&thermal_zones { + pm8550b_temp_alarm: pm8550b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550b_tz>; + + trips { + pm8550b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550b_lite_temp_alarm: pm8550b_lite_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550b_lite_tz>; + + trips { + trip0 { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <135000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550b-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8550b_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <10000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8550b-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm8550b_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <11500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8550b-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8550b_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8550b-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8550b_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pm8550b-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8550b_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip: socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8550ve.dtsi b/qcom/pm8550ve.dtsi new file mode 100644 index 00000000..e82971be --- /dev/null +++ b/qcom/pm8550ve.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8550ve@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_tz: pm8550ve-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_gpios: pinctrl@8800 { + compatible = "qcom,pm8550ve-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm8550ve_temp_alarm: pm8550ve_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550ve_tz>; + + trips { + pm8550ve_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550ve_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550ve_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pm8550vs.dtsi b/qcom/pm8550vs.dtsi new file mode 100644 index 00000000..d03b8492 --- /dev/null +++ b/qcom/pm8550vs.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8550vs_c: qcom,pm8550vs@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_c_tz: pm8550vs-c-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_c_gpios: pinctrl@8800 { + compatible = "qcom,pm8550vs-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_d: qcom,pm8550vs@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_d_tz: pm8550vs-d-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_d_gpios: pinctrl@8800 { + compatible = "qcom,pm8550vs-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_e: qcom,pm8550vs@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_e_tz: pm8550vs-e-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_e_gpios: pinctrl@8800 { + compatible = "qcom,pm8550vs-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_g: qcom,pm8550vs@6 { + compatible = "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_g_tz: pm8550vs-g-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_g_gpios: pinctrl@8800 { + compatible = "qcom,pm8550vs-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm8550vs_c_temp_alarm: pm8550vs_c_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550vs_c_tz>; + + trips { + pm8550vs_c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_c_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_c_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550vs_d_temp_alarm: pm8550vs_d_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550vs_d_tz>; + + trips { + pm8550vs_d_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_d_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_d_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550vs_e_temp_alarm: pm8550vs_e_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550vs_e_tz>; + + trips { + pm8550vs_e_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_e_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_e_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8550vs_g_temp_alarm: pm8550vs_g_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8550vs_g_tz>; + + trips { + pm8550vs_g_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_g_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8550vs_g_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi new file mode 100644 index 00000000..dc53573f --- /dev/null +++ b/qcom/pmk8550.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#define PM8550VE_SID 8 +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmk8550@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_sdam_1: sdam@7000 { + compatible = "qcom,spmi-sdam"; + reg = <0x7000>; + #address-cells = <1>; + #size-cells = <1>; + + ocp_log: ocp-log@76 { + reg = <0x76 0x6>; + }; + }; + + pmk8550_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + + restart_reason: restart@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + + alarm_log: alarm-log@76 { + reg = <0x76 0x6>; + }; + }; + + pmk8550_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + }; + + pmk8550_sdam_6: sdam@7500 { + compatible = "qcom,spmi-sdam"; + reg = <0x7500>; + }; + + pmk8550_sdam_21: sdam@8400 { + compatible = "qcom,spmi-sdam"; + reg = <0x8400>; + }; + + pmk8550_sdam_22: sdam@8500 { + compatible = "qcom,spmi-sdam"; + reg = <0x8500>; + }; + + pon_hlos@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + + pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + }; + + pmk8550_gpios: pinctrl@b800 { + compatible = "qcom,pmk8550-gpio"; + reg = <0xb800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8550_vadc: vadc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "adc-sdam0", "adc-sdam1"; + interrupts = <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* PMK8550 Channel nodes */ + pmk8550_offset_ref { + reg = ; + label = "pmk8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + pmk8550_vref_1p25 { + reg = ; + label = "pmk8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pmk8550_die_temp { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550 Channel nodes */ + pm8550_offset_ref { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + pm8550_vref_1p25 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8550_die_temp { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8550_vph_pwr { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550B Channel nodes */ + pm8550b_offset_ref { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + pm8550b_vref_1p25 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + pm8550b_die_temp { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8550b_lite_die_temp { + reg = ; + label = "pm8550b_lite_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pm8550b_vph_pwr { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + pm8550b_vbat_sns_qbg { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + pm8550vs_c_die_temp { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + pm8550vs_d_die_temp { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + pm8550vs_e_die_temp { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + pm8550vs_g_die_temp { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + pm8550ve_die_temp { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + }; +}; diff --git a/qcom/pmr735d.dtsi b/qcom/pmr735d.dtsi new file mode 100644 index 00000000..ab41ee13 --- /dev/null +++ b/qcom/pmr735d.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmr735d@a { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_tz: pmr735d-temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_gpios: pinctrl@8800 { + compatible = "qcom,pmr735d-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmr735d_temp_alarm: pmr735d_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmr735d_tz>; + + trips { + pmr735d_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735d_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735d_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +};