From 8d297483dcadc21a5b609dc9ffaca4f06e9a12e0 Mon Sep 17 00:00:00 2001
From: Chintan Kothari <quic_ckothari@quicinc.com>
Date: Thu, 6 Mar 2025 14:14:17 +0530
Subject: [PATCH] ARM: dts: msm: Add interconnect devices for SM6150

Add interconnect devices for camnoc_virt, ipa_virt, mc_virt,
dc_noc, gem_noc, config_noc, system_noc, aggre1_noc and
mmss_noc. This will allow consumers to get their
path and set bandwidth constraints on them.

Change-Id: I8c2eb0b8a63252cbfcfe44355ad9b4421c8aee5c
Signed-off-by: Chintan Kothari <quic_ckothari@quicinc.com>
---
 qcom/sm6150.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 4dd1255f..a86e95db 100644
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -9,6 +9,8 @@
 #include <dt-bindings/clock/qcom,gcc-sm6150.h>
 #include <dt-bindings/clock/qcom,gpucc-sm6150.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm6150.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/clock/qcom,videocc-sm6150.h>
@@ -442,6 +444,10 @@
 						  <FAST_PATH_TCS 0>;
 			};
 
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
+
 			rpmhcc: qcom,rpmhclk {
 				compatible = "qcom,sm6150-rpmh-clk";
 				#clock-cells = <1>;
@@ -468,6 +474,11 @@
 						  <CONTROL_TCS   0>,
 						  <FAST_PATH_TCS 0>;
 			};
+
+			disp_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+				qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
+			};
 		};
 	};
 
@@ -576,6 +587,78 @@
 		};
 	};
 
+	camnoc_virt: interconnect@0 {
+		compatible = "qcom,sm6150-camnoc_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	ipa_virt: interconnect@1 {
+		compatible = "qcom,sm6150-ipa_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect@2 {
+		compatible = "qcom,sm6150-mc_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	dc_noc: interconnect@9160000 {
+		reg = <0x9160000 0x3200>;
+		compatible = "qcom,sm6150-dc_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	gem_noc: interconnect@9680000 {
+		reg = <0x9680000 0x3e200>;
+		compatible = "qcom,sm6150-gem_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	config_noc: interconnect@1500000 {
+		reg = <0x1500000 0x5080>;
+		compatible = "qcom,sm6150-config_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	system_noc: interconnect@1620000 {
+		reg = <0x1620000 0x1f300>;
+		compatible = "qcom,sm6150-system_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	aggre1_noc: interconnect@1700000 {
+		reg = <0x1700000 0x3f200>;
+		compatible = "qcom,sm6150-aggre1_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+	};
+
+	mmss_noc: interconnect@1740000 {
+		reg = <0x1740000 0x1c100>;
+		compatible = "qcom,sm6150-mmss_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
 	gcc: clock-controller@100000 {
 		compatible = "qcom,sm6150-gcc", "syscon";
 		reg = <0x100000 0x1f0000>;