From ed574458cf0c0b5f2a30f0dc828989668fb3885b Mon Sep 17 00:00:00 2001
From: Vivek Aknurwar <quic_viveka@quicinc.com>
Date: Wed, 18 Oct 2023 17:32:08 -0700
Subject: [PATCH 1/2] dt-bindings: clock: Add binding for sun debugcc clock
 controller

Add DEBUGCC bindings for sun device.

Change-Id: Id36bce94d6e02e7efafc59390be1c7baaf800f27
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
---
 bindings/clock/qcom,debugcc.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml
index d22c7d7d..8a8426dc 100644
--- a/bindings/clock/qcom,debugcc.yaml
+++ b/bindings/clock/qcom,debugcc.yaml
@@ -4,10 +4,11 @@
 $id: http://devicetree.org/schemas/clock/qcom,debugcc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Technologies, Inc. Debug Clock Controller Binding
+title: Qualcomm Technologies, Inc. Debug Clock Controller
 
 maintainers:
   - Xubin Bai <quic_xubibai@quicinc.com>
+  - Vivek Aknurwar <quic_viveka@quicinc.com>
 
 description: |
   Debug Clock Controller module which support debug clock controllers.
@@ -16,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,pineapple-debugcc
+      - qcom,sun-debugcc
 
   clocks:
     items:

From af41f8a07878baf36a66eb75bcde98806a4dcac6 Mon Sep 17 00:00:00 2001
From: Vivek Aknurwar <quic_viveka@quicinc.com>
Date: Wed, 18 Oct 2023 15:16:13 -0700
Subject: [PATCH 2/2] ARM: dts: msm: Add debugcc device for Sun

Add device tree node for measure nodes and enable
debug cc driver on Sun.

Change-Id: I5475161d0f1d7ce488b6372d19ba1212dea238f5
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
---
 qcom/sun.dtsi | 44 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 39 insertions(+), 5 deletions(-)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 3ed69a52..aa50ec7e 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -1207,16 +1207,50 @@
 		#reset-cells = <1>;
 	};
 
-	apsscc: syscon@16450000 {
-		compatible = "syscon";
-		reg = <0x16450000 0x3553000>;
-	};
-
 	mccc: syscon@240ba000 {
 		compatible = "syscon";
 		reg = <0x240ba000 0x800>;
 	};
 
+	gxclkctldebugcc: syscon@3d64000 {
+		compatible = "syscon";
+		reg = <0x3d64000 0x6000>;
+	};
+
+	debugcc: qcom,cc-debug {
+		compatible = "qcom,sun-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,gxclkctl = <&gxclkctldebugcc>;
+		qcom,videocc = <&videocc>;
+		qcom,evacc = <&evacc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,camcc = <&camcc>;
+		qcom,cambistmclkcc = <&cambistmclkcc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&cambistmclkcc 0>,
+			 <&camcc 0>,
+			 <&dispcc 0>,
+			 <&evacc 0>,
+			 <&gcc 0>,
+			 <&gpucc 0>,
+			 <&gxclkctl 0>,
+			 <&tcsrcc 0>,
+			 <&videocc 0>;
+		clock-names = "xo_clk_src",
+			      "cambistmclkcc",
+			      "camcc",
+			      "dispcc",
+			      "evacc",
+			      "gcc",
+			      "gpucc",
+			      "gxclkctl",
+			      "tcsrcc",
+			      "videocc";
+		#clock-cells = <1>;
+	};
+
 	/* CAM_CC GDSCs */
 	cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
 		compatible = "qcom,gdsc";