ARM: dts: msm: PCIe CESTA related dt properties
PCIe CESTA related dtsi node properties and cesta based is not yet enabled. Change-Id: I5846df725b690d95ef54ec5f7b85cbe1fe206325 Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
@@ -16,8 +16,10 @@
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<0x40000000 0xf1d>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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<0x40100000 0x100000>,
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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<0x01D07000 0x7000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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"pcie_sm";
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cell-index = <0>;
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cell-index = <0>;
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linux,pci-domain = <0>;
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linux,pci-domain = <0>;
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@@ -49,20 +51,8 @@
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&pcie0_clkreq_sleep
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
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vreg-1p2-supply = <&pm_v8g_l3>;
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vreg-0p9-supply = <&pm_v6f_l1>;
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vreg-qref-supply = <&pm_v8i_l3>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
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qcom,vreg-0p9-voltage-level = <912000 880000 80900>;
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qcom,vreg-qref-voltage-level = <880000 880000 25700>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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@@ -77,35 +67,8 @@
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100000000>;
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100000000>;
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interconnect-names = "icc_path";
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interconnect-names = "icc_path";
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interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>;
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interconnects = <&pcie_noc MASTER_PCIE_3_PCIE_CRM_HW_0
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&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
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<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_rate_change_clk",
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"gcc_ddrss_pcie_sf_qtb_clk",
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"pcie_aggre_noc_axi_clk",
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"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
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<100000000>, <0>, <0>, <0>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>, <1>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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<&gcc GCC_PCIE_0_PHY_BCR>;
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@@ -251,6 +214,20 @@
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0x0400 0x00 0x0
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0x0400 0x00 0x0
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0x0444 0x03 0x0>;
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0x0444 0x03 0x0>;
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qcom,pcie-clkreq-offset = <0x2C48>;
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qcom,pcie-clkreq-pin = <103>;
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qcom,pcie-sm-branch-offset = <0x1000>;
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qcom,pcie-sm-start-offset = <0x1090>;
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qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
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<0x28007003>, <0x80804002>, <0x70021c01>,
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<0x18001802>, <0x70005000>, <0x10004000>,
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<0x80814002>, <0x18001c01>, <0x1c018080>,
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<0x0000100>;
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qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
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<0x0>, <0x0>;
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pcie0_rp: pcie0_rp {
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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reg = <0 0 0 0 0>;
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};
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};
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@@ -99,9 +99,10 @@
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<0x40000f20 0xa8>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>,
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<0x40100000 0x100000>,
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<0x01D07000 0x7000>,
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<0x01c05000 0x1000>;
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<0x01c05000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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"rumi";
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"pcie_sm", "rumi";
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linux,pci-domain = <0>;
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linux,pci-domain = <0>;
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qcom,target-link-speed = <0x1>;
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qcom,target-link-speed = <0x1>;
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qcom,link-check-max-count = <200>; /* 1 sec */
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qcom,link-check-max-count = <200>; /* 1 sec */
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