ARM: dts: msm: PCIe CESTA related dt properties

PCIe CESTA related dtsi node properties and cesta
based is not yet enabled.

Change-Id: I5846df725b690d95ef54ec5f7b85cbe1fe206325
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
This commit is contained in:
Prudhvi Yarlagadda
2023-09-01 18:00:28 -07:00
parent d8ab22901a
commit a7d6099a6d
2 changed files with 23 additions and 45 deletions

View File

@@ -16,8 +16,10 @@
<0x40000000 0xf1d>, <0x40000000 0xf1d>,
<0x40000f20 0xa8>, <0x40000f20 0xa8>,
<0x40001000 0x1000>, <0x40001000 0x1000>,
<0x40100000 0x100000>; <0x40100000 0x100000>,
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf"; <0x01D07000 0x7000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"pcie_sm";
cell-index = <0>; cell-index = <0>;
linux,pci-domain = <0>; linux,pci-domain = <0>;
@@ -49,20 +51,8 @@
&pcie0_clkreq_sleep &pcie0_clkreq_sleep
&pcie0_wake_default>; &pcie0_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>; gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
vreg-1p2-supply = <&pm_v8g_l3>;
vreg-0p9-supply = <&pm_v6f_l1>;
vreg-qref-supply = <&pm_v8i_l3>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
qcom,vreg-0p9-voltage-level = <912000 880000 80900>;
qcom,vreg-qref-voltage-level = <880000 880000 25700>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */ qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS <RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS RPMH_REGULATOR_LEVEL_LOW_SVS
@@ -77,35 +67,8 @@
100000000>; 100000000>;
interconnect-names = "icc_path"; interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_3 &mc_virt SLAVE_EBI1>; interconnects = <&pcie_noc MASTER_PCIE_3_PCIE_CRM_HW_0
&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_rate_change_clk",
"gcc_ddrss_pcie_sf_qtb_clk",
"pcie_aggre_noc_axi_clk",
"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
<100000000>, <0>, <0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>, <1>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>, resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>; <&gcc GCC_PCIE_0_PHY_BCR>;
@@ -251,6 +214,20 @@
0x0400 0x00 0x0 0x0400 0x00 0x0
0x0444 0x03 0x0>; 0x0444 0x03 0x0>;
qcom,pcie-clkreq-offset = <0x2C48>;
qcom,pcie-clkreq-pin = <103>;
qcom,pcie-sm-branch-offset = <0x1000>;
qcom,pcie-sm-start-offset = <0x1090>;
qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
<0x28007003>, <0x80804002>, <0x70021c01>,
<0x18001802>, <0x70005000>, <0x10004000>,
<0x80814002>, <0x18001c01>, <0x1c018080>,
<0x0000100>;
qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
<0x0>, <0x0>;
pcie0_rp: pcie0_rp { pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>; reg = <0 0 0 0 0>;
}; };

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@@ -99,9 +99,10 @@
<0x40000f20 0xa8>, <0x40000f20 0xa8>,
<0x40001000 0x1000>, <0x40001000 0x1000>,
<0x40100000 0x100000>, <0x40100000 0x100000>,
<0x01D07000 0x7000>,
<0x01c05000 0x1000>; <0x01c05000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"rumi"; "pcie_sm", "rumi";
linux,pci-domain = <0>; linux,pci-domain = <0>;
qcom,target-link-speed = <0x1>; qcom,target-link-speed = <0x1>;
qcom,link-check-max-count = <200>; /* 1 sec */ qcom,link-check-max-count = <200>; /* 1 sec */