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ARM: dts: msm: PCIe CESTA related dt properties for tuna

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PCIe CESTA related dt properties for tuna.

Change-Id: I4bb53ed6378bb6f02600ec8d6109788a2bc84312
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
This commit is contained in:
Paras Sharma
2024-10-17 17:34:13 +05:30
committed by Vishvanath Singh
parent e3fe7b6fe7
commit a532935af1
2 changed files with 37 additions and 51 deletions
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86
qcom/tuna-pcie.dtsi
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@@ -17,8 +17,9 @@
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>,
<0x1c03000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
<0x1c03000 0x1000>,
<0x01D07000 0x7000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi", "pcie_sm";
cell-index = <0>;
linux,pci-domain = <0>;
@@ -50,22 +51,8 @@
&pcie0_clkreq_sleep
&pcie0_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
vreg-1p2-supply = <&L4B>;
vreg-0p9-supply = <&L2B>;
vreg-qref-supply = <&L2B>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>;
qcom,vreg-0p9-voltage-level = <912000 880000 92070>;
qcom,vreg-qref-voltage-level = <880000 880000 46800>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
@@ -80,38 +67,8 @@
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_rate_change_clk",
"gcc_ddrss_pcie_sf_qtb_clk",
"pcie_aggre_noc_axi_clk",
"gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
"pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>;
interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0
&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
@@ -129,8 +86,6 @@
qcom,l1-2-th-value = <150>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,drv-name = "lpass";
qcom,drv-l1ss-timeout-us = <5000>;
qcom,pcie-phy-ver = <112>;
qcom,phy-status-offset = <0x214>;
@@ -253,6 +208,37 @@
0x0200 0x00 0x0
0x0244 0x03 0x0>;
qcom,drv-name = "cesta";
qcom,drv-l1ss-timeout-us = <5000>;
qcom,pcie-clkreq-offset = <0x2c48>;
qcom,pcie-clkreq-pin = <118>;
qcom,pcie-sm-branch-offset = <0x1000>;
qcom,pcie-sm-start-offset = <0x1090>;
qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
<0x28007003>, <0x80804002>, <0x70021c01>,
<0x18002802>, <0x70005000>, <0x10004000>,
<0x80814002>, <0x18001c01>, <0x1c018080>,
<0x0000100>;
qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
<0x0>, <0x0>;
qcom,pcie-sm-debug = <0x1040>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
<0x1048>, /* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
<0x1050>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
<0x1058>, /* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
<0x1060>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
<0x1068>, /* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
<0x1070>, /* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
<0x1078>, /* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
<0x1080>, /* PCIE_SMs_SEQ_BR_EVENT_STATUS */
<0x1088>, /* PCIE_SMs_SEQ_PC_VAL */
<0x1090>, /* PCIE_SMs_SEQ_START */
<0x1094>, /* PCIE_SMs_CLKREQ_GATE */
<0x1098>, /* PCIE_SMs_CLKREQ_UNGATE */
<0x109C>; /* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */
status = "disabled";
pcie0_rp: pcie0_rp {