From bf34f7e5c8c4480be6e2a69decd44a8ead2f5e20 Mon Sep 17 00:00:00 2001
From: Prasanna S <quic_prass@quicinc.com>
Date: Wed, 8 May 2024 12:49:06 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 UART console node for kera

Enable console support on kera.

Change-Id: I5ad3d0c05512b6f49cd67a773e5b2e16f6d1a10d
Signed-off-by: Prasanna S <quic_prass@quicinc.com>
---
 qcom/kera-pinctrl.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
 qcom/kera-qupv3.dtsi   | 33 +++++++++++++++++++++++++++++++++
 qcom/kera.dtsi         |  9 ++++++++-
 3 files changed, 81 insertions(+), 1 deletion(-)
 create mode 100644 qcom/kera-qupv3.dtsi

diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi
index f0567b81..1aa1ce71 100644
--- a/qcom/kera-pinctrl.dtsi
+++ b/qcom/kera-pinctrl.dtsi
@@ -4,4 +4,44 @@
  */
 
 &tlmm {
+	qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
+		qupv3_se13_2uart_tx_active: qupv3_se13_2uart_tx_active {
+			mux {
+				pins = "gpio18";
+				function = "qup2_se5_l2";
+			};
+
+			config {
+				pins = "gpio18";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_2uart_rx_active: qupv3_se13_2uart_rx_active {
+			mux {
+				pins = "gpio19";
+				function = "qup2_se5_l3";
+			};
+
+			config {
+				pins = "gpio19";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
+			mux {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
 };
diff --git a/qcom/kera-qupv3.dtsi b/qcom/kera-qupv3.dtsi
new file mode 100644
index 00000000..5f79ee9c
--- /dev/null
+++ b/qcom/kera-qupv3.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	/* QUPv3_2 Wrapper Instance */
+	qupv3_2: qcom,qupv3_1_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se13_2uart: qcom,qup_uart@894000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x894000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_2uart_tx_active>, <&qupv3_se13_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se13_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index d75b7787..93498e60 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -39,7 +39,9 @@
 		qcom_scm: qcom_scm { };
 	};
 
-	aliases {};
+	aliases {
+		serial0 = &qupv3_se13_2uart;
+	};
 
 	cpus {
 		#address-cells = <2>;
@@ -725,3 +727,8 @@
 
 #include "kera-pinctrl.dtsi"
 #include "kera-usb.dtsi"
+#include "kera-qupv3.dtsi"
+
+&qupv3_se13_2uart {
+	status = "ok";
+};