Merge "ARM: dts: msm: Update gpucc and gx_clkctl clock node as GenPD provider"

bindings/clock/qcom,gx_clkctl.yaml

@@ -15,12 +15,13 @@ description: |
 
   See also:
     dt-bindings/clock/qcom,gxclkctl-sun.h
+    dt-bindings/clock/qcom,gpucc-tuna.h
 
 properties:
   compatible:
     enum:
       - qcom,sun-gx_clkctl
-
+      - qcom,tuna-gx_clkctl
   reg:
     maxItems: 1
 

qcom/tuna-rumi.dtsi

@@ -212,3 +212,11 @@
 &video_cc_mvs0c_gdsc {
 	status = "ok";
 };
+
+&gpu_cc_cx_gdsc {
+	status = "ok";
+};
+
+&gx_clkctl_gx_gdsc {
+	status = "ok";
+};

qcom/tuna.dtsi

@@ -1712,13 +1712,16 @@
 			      "gpll0_out_main_div";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		#power-domain-cells = <1>;
 	};
 
 	gxclkctl: clock-controller@3d68024 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "gxclkctl_clocks";
-		#clock-cells = <1>;
-		#reset-cells = <1>;
+		compatible = "qcom,tuna-gx_clkctl";
+		reg = <0x3d68024 0x8>;
+		reg-name = "cc_base";
+		power-domains = <&gpucc GPU_CC_CX_GDSC>;
+		vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
+		#power-domain-cells = <1>;
 	};
 
 	tcsrcc: clock-controller@1fbf000 {
@@ -3112,12 +3115,10 @@
 &gpu_cc_cx_gdsc {
 	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
-	status = "ok";
 };
 
 &gx_clkctl_gx_gdsc {
 	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
-	status = "ok";
 };
 
 &video_cc_mvs0_gdsc {