Merge "bindings: pinctrl: Add devicetree bindings for Kera TLMM"
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bindings/pinctrl/qcom,kera-tlmm.yaml
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196
bindings/pinctrl/qcom,kera-tlmm.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,kera-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Kera TLMM block
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maintainers:
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- Mukesh Ojha <quic_mojha@quicinc.com>
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description: |
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This binding describes the Top Level Mode Multiplexer (TLMM) block found
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in the Kera platform.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,kera-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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'#interrupt-cells': true
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gpio-controller: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 105
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gpio-line-names:
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maxItems: 214
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'#gpio-cells': true
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gpio-ranges: true
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wakeup-parent: true
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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'-state$':
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oneOf:
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- $ref: "#/$defs/qcom-kera-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-kera-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-kera-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
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atest_char_start, atest_usb0, atest_usb00, atest_usb01,
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atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
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audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
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cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
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cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
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cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
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cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
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cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
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cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
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coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
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ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
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gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
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i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
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i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
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i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
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i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
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i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
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i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
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i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
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mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
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mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
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nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
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phase_flag10, phase_flag11, phase_flag12, phase_flag13,
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phase_flag14, phase_flag15, phase_flag16, phase_flag17,
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phase_flag18, phase_flag19, phase_flag2, phase_flag20,
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phase_flag21, phase_flag22, phase_flag23, phase_flag24,
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phase_flag25, phase_flag26, phase_flag27, phase_flag28,
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phase_flag29, phase_flag3, phase_flag30, phase_flag31,
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phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
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phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
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qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
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qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
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qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
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qlink_big_enable, qlink_big_request, qlink_little_enable,
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qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
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qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
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qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
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qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
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qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
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qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
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qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
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qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
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qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
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qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
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qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
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qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
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qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
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qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
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qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
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qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
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sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
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tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
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tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
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uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
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uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
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vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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allOf:
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- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
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- if:
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properties:
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pins:
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pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
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then:
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required:
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- function
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@f100000 {
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compatible = "qcom,kera-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 211>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio26";
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function = "qup1_se7_l0";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio27";
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function = "qup1_se7_l1";
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bias-disable;
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};
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};
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};
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...
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