From acfc51f2dd8198d8508f172ac212eae1beaee5e2 Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Mon, 12 Aug 2024 15:11:20 +0530 Subject: [PATCH] ARM: dts: qcom: Remove sdpm clock driver support Remove SDPM clock driver support from clarence gaming. Remove cpu pause action on boot core. Add cold temperature interrupt handling support in clarence. Change-Id: I05da43e8a8e392f2bec8f425ac9750f559221953 Signed-off-by: Nitesh Kumar --- qcom/ravelin-sg.dtsi | 4 ++++ qcom/ravelin-thermal.dtsi | 35 +++++++++++++++++++++-------------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/qcom/ravelin-sg.dtsi b/qcom/ravelin-sg.dtsi index 0981fc84..2781eada 100644 --- a/qcom/ravelin-sg.dtsi +++ b/qcom/ravelin-sg.dtsi @@ -5,6 +5,10 @@ #include "ravelin.dtsi" +&cx_sdpm { + status = "disabled"; +}; + / { model = "Qualcomm Technologies, Inc. Ravelin SG"; diff --git a/qcom/ravelin-thermal.dtsi b/qcom/ravelin-thermal.dtsi index 83c3984f..83077030 100644 --- a/qcom/ravelin-thermal.dtsi +++ b/qcom/ravelin-thermal.dtsi @@ -9,6 +9,12 @@ #cooling-cells = <2>; }; +&aoss_qmp { + cx_cdev: cx_cdev { + #cooling-cells = <2>; + }; +}; + &soc { tsens0: thermal-sensor@c263000 { compatible = "qcom,tsens-v2"; @@ -222,7 +228,7 @@ }; }; - cx_sdpm@634000 { + cx_sdpm: cx_sdpm@634000 { compatible = "qcom,sdpm"; reg = <0x00634000 0x1000>; clock-names = "gpu_cc_gx_gfx3d", @@ -285,25 +291,12 @@ type = "passive"; }; - cpu0_emerg: cpu0-emerg-cfg { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - reset-mon-cfg { temperature = <115000>; hysteresis = <0>; type = "hot"; }; }; - - cooling-maps { - cpu00_cdev { - trip = <&cpu0_emerg>; - cooling-device = <&cpu0_pause 1 1>; - }; - }; }; cpu-0-1 { @@ -906,6 +899,13 @@ type = "passive"; }; }; + + cooling-maps { + wcss_cx_vdd_cdev { + trip = <&min_temp_0_trip>; + cooling-device = <&cx_cdev 1 1>; + }; + }; }; zeroc-1 { @@ -925,6 +925,13 @@ type = "passive"; }; }; + + cooling-maps { + wcss_cx_vdd_cdev { + trip = <&min_temp_1_trip>; + cooling-device = <&cx_cdev 1 1>; + }; + }; }; cx-pe {