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ARM: dts: msm: Add powerlevels for AB and AC sku for sun gpu

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Add supporting power levels for AB and AC sku devices.

Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
This commit is contained in:
Mohammed Mirza Mandayappurath Manzoor
2024-01-19 16:03:19 -08:00
committed by Kamal Agrawal
parent 8687f5ac09
commit a17c326b0e
2 changed files with 148 additions and 2 deletions
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132
gpu/sun-gpu-pwrlevels.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
&msm_gpu { &msm_gpu {
@@ -15,6 +15,136 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
qcom,initial-pwrlevel = <10>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
/* NOM_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
};
/* NOM */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <11>; qcom,initial-pwrlevel = <11>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>; qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;

18
gpu/sun-gpu.dtsi
View File

@@ -1,15 +1,31 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024)) #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
/* External feature codes */ /* External feature codes */
#define FC_UNKNOWN 0x0 #define FC_UNKNOWN 0x0
#define FC_AA 0x1
#define FC_AB 0x2
#define FC_AC 0x3
#define FC_AD 0x4
/* Internal feature codes */
#define FC_Y0 0x00f1
#define FC_Y1 0x00f2
/* Pcodes */ /* Pcodes */
#define PCODE_UNKNOWN 0 #define PCODE_UNKNOWN 0
#define PCODE_0 1
#define PCODE_1 2
#define PCODE_2 3
#define PCODE_3 4
#define PCODE_4 5
#define PCODE_5 6
#define PCODE_6 7
#define PCODE_7 8
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode) #define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)