diff --git a/bindings/arm/msm/msm.yaml b/bindings/arm/msm/msm.yaml index 30c87d0b..996c4289 100644 --- a/bindings/arm/msm/msm.yaml +++ b/bindings/arm/msm/msm.yaml @@ -156,8 +156,33 @@ properties: - enum: - qcom,kera-rumi - qcom,rumi + - qcom,kera-atp + - qcom,atp + - qcom,kera-cdp + - qcom,cdp + - qcom,kera-mtp + - qcom,mtp + - qcom,kera-qrd + - qcom,qrd + - qcom,kera-rcm + - qcom,rcm - const: qcom,kera + - description: Qualcomm Technologies, Inc. KERAP + items: + - enum: + - qcom,kerap-atp + - qcom,atp + - qcom,kerap-cdp + - qcom,cdp + - qcom,kerap-mtp + - qcom,mtp + - qcom,kerap-qrd + - qcom,qrd + - qcom,kerap-rcm + - qcom,rcm + - const: qcom,kerap + - description: Qualcomm Technologies, Inc. MONACO items: - enum: diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml index eb7c6bdd..cb841be8 100644 --- a/bindings/arm/msm/qcom,llcc.yaml +++ b/bindings/arm/msm/qcom,llcc.yaml @@ -37,6 +37,7 @@ properties: - qcom,sun-llcc - qcom,sdxpinn-llcc - qcom,tuna-llcc + - qcom,tuna7-llcc - qcom,kera-llcc - qcom,x1e80100-llcc diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 81a14145..0d15434e 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -31,6 +31,7 @@ properties: - qcom,pineapple-dispcc - qcom,sun-dispcc - qcom,tuna-dispcc + - qcom,tuna-dispcc-v1 clocks: items: diff --git a/bindings/clock/qcom,gcc-sun.yaml b/bindings/clock/qcom,gcc-sun.yaml index fa5755e4..f24558f6 100644 --- a/bindings/clock/qcom,gcc-sun.yaml +++ b/bindings/clock/qcom,gcc-sun.yaml @@ -23,6 +23,7 @@ properties: - qcom,gcc-sun - qcom,tuna-gcc - qcom,kera-gcc + - qcom,tuna-gcc-v1 clocks: items: diff --git a/bindings/thermal/qcom-bcl-pmic5.yaml b/bindings/thermal/qcom-bcl-pmic5.yaml index 5bfb1a83..dbf134a8 100644 --- a/bindings/thermal/qcom-bcl-pmic5.yaml +++ b/bindings/thermal/qcom-bcl-pmic5.yaml @@ -23,10 +23,11 @@ description: | properties: compatible: - description: msm battery state of charge device + description: msm battery current limiting device items: - const: qcom,bcl-v5 - const: qcom,pm8550-bcl-v5 + - const: qcom,pmiv010x-bcl-v5 reg: maxItems: 1 diff --git a/bindings/ufs/qcom,ufs.yaml b/bindings/ufs/qcom,ufs.yaml index cd88de10..83a3a2dc 100644 --- a/bindings/ufs/qcom,ufs.yaml +++ b/bindings/ufs/qcom,ufs.yaml @@ -37,6 +37,7 @@ properties: - qcom,ufs-phy-qmp-v4-pineapple - qcom,ufs-phy-qmp-v4-waipio - qcom,ufs-phy-qmp-v4-sun + - qcom,ufs-phy-qmp-v4-niobe - const: qcom,ufshc - const: jedec,ufs-2.0 diff --git a/bindings/usb/qcom,dwc-usb3-msm.yaml b/bindings/usb/qcom,dwc-usb3-msm.yaml index 96d9b20a..7947bdd9 100644 --- a/bindings/usb/qcom,dwc-usb3-msm.yaml +++ b/bindings/usb/qcom,dwc-usb3-msm.yaml @@ -61,6 +61,11 @@ properties: USB3_GDSC-supply: description: USB GDSC supply. + vbus_dwc3-supply: + description: Regulator supply for the VBUS 5V power for USB host mode. + This is typically used when VBUS is controlled by a GPIO-based + regulator to enable/disable USB port power. + clock-names: minItems: 1 items: @@ -168,6 +173,7 @@ examples: ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + vbus_dwc3-supply = <&usb0_vbus_reg>; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, diff --git a/qcom/Makefile b/qcom/Makefile index 6f922104..51ca4378 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -53,7 +53,8 @@ sun-dtb-$(CONFIG_ARCH_SUN) += \ sun-overlays-dtb-$(CONFIG_ARCH_SUN) += $(SUN_BOARDS) $(NOAPQ_SUN_BOARDS) $(SUN_BASE_DTB) $(SUN_APQ_BASE_DTB) TUNA_BASE_DTB += tuna.dtb tuna7.dtb -NOAPQ_TUNA_BOARDS += \ +TUNA_APQ_BASE_DTB += tunap.dtb +TUNA_BOARDS += \ tuna-atp-overlay.dtbo \ tuna-cdp-overlay.dtbo \ tuna-mtp-kiwi-harmonium-overlay.dtbo \ @@ -64,21 +65,48 @@ NOAPQ_TUNA_BOARDS += \ tuna-mtp-kiwi-pmd802x-overlay.dtbo \ tuna-qrd-overlay.dtbo \ tuna-rcm-kiwi-overlay.dtbo \ - tuna-rcm-overlay.dtbo \ + tuna-rcm-overlay.dtbo + +NOAPQ_TUNA_BOARDS += \ tuna-rumi-overlay.dtbo sun-dtb-$(CONFIG_ARCH_TUNA) += \ - $(call add-overlays, $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB)) -sun-overlays-dtb-$(CONFIG_ARCH_TUNA) += $(NOAPQ_TUNA_BOARDS) $(TUNA_BASE_DTB) + $(call add-overlays, $(TUNA_BOARDS) $(NOAPQ_TUNA_BOARDS),$(TUNA_BASE_DTB)) \ + $(call add-overlays, $(TUNA_BOARDS) $(APQ_TUNA_BOARDS),$(TUNA_APQ_BASE_DTB)) +sun-overlays-dtb-$(CONFIG_ARCH_TUNA) += $(TUNA_BOARDS) $(NOAPQ_TUNA_BOARDS) $(TUNA_BASE_DTB) $(TUNA_APQ_BASE_DTB) dtb-y += $(sun-dtb-y) KERA_BASE_DTB += kera.dtb +KERA_APQ_BASE_DTB += kerap.dtb +KERA_BOARDS += \ + kera-atp-overlay.dtbo \ + kera-mtp-qca6750-ufs4-overlay.dtbo \ + kera-mtp-qca6750-ufs3-overlay.dtbo \ + kera-mtp-qca6750-qmp1000-overlay.dtbo \ + kera-mtp-wcn7750-qmp1000-overlay.dtbo \ + kera-mtp-wcn7750-ufs4-overlay.dtbo \ + kera-mtp-wcn7750-ufs3-overlay.dtbo \ + kera-cdp-qca6750-ufs2-overlay.dtbo \ + kera-cdp-qca6750-ufs3-overlay.dtbo \ + kera-cdp-qca6750-ufs4-overlay.dtbo \ + kera-qrd-wcn7750-ufs4-overlay.dtbo \ + kera-qrd-wcn7750-ufs2-overlay.dtbo \ + kera-qrd-wcn7750-ufs3-overlay.dtbo \ + kera-rcm-qca6750-ufs4-overlay.dtbo \ + kera-rcm-qca6750-ufs2-overlay.dtbo \ + kera-rcm-qca6750-ufs3-overlay.dtbo \ + kera-rcm-wcn7750-ufs2-overlay.dtbo \ + kera-rcm-wcn7750-ufs3-overlay.dtbo \ + kera-rcm-wcn7750-ufs4-overlay.dtbo + NOAPQ_KERA_BOARDS += \ - kera-rumi-overlay.dtbo + kera-rumi-overlay.dtbo sun-dtb-$(CONFIG_ARCH_KERA) += \ - $(call add-overlays, $(NOAPQ_KERA_BOARDS),$(KERA_BASE_DTB)) -sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(NOAPQ_KERA_BOARDS) $(KERA_BASE_DTB) + $(call add-overlays, $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS),$(KERA_BASE_DTB)) \ + $(call add-overlays, $(KERA_BOARDS) $(APQ_KERA_BOARDS),$(KERA_APQ_BASE_DTB)) +sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS) $(KERA_BASE_DTB) $(KERA_APQ_BASE_DTB) + dtb-y += $(sun-dtb-y) PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb @@ -240,7 +268,17 @@ endif ifeq ($(CONFIG_ARCH_KERA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb \ - kera-oemvm-rumi.dtb + kera-vm-atp.dtb \ + kera-vm-cdp.dtb \ + kera-vm-mtp.dtb \ + kera-vm-qrd.dtb \ + kera-vm-rcm.dtb \ + kera-oemvm-rumi.dtb \ + kera-oemvm-atp.dtb \ + kera-oemvm-cdp.dtb \ + kera-oemvm-mtp.dtb \ + kera-oemvm-qrd.dtb \ + kera-oemvm-rcm.dtb dtb-y += $(kera_tuivm-dtb-y) endif endif diff --git a/qcom/kera-atp-overlay.dts b/qcom/kera-atp-overlay.dts new file mode 100644 index 00000000..657f5d6d --- /dev/null +++ b/qcom/kera-atp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-pm7550ba.dtsi" +#include "kera-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/kera-atp.dtsi b/qcom/kera-atp.dtsi new file mode 100644 index 00000000..ed1d67d3 --- /dev/null +++ b/qcom/kera-atp.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + +&pmic_glink_debug { + status = "disabled"; +}; + +&pmic_glink_adc { + status = "disabled"; +}; diff --git a/qcom/kera-cdp-qca6750-ufs2-overlay.dts b/qcom/kera-cdp-qca6750-ufs2-overlay.dts new file mode 100644 index 00000000..4d940c38 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs2-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-cdp-qca6750-ufs2.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS2"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30001 0>; +}; diff --git a/qcom/kera-cdp-qca6750-ufs2.dtsi b/qcom/kera-cdp-qca6750-ufs2.dtsi new file mode 100644 index 00000000..ffe73fdf --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-cdp.dtsi" +#include "kera_ufs2.dtsi" diff --git a/qcom/kera-cdp-qca6750-ufs3-overlay.dts b/qcom/kera-cdp-qca6750-ufs3-overlay.dts new file mode 100644 index 00000000..448cdba5 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs3-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-cdp-qca6750-ufs3.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS3"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x20001 0>; +}; diff --git a/qcom/kera-cdp-qca6750-ufs3.dtsi b/qcom/kera-cdp-qca6750-ufs3.dtsi new file mode 100644 index 00000000..c75de3b3 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-cdp.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-cdp-qca6750-ufs4-overlay.dts b/qcom/kera-cdp-qca6750-ufs4-overlay.dts new file mode 100644 index 00000000..747e5c50 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs4-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-cdp-qca6750-ufs4.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP + QCA6750 + UFS4"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x40001 0>; +}; diff --git a/qcom/kera-cdp-qca6750-ufs4.dtsi b/qcom/kera-cdp-qca6750-ufs4.dtsi new file mode 100644 index 00000000..10e96578 --- /dev/null +++ b/qcom/kera-cdp-qca6750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-cdp.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-cdp.dtsi b/qcom/kera-cdp.dtsi new file mode 100644 index 00000000..f9d8f28b --- /dev/null +++ b/qcom/kera-cdp.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + +&qupv3_se8_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + goodix,reset-gpio = <&tlmm 16 0x00>; + goodix,irq-gpio = <&tlmm 13 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L22B>; + iovdd-supply = <&L8B>; + goodix,touch-type = "primary"; + goodix,qts_en; + + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/kera-dma-heaps.dtsi b/qcom/kera-dma-heaps.dtsi index ac87057a..f41a1746 100644 --- a/qcom/kera-dma-heaps.dtsi +++ b/qcom/kera-dma-heaps.dtsi @@ -10,10 +10,29 @@ compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = ; memory-region = <&cdsp_secure_heap_cma>; }; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = ; + memory-region = <&qseecom_ta_mem>; + }; }; }; diff --git a/qcom/kera-mtp-qca6750-qmp1000-overlay.dts b/qcom/kera-mtp-qca6750-qmp1000-overlay.dts new file mode 100644 index 00000000..b895e10a --- /dev/null +++ b/qcom/kera-mtp-qca6750-qmp1000-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-qca6750-qmp1000.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + QMP1000 + UFS3"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30008 0>; +}; diff --git a/qcom/kera-mtp-qca6750-qmp1000.dtsi b/qcom/kera-mtp-qca6750-qmp1000.dtsi new file mode 100644 index 00000000..a780aeb3 --- /dev/null +++ b/qcom/kera-mtp-qca6750-qmp1000.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-mtp-qca6750-ufs3-overlay.dts b/qcom/kera-mtp-qca6750-ufs3-overlay.dts new file mode 100644 index 00000000..88543d2c --- /dev/null +++ b/qcom/kera-mtp-qca6750-ufs3-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-qca6750-ufs3.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + UFS3"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/kera-mtp-qca6750-ufs3.dtsi b/qcom/kera-mtp-qca6750-ufs3.dtsi new file mode 100644 index 00000000..a780aeb3 --- /dev/null +++ b/qcom/kera-mtp-qca6750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-mtp-qca6750-ufs4-overlay.dts b/qcom/kera-mtp-qca6750-ufs4-overlay.dts new file mode 100644 index 00000000..6c39dad6 --- /dev/null +++ b/qcom/kera-mtp-qca6750-ufs4-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-qca6750-ufs4.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + QCA6750 + UFS4"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>; +}; diff --git a/qcom/kera-mtp-qca6750-ufs4.dtsi b/qcom/kera-mtp-qca6750-ufs4.dtsi new file mode 100644 index 00000000..f30576eb --- /dev/null +++ b/qcom/kera-mtp-qca6750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-mtp-wcn7750-qmp1000-overlay.dts b/qcom/kera-mtp-wcn7750-qmp1000-overlay.dts new file mode 100644 index 00000000..75259c55 --- /dev/null +++ b/qcom/kera-mtp-wcn7750-qmp1000-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-wcn7750-qmp1000.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + QMP1000 + UFS3"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30008 1>; +}; diff --git a/qcom/kera-mtp-wcn7750-qmp1000.dtsi b/qcom/kera-mtp-wcn7750-qmp1000.dtsi new file mode 100644 index 00000000..a780aeb3 --- /dev/null +++ b/qcom/kera-mtp-wcn7750-qmp1000.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-mtp-wcn7750-ufs3-overlay.dts b/qcom/kera-mtp-wcn7750-ufs3-overlay.dts new file mode 100644 index 00000000..634fe890 --- /dev/null +++ b/qcom/kera-mtp-wcn7750-ufs3-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-wcn7750-ufs3.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + UFS3"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x20008 1>; +}; diff --git a/qcom/kera-mtp-wcn7750-ufs3.dtsi b/qcom/kera-mtp-wcn7750-ufs3.dtsi new file mode 100644 index 00000000..a780aeb3 --- /dev/null +++ b/qcom/kera-mtp-wcn7750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-mtp-wcn7750-ufs4-overlay.dts b/qcom/kera-mtp-wcn7750-ufs4-overlay.dts new file mode 100644 index 00000000..06a3fd50 --- /dev/null +++ b/qcom/kera-mtp-wcn7750-ufs4-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-mtp-wcn7750-ufs4.dtsi" +#include "kera-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP + WCN7750 + UFS4"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 1>; +}; + diff --git a/qcom/kera-mtp-wcn7750-ufs4.dtsi b/qcom/kera-mtp-wcn7750-ufs4.dtsi new file mode 100644 index 00000000..f30576eb --- /dev/null +++ b/qcom/kera-mtp-wcn7750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-mtp.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-mtp.dtsi b/qcom/kera-mtp.dtsi new file mode 100644 index 00000000..fe3b8f24 --- /dev/null +++ b/qcom/kera-mtp.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include "pmk8550.dtsi" + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + +&wcd_usbss { + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_wcd"; + nvmem-cells = <&usb_mode>; + nvmem-cell-names = "usb_mode"; +}; + +&qupv3_se8_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + goodix,reset-gpio = <&tlmm 16 0x00>; + goodix,irq-gpio = <&tlmm 13 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L22B>; + iovdd-supply = <&L8B>; + goodix,touch-type = "primary"; + goodix,qts_en; + + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/kera-oemvm-atp.dts b/qcom/kera-oemvm-atp.dts new file mode 100644 index 00000000..6413e8f3 --- /dev/null +++ b/qcom/kera-oemvm-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + + qcom,board-id = <33 0>; +}; diff --git a/qcom/kera-oemvm-atp.dtsi b/qcom/kera-oemvm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-oemvm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-oemvm-cdp.dts b/qcom/kera-oemvm-cdp.dts new file mode 100644 index 00000000..0120d39e --- /dev/null +++ b/qcom/kera-oemvm-cdp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/qcom/kera-oemvm-cdp.dtsi b/qcom/kera-oemvm-cdp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-oemvm-cdp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-oemvm-mtp.dts b/qcom/kera-oemvm-mtp.dts new file mode 100644 index 00000000..8c35e062 --- /dev/null +++ b/qcom/kera-oemvm-mtp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, <0x30008 1>; +}; diff --git a/qcom/kera-oemvm-mtp.dtsi b/qcom/kera-oemvm-mtp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-oemvm-mtp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-oemvm-qrd.dts b/qcom/kera-oemvm-qrd.dts new file mode 100644 index 00000000..bbc32acd --- /dev/null +++ b/qcom/kera-oemvm-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/qcom/kera-oemvm-qrd.dtsi b/qcom/kera-oemvm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-oemvm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-oemvm-rcm.dts b/qcom/kera-oemvm-rcm.dts new file mode 100644 index 00000000..e9e5cb10 --- /dev/null +++ b/qcom/kera-oemvm-rcm.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, <0x30015 1>; +}; diff --git a/qcom/kera-oemvm-rcm.dtsi b/qcom/kera-oemvm-rcm.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-oemvm-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-oemvm.dtsi b/qcom/kera-oemvm.dtsi index cd6f0bf4..b72e35f9 100644 --- a/qcom/kera-oemvm.dtsi +++ b/qcom/kera-oemvm.dtsi @@ -8,7 +8,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <659 0x10000>; + qcom,msm-id = <659 0x10000>, <686 0x10000>; interrupt-parent = <&vgic>; chosen { @@ -163,6 +163,67 @@ allocate-base; }; + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x000000C>; + }; + + test-dbl-oemvm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-oemvm"; + qcom,label = <0x5>; + peer-default; + }; + + test-dbl-oemvm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-oemvm-source"; + qcom,label = <0x5>; + peer-default; + }; + + test-msgq-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x5>; + peer-default; + }; + + test-large-dmabuf-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xe>; + peer-default; + }; + + msgqsock-msgq-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/msgqsock-msgq-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + peer = "vm-name:qcom,trustedvm"; + qcom,label = <0x3>; + }; + + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x8>; + allocate-base; + }; + }; + }; }; @@ -206,10 +267,75 @@ clock-frequency = <19200000>; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ + qcom,vmid = <49>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "oem_vm"; + }; + + virtio_mem_device { + compatible = "qcom,virtio-mem"; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x10000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + }; + + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; }; + qcom_mem_object { + compatible = "qcom,mem-object"; + }; + + qmsgq-gunyah { + compatible = "qcom,qmsgq-gh"; + msgq-label = <3>; + }; + + qcom,qrtr { + compatible = "qcom,qrtr"; + qcom,node-id = <21>; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <8>; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <512>; diff --git a/qcom/kera-pinctrl.dtsi b/qcom/kera-pinctrl.dtsi index 1aa1ce71..3eef2cd5 100644 --- a/qcom/kera-pinctrl.dtsi +++ b/qcom/kera-pinctrl.dtsi @@ -4,6 +4,1600 @@ */ &tlmm { + i2s0_sck { + i2s0_sck_sleep: i2s0_sck_sleep { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sck_active: i2s0_sck_active { + mux { + pins = "gpio60"; + function = "i2s0_sck"; + }; + + config { + pins = "gpio60"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_ws { + i2s0_ws_sleep: i2s0_ws_sleep { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_ws_active: i2s0_ws_active { + mux { + pins = "gpio61"; + function = "i2s0_ws"; + }; + + config { + pins = "gpio61"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_sd0 { + i2s0_sd0_sleep: i2s0_sd0_sleep { + mux { + pins = "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sd0_active: i2s0_sd0_active { + mux { + pins = "gpio62"; + function = "i2s0_data0"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + i2s0_sd1 { + i2s0_sd1_sleep: i2s0_sd1_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + i2s0_sd1_active: i2s0_sd1_active { + mux { + pins = "gpio63"; + function = "i2s0_data1"; + }; + + config { + pins = "gpio63"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + + /* WCD reset pin */ + wcd_reset_active: wcd_reset_active { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <16>; + output-high; + }; + }; + + wcd_reset_sleep: wcd_reset_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + +/* WSA speaker reset pins North Pins*/ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio59"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + +/* WSA speaker reset pins south Pins*/ + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active { + mux { + pins = "gpio28"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active { + mux { + pins = "gpio29"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active { + mux { + pins = "gpio28"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active { + mux { + pins = "gpio29"; + function = "qup1_se0_l1"; + }; + + config { + pins = "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active { + mux { + pins = "gpio30"; + function = "qup1_se0_l2"; + }; + + config { + pins = "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { + mux { + pins = "gpio31"; + function = "qup1_se0_l3"; + }; + + config { + pins = "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active { + mux { + pins = "gpio32"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active { + mux { + pins = "gpio33"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active { + mux { + pins = "gpio32"; + function = "qup1_se1_l0"; + }; + + config { + pins = "gpio32"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active { + mux { + pins = "gpio33"; + function = "qup1_se1_l1"; + }; + + config { + pins = "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active { + mux { + pins = "gpio34"; + function = "qup1_se1_l2"; + }; + + config { + pins = "gpio34"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active { + mux { + pins = "gpio35"; + function = "qup1_se1_l3"; + }; + + config { + pins = "gpio35"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active { + mux { + pins = "gpio52"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active { + mux { + pins = "gpio53"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio52", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active { + mux { + pins = "gpio52"; + function = "qup1_se2_l0"; + }; + + config { + pins = "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active { + mux { + pins = "gpio53"; + function = "qup1_se2_l1"; + }; + + config { + pins = "gpio53"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active { + mux { + pins = "gpio54"; + function = "qup1_se2_l2_mira"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup1_se2_l3_mira"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active { + mux { + pins = "gpio44"; + function = "qup1_se3_l0"; + }; + + config { + pins = "gpio44"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active { + mux { + pins = "gpio45"; + function = "qup1_se3_l1"; + }; + + config { + pins = "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active { + mux { + pins = "gpio46"; + function = "qup1_se3_l2"; + }; + + config { + pins = "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active { + mux { + pins = "gpio47"; + function = "qup1_se3_l3"; + }; + + config { + pins = "gpio47"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { + mux { + pins = "gpio36"; + function = "qup1_se4_l0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { + mux { + pins = "gpio37"; + function = "qup1_se4_l1"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se5_4uart_pins: qupv3_se5_4uart_pins { + qupv3_se5_default_cts: qupv3_se5_default_cts { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_default_rts: qupv3_se5_default_rts { + mux { + pins = "gpio133"; + function = "gpio"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_default_tx: qupv3_se5_default_tx { + mux { + pins = "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_default_rx: qupv3_se5_default_rx { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_cts: qupv3_se5_cts { + mux { + pins = "gpio132"; + function = "qup1_se5_l0"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_rts: qupv3_se5_rts { + mux { + pins = "gpio133"; + function = "qup1_se5_l1"; + }; + + config { + pins = "gpio133"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se5_tx: qupv3_se5_tx { + mux { + pins = "gpio134"; + function = "qup1_se5_l2"; + }; + + config { + pins = "gpio134"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_rx_active: qupv3_se5_rx_active { + mux { + pins = "gpio135"; + function = "qup1_se5_l3"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* RX to be in gpio mode for sleep config */ + qupv3_se5_rx_wake: qupv3_se5_rx_wake { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active { + mux { + pins = "gpio40"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active { + mux { + pins = "gpio54"; + function = "qup1_se6_l1_mirb"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio40", "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio54"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active { + mux { + pins = "gpio40"; + function = "qup1_se6_l0"; + }; + + config { + pins = "gpio40"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active { + mux { + pins = "gpio54"; + function = "qup1_se6_l1_mirb"; + }; + + config { + pins = "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active { + mux { + pins = "gpio42"; + function = "qup1_se6_l2"; + }; + + config { + pins = "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active { + mux { + pins = "gpio55"; + function = "qup1_se6_l3_mirb"; + }; + + config { + pins = "gpio55"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio40", "gpio54", + "gpio42", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio40", "gpio54", + "gpio42", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active { + mux { + pins = "gpio81"; + function = "qup1_se7_l0_mira"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active { + mux { + pins = "gpio80"; + function = "qup1_se7_l1_mira"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio81", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio80"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active { + mux { + pins = "gpio81"; + function = "qup1_se7_l0_mira"; + }; + + config { + pins = "gpio81"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active { + mux { + pins = "gpio80"; + function = "qup1_se7_l1_mira"; + }; + + config { + pins = "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active { + mux { + pins = "gpio114"; + function = "qup1_se7_l2"; + }; + + config { + pins = "gpio114"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active { + mux { + pins = "gpio78"; + function = "qup1_se7_l3"; + }; + + config { + pins = "gpio78"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio81", "gpio80", + "gpio114", "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio80", + "gpio114", "gpio78"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active { + mux { + pins = "gpio0"; + function = "qup2_se0_l0"; + }; + + config { + pins = "gpio0"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active { + mux { + pins = "gpio1"; + function = "qup2_se0_l1"; + }; + + config { + pins = "gpio1"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active { + mux { + pins = "gpio2"; + function = "qup2_se0_l2"; + }; + + config { + pins = "gpio2"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active { + mux { + pins = "gpio3"; + function = "qup2_se0_l3"; + }; + + config { + pins = "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active { + mux { + pins = "gpio4"; + function = "qup2_se1_l0"; + }; + + config { + pins = "gpio4"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active { + mux { + pins = "gpio5"; + function = "qup2_se1_l1"; + }; + + config { + pins = "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active { + mux { + pins = "gpio6"; + function = "qup2_se1_l2"; + }; + + config { + pins = "gpio6"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active { + mux { + pins = "gpio7"; + function = "qup2_se1_l3"; + }; + + config { + pins = "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active { + mux { + pins = "gpio8"; + function = "qup2_se2_l0"; + }; + + config { + pins = "gpio8"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active { + mux { + pins = "gpio9"; + function = "qup2_se2_l1"; + }; + + config { + pins = "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active { + mux { + pins = "gpio10"; + function = "qup2_se2_l2"; + }; + + config { + pins = "gpio10"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active { + mux { + pins = "gpio11"; + function = "qup2_se2_l3"; + }; + + config { + pins = "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active { + mux { + pins = "gpio79"; + function = "qup2_se3_l0_mira"; + }; + + config { + pins = "gpio79"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active { + mux { + pins = "gpio97"; + function = "qup2_se3_l1_mira"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio79", "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio79", "gpio97"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active { + mux { + pins = "gpio79"; + function = "qup2_se3_l0_mira"; + }; + + config { + pins = "gpio79"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active { + mux { + pins = "gpio97"; + function = "qup2_se3_l1_mira"; + }; + + config { + pins = "gpio97"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active { + mux { + pins = "gpio100"; + function = "qup2_se3_l2"; + }; + + config { + pins = "gpio100"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active { + mux { + pins = "gpio116"; + function = "qup2_se3_l3"; + }; + + config { + pins = "gpio116"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio79", "gpio97", + "gpio100", "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio79", "gpio97", + "gpio100", "gpio116"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active { + mux { + pins = "gpio12"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active { + mux { + pins = "gpio13"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active { + mux { + pins = "gpio12"; + function = "qup2_se4_l0"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active { + mux { + pins = "gpio13"; + function = "qup2_se4_l1"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active { + mux { + pins = "gpio26"; + function = "qup2_se4_l2"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active { + mux { + pins = "gpio27"; + function = "qup2_se4_l3"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + qupv3_se13_2uart_pins: qupv3_se13_2uart_pins { qupv3_se13_2uart_tx_active: qupv3_se13_2uart_tx_active { mux { @@ -44,4 +1638,345 @@ }; }; }; + + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_sda_active: qupv3_se14_i2c_sda_active { + mux { + pins = "gpio20"; + function = "qup2_se6_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se14_i2c_scl_active: qupv3_se14_i2c_scl_active { + mux { + pins = "gpio21"; + function = "qup2_se6_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_miso_active: qupv3_se14_spi_miso_active { + mux { + pins = "gpio20"; + function = "qup2_se6_l0"; + }; + + config { + pins = "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_mosi_active: qupv3_se14_spi_mosi_active { + mux { + pins = "gpio21"; + function = "qup2_se6_l1"; + }; + + config { + pins = "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_clk_active: qupv3_se14_spi_clk_active { + mux { + pins = "gpio22"; + function = "qup2_se6_l2"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_cs_active: qupv3_se14_spi_cs_active { + mux { + pins = "gpio23"; + function = "qup2_se6_l3"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active { + mux { + pins = "gpio27"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active { + mux { + pins = "gpio26"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + qcom,i2c_pull; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio27", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio26"; + drive-strength = <2>; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active { + mux { + pins = "gpio27"; + function = "qup2_se7_l0"; + }; + + config { + pins = "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active { + mux { + pins = "gpio26"; + function = "qup2_se7_l1"; + }; + + config { + pins = "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active { + mux { + pins = "gpio13"; + function = "qup2_se7_l2"; + }; + + config { + pins = "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active { + mux { + pins = "gpio12"; + function = "qup2_se7_l3"; + }; + + config { + pins = "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio27", "gpio26", + "gpio13", "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio26", + "gpio13", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + /* touchscreen pins */ + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio16", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio13"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio16", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* sdcc2 pins */ + sdc2_on: sdc2_on { + clk { + pins = "gpio62"; + function = "SDC2_CLK"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "gpio51"; + function = "SDC2_CMD"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "gpio38", "gpio39", "gpio48", "gpio49"; + function = "SDC2_DATA"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio58"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "gpio62"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "gpio38", "gpio39", "gpio48", "gpio49"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio58"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; diff --git a/qcom/kera-pm7550ba.dtsi b/qcom/kera-pm7550ba.dtsi new file mode 100644 index 00000000..acd6f6ef --- /dev/null +++ b/qcom/kera-pm7550ba.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-pm7550ba.dtsi" + +&pmic_glink_debug { + /delete-node/ i2c@104; + /delete-node/ spmi@200; + + i2c@104 { + reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1500@69 { + compatible = "qcom,i2c-pmic"; + reg = <0x69>; + qcom,can-sleep; + }; + + qcom,smb1500@68 { + compatible = "qcom,i2c-pmic"; + reg = <0x68>; + qcom,can-sleep; + }; + }; +}; + +&pmic_glink_adc { + /delete-node/ smb1398_1_iin; + /delete-node/ smb1398_1_ichg; + /delete-node/ smb1398_1_die_temp; + + smb1500_1_iin { + reg = <0x1046901>; + label = "smb1393_1_iin"; + }; + + smb1500_1_ichg { + reg = <0x1046902>; + label = "smb1393_1_ichg"; + }; + + smb1500_1_die_temp { + reg = <0x1046903>; + label = "smb1393_1_die_temp"; + }; + + smb1500_2_iin { + reg = <0x1046801>; + label = "smb1393_2_iin"; + }; + + smb1500_2_ichg { + reg = <0x1046802>; + label = "smb1393_2_ichg"; + }; + + smb1500_2_die_temp { + reg = <0x1046803>; + label = "smb1393_2_die_temp"; + }; +}; + diff --git a/qcom/kera-pmic-overlay.dtsi b/qcom/kera-pmic-overlay.dtsi new file mode 100644 index 00000000..a523d4f0 --- /dev/null +++ b/qcom/kera-pmic-overlay.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-pmic-overlay.dtsi" + +&pm8550ve_f { + status = "disabled"; +}; + +&pm8550ve_f_temp_alarm { + status = "disabled"; +}; + +&pm8550ve_f_tz { + status = "disabled"; +}; + +&pmk8550_sdam_1 { + ufs_dev: ufs_dev@af { + reg = <0xaf 0x1>; + bits = <0 0>; + }; +}; diff --git a/qcom/kera-pmiv0102.dtsi b/qcom/kera-pmiv0102.dtsi index 94ec6fbd..f933587c 100644 --- a/qcom/kera-pmiv0102.dtsi +++ b/qcom/kera-pmiv0102.dtsi @@ -10,7 +10,5 @@ }; &pmiv010x_amoled_ecm { - status = "ok" + status = "ok"; }; - - diff --git a/qcom/kera-qrd-wcn7750-ufs2-overlay.dts b/qcom/kera-qrd-wcn7750-ufs2-overlay.dts new file mode 100644 index 00000000..10cd2559 --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs2-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-qrd-wcn7750-ufs2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS2"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x3000B 0>; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs2.dtsi b/qcom/kera-qrd-wcn7750-ufs2.dtsi new file mode 100644 index 00000000..5743706b --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-qrd.dtsi" +#include "kera_ufs2.dtsi" diff --git a/qcom/kera-qrd-wcn7750-ufs3-overlay.dts b/qcom/kera-qrd-wcn7750-ufs3-overlay.dts new file mode 100644 index 00000000..533095a1 --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs3-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-qrd-wcn7750-ufs3.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS3"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x2000B 0>; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs3.dtsi b/qcom/kera-qrd-wcn7750-ufs3.dtsi new file mode 100644 index 00000000..0a4228ff --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-qrd.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-qrd-wcn7750-ufs4-overlay.dts b/qcom/kera-qrd-wcn7750-ufs4-overlay.dts new file mode 100644 index 00000000..0407343c --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs4-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-qrd-wcn7750-ufs4.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD + WCN7750 + UFS4"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/kera-qrd-wcn7750-ufs4.dtsi b/qcom/kera-qrd-wcn7750-ufs4.dtsi new file mode 100644 index 00000000..d28259d2 --- /dev/null +++ b/qcom/kera-qrd-wcn7750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-qrd.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-qrd.dtsi b/qcom/kera-qrd.dtsi new file mode 100644 index 00000000..30bb3c7c --- /dev/null +++ b/qcom/kera-qrd.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; + +&qupv3_se7_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + }; +}; + +&qupv3_se8_spi { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; + + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&tlmm>; + interrupts = <13 0x2008>; + goodix,reset-gpio = <&tlmm 16 0x00>; + goodix,irq-gpio = <&tlmm 13 0x2008>; + goodix,irq-flags = <2>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,firmware-name = "goodix_firmware_spi.bin"; + goodix,config-name = "goodix_cfg_group_spi.bin"; + goodix,avdd-name = "avdd"; + goodix,iovdd-name = "iovdd"; + avdd-supply = <&L22B>; + iovdd-supply = <&L8B>; + goodix,touch-type = "primary"; + goodix,qts_en; + + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; + +&pmic_glink_debug { + i2c@104 { + reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */ + #address-cells = <1>; + #size-cells = <0>; + qcom,bus-type = "i2c"; + + qcom,smb1393@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + qcom,can-sleep; + }; + }; +}; + +&pmic_glink_adc { + status = "ok"; + + smb1393_1_iin { + reg = <0x1043401>; + label = "smb1393_1_iin"; + }; + + smb1393_1_ichg { + reg = <0x1043402>; + label = "smb1393_1_ichg"; + }; + + smb1393_1_die_temp { + reg = <0x1043403>; + label = "smb1393_1_die_temp"; + }; +}; diff --git a/qcom/kera-qupv3.dtsi b/qcom/kera-qupv3.dtsi index 5f79ee9c..643c8d7e 100644 --- a/qcom/kera-qupv3.dtsi +++ b/qcom/kera-qupv3.dtsi @@ -4,8 +4,452 @@ */ &soc { - /* QUPv3_2 Wrapper Instance */ - qupv3_2: qcom,qupv3_1_geni_se@8c0000 { + /* QUPv3 SE Instances + * Qup1 0: SE 0 + * Qup1 1: SE 1 + * Qup1 2: SE 2 + * Qup1 3: SE 3 + * Qup1 4: SE 4 + * Qup1 5: SE 5 + * Qup1 6: SE 6 + * Qup1 7: SE 7 + * Qup2 0: SE 8 + * Qup2 1: SE 9 + * Qup2 2: SE 10 + * Qup2 3: SE 11 + * Qup2 4: SE 12 + * Qup2 5: SE 13 + * Qup2 6: SE 14 + * Qup2 7: SE 15 + */ + + qup1_gpi_iommu_region: qup1_gpi_iommu_region { + iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xFFE00000>; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb6 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; + qcom,ev-factor = <1>; + memory-region = <&qup1_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup1_se_iommu_region: qup1_se_iommu_region { + iommu-addresses = <&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0x0>; + memory-region = <&qup1_se_iommu_region>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + ranges; + status = "ok"; + + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 2>, + <&gpi_dma1 1 0 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, + <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 2>, + <&gpi_dma1 1 0 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + reg = <0xa84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>, + <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + reg = <0xa88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>, + <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + reg = <0xa8c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>, + <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 1024 0>, + <&gpi_dma1 1 4 3 1024 0>; + dma-names = "tx", "rx"; + qcom,shared; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se5_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 135 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "active", "sleep", "shutdown"; + pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, + <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; + pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>, + <&qupv3_se5_tx>, <&qupv3_se5_rx_active>; + pinctrl-2 = <&qupv3_se5_cts>, <&qupv3_se5_rts>, + <&qupv3_se5_tx>, <&qupv3_se5_rx_wake>; + pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, + <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; + qcom,wakeup-byte = <0xFD>; + qcom,suspend-ignore-children; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a98000 { + compatible = "qcom,i2c-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 6 3 64 0>, + <&gpi_dma1 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a98000 { + compatible = "qcom,spi-geni"; + reg = <0xa98000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>, + <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 6 1 64 0>, + <&gpi_dma1 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a9c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma1 0 7 3 64 0>, + <&gpi_dma1 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a9c000 { + compatible = "qcom,spi-geni"; + reg = <0xa9c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>, + <&aggre1_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>, + <&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + dmas = <&gpi_dma1 0 7 1 64 0>, + <&gpi_dma1 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + qup2_gpi_iommu_region: qup2_gpi_iommu_region { + iommu-addresses = <&gpi_dma2 0x0 0x100000>, <&gpi_dma2 0x200000 0xFFE00000>; + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x436 0x0>; + qcom,max-num-gpii = <12>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; + qcom,ev-factor = <1>; + memory-region = <&qup2_gpi_iommu_region>; + qcom,gpi-ee-offset = <0x10000>; + dma-coherent; + status = "ok"; + }; + + qup2_se_iommu_region: qup2_se_iommu_region { + iommu-addresses = <&qupv3_2 0x0 0x40000000>, <&qupv3_2 0x50000000 0xb0000000>; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x8c0000 0x2000>; #address-cells = <1>; @@ -13,9 +457,250 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0x0>; + memory-region = <&qup2_se_iommu_region>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + dma-coherent; ranges; status = "ok"; + + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma2 0 0 3 64 2>, + <&gpi_dma2 1 0 3 64 2>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, + <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + dmas = <&gpi_dma2 0 0 1 64 2>, + <&gpi_dma2 1 0 1 64 2>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + dmas = <&gpi_dma2 0 1 3 64 0>, + <&gpi_dma2 1 1 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@884000 { + compatible = "qcom,spi-geni"; + reg = <0x884000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>, + <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + dmas = <&gpi_dma2 0 1 1 64 0>, + <&gpi_dma2 1 1 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma2 0 2 3 64 0>, + <&gpi_dma2 1 2 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@888000 { + compatible = "qcom,spi-geni"; + reg = <0x888000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>, + <&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + dmas = <&gpi_dma2 0 2 1 64 0>, + <&gpi_dma2 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + dmas = <&gpi_dma2 0 3 3 64 0>, + <&gpi_dma2 1 3 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + reg = <0x88c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>, + <&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + dmas = <&gpi_dma2 0 3 1 64 0>, + <&gpi_dma2 1 3 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + dmas = <&gpi_dma2 0 4 3 64 0>, + <&gpi_dma2 1 4 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_spi: spi@890000 { + compatible = "qcom,spi-geni"; + reg = <0x890000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>, + <&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + dmas = <&gpi_dma2 0 4 1 64 0>, + <&gpi_dma2 1 4 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + /* Debug UART Instance */ qupv3_se13_2uart: qcom,qup_uart@894000 { compatible = "qcom,geni-debug-uart"; @@ -24,10 +709,109 @@ interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se13_2uart_tx_active>, <&qupv3_se13_2uart_rx_active>; pinctrl-1 = <&qupv3_se13_2uart_sleep>; status = "disabled"; }; + + qupv3_se14_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_sda_active>, <&qupv3_se14_i2c_scl_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + dmas = <&gpi_dma2 0 6 3 64 0>, + <&gpi_dma2 1 6 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se14_spi: spi@898000 { + compatible = "qcom,spi-geni"; + reg = <0x898000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_mosi_active>, <&qupv3_se14_spi_miso_active>, + <&qupv3_se14_spi_clk_active>, <&qupv3_se14_spi_cs_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + dmas = <&gpi_dma2 0 6 1 64 0>, + <&gpi_dma2 1 6 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + dmas = <&gpi_dma2 0 7 3 64 0>, + <&gpi_dma2 1 7 3 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + interconnects = + <&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>, + <&aggre2_noc MASTER_QUP_2 &mc_virt SLAVE_EBI1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, + <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + dmas = <&gpi_dma2 0 7 1 64 0>, + <&gpi_dma2 1 7 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; }; }; diff --git a/qcom/kera-rcm-qca6750-ufs2-overlay.dts b/qcom/kera-rcm-qca6750-ufs2-overlay.dts new file mode 100644 index 00000000..df5f9933 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs2-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-qca6750-ufs2.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS2"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30015 0>; +}; diff --git a/qcom/kera-rcm-qca6750-ufs2.dtsi b/qcom/kera-rcm-qca6750-ufs2.dtsi new file mode 100644 index 00000000..dc823592 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs2.dtsi" diff --git a/qcom/kera-rcm-qca6750-ufs3-overlay.dts b/qcom/kera-rcm-qca6750-ufs3-overlay.dts new file mode 100644 index 00000000..b41df9c0 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs3-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-qca6750-ufs3.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS3"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x20015 0>; +}; diff --git a/qcom/kera-rcm-qca6750-ufs3.dtsi b/qcom/kera-rcm-qca6750-ufs3.dtsi new file mode 100644 index 00000000..99203b93 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-rcm-qca6750-ufs4-overlay.dts b/qcom/kera-rcm-qca6750-ufs4-overlay.dts new file mode 100644 index 00000000..973cd065 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs4-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-qca6750-ufs4.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM + QCA6750 + UFS4"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>; +}; diff --git a/qcom/kera-rcm-qca6750-ufs4.dtsi b/qcom/kera-rcm-qca6750-ufs4.dtsi new file mode 100644 index 00000000..4834e869 --- /dev/null +++ b/qcom/kera-rcm-qca6750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-rcm-wcn7750-ufs2-overlay.dts b/qcom/kera-rcm-wcn7750-ufs2-overlay.dts new file mode 100644 index 00000000..2edce214 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs2-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-wcn7750-ufs2.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM + WCN7750 + UFS2"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x30015 1>; +}; diff --git a/qcom/kera-rcm-wcn7750-ufs2.dtsi b/qcom/kera-rcm-wcn7750-ufs2.dtsi new file mode 100644 index 00000000..dc823592 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs2.dtsi" diff --git a/qcom/kera-rcm-wcn7750-ufs3-overlay.dts b/qcom/kera-rcm-wcn7750-ufs3-overlay.dts new file mode 100644 index 00000000..00131475 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs3-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-wcn7750-ufs3.dtsi" +#include "kera-pmiv0102.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KERA RCM + WCN7750 + UFS3"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x20015 1>; +}; diff --git a/qcom/kera-rcm-wcn7750-ufs3.dtsi b/qcom/kera-rcm-wcn7750-ufs3.dtsi new file mode 100644 index 00000000..99203b93 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs3.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs3.dtsi" diff --git a/qcom/kera-rcm-wcn7750-ufs4-overlay.dts b/qcom/kera-rcm-wcn7750-ufs4-overlay.dts new file mode 100644 index 00000000..d3816403 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs4-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-rcm-wcn7750-ufs4.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM + WCN7750 + UFS4"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 1>; +}; diff --git a/qcom/kera-rcm-wcn7750-ufs4.dtsi b/qcom/kera-rcm-wcn7750-ufs4.dtsi new file mode 100644 index 00000000..4834e869 --- /dev/null +++ b/qcom/kera-rcm-wcn7750-ufs4.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-rcm.dtsi" +#include "kera_ufs4.dtsi" diff --git a/qcom/kera-rcm.dtsi b/qcom/kera-rcm.dtsi new file mode 100644 index 00000000..fccccc16 --- /dev/null +++ b/qcom/kera-rcm.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&sdhc_2 { + vdd-supply = <&L13B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 976270>; + + vdd-io-supply = <&L23B>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 5830>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + qcom,uses_level_shifter; + + status = "ok"; +}; diff --git a/qcom/kera-regulators.dtsi b/qcom/kera-regulators.dtsi new file mode 100644 index 00000000..1b90a63c --- /dev/null +++ b/qcom/kera-regulators.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&apps_rsc_drv2 { + rpmh-regulator-smpb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb1"; + qcom,regulator-type = "pmic5-ftsmps"; + qcom,supported-modes = ; + qcom,mode-threshold-currents = <0 200000>; + + S1B: pmxr2230_s1: vreg-pmxr2230-s1 { + regulator-name = "pmxr2230_s1"; + qcom,set = ; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2044000>; + qcom,init-voltage = <1856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpb2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb2"; + qcom,regulator-type = "pmic5-ftsmps"; + qcom,supported-modes = ; + qcom,mode-threshold-currents = <0 200000>; + + S2B: pmxr2230_s2: vreg-pmxr2230-s2 { + regulator-name = "pmxr2230_s2"; + qcom,set = ; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <2092000>; + qcom,init-voltage = <1256000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpb3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb3"; + + S3B: pmxr2230_s3: vreg-pmxr2230-s3 { + regulator-name = "pmxr2230_s3"; + qcom,set = ; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <2736000>; + qcom,init-voltage = <952000>; + }; + }; + + rpmh-regulator-smpb4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb4"; + + S4B: pmxr2230_s4: vreg-pmxr2230-s4 { + regulator-name = "pmxr2230_s4"; + qcom,set = ; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2700000>; + qcom,init-voltage = <2156000>; + }; + }; + + rpmh-regulator-nsplvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "nsp.lvl"; + + VDD_NSP1_LEVEL: + S5B_LEVEL: + pmxr2230_s5_level: vreg-pmxr2230-s5-level { + regulator-name = "pmxr2230_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1B: pmxr2230_l1: vreg-pmxr2230-l1 { + regulator-name = "pmxr2230_l1"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2B: pmxr2230_l2: vreg-pmxr2230-l2 { + regulator-name = "pmxr2230_l2"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lmx.lvl"; + + VDD_LPI_MX_LEVEL: + L3B_LEVEL: + pmxr2230_l3_level: vreg-pmxr2230-l3-level { + regulator-name = "pmxr2230_l3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L4B: pmxr2230_l4: vreg-pmxr2230-l4 { + regulator-name = "pmxr2230_l4"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L5B: pmxr2230_l5: vreg-pmxr2230-l5 { + regulator-name = "pmxr2230_l5"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L6B: pmxr2230_l6: vreg-pmxr2230-l6 { + regulator-name = "pmxr2230_l6"; + qcom,set = ; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L7B: pmxr2230_l7: vreg-pmxr2230-l7 { + regulator-name = "pmxr2230_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L8B: pmxr2230_l8: vreg-pmxr2230-l8 { + regulator-name = "pmxr2230_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L9B: pmxr2230_l9: vreg-pmxr2230-l9 { + regulator-name = "pmxr2230_l9"; + qcom,set = ; + regulator-min-microvolt = <756000>; + regulator-max-microvolt = <816000>; + qcom,init-voltage = <756000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L10B: pmxr2230_l10: vreg-pmxr2230-l10 { + regulator-name = "pmxr2230_l10"; + qcom,set = ; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + qcom,init-voltage = <866000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L11B: pmxr2230_l11: vreg-pmxr2230-l11 { + regulator-name = "pmxr2230_l11"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + regulator-always-on; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L12B: pmxr2230_l12: vreg-pmxr2230-l12 { + regulator-name = "pmxr2230_l12"; + qcom,set = ; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L13B: pmxr2230_l13: vreg-pmxr2230-l13 { + regulator-name = "pmxr2230_l13"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L14B: pmxr2230_l14: vreg-pmxr2230-l14 { + regulator-name = "pmxr2230_l14"; + qcom,set = ; + regulator-min-microvolt = <2650000>; + regulator-max-microvolt = <2940000>; + qcom,init-voltage = <2650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L15B: pmxr2230_l15: vreg-pmxr2230-l15 { + regulator-name = "pmxr2230_l15"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L16B: pmxr2230_l16: vreg-pmxr2230-l16 { + regulator-name = "pmxr2230_l16"; + qcom,set = ; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2900000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L17B: pmxr2230_l17: vreg-pmxr2230-l17 { + regulator-name = "pmxr2230_l17"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3104000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob18 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L18B: pmxr2230_l18: vreg-pmxr2230-l18 { + regulator-name = "pmxr2230_l18"; + qcom,set = ; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1600000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob19 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L19B: pmxr2230_l19: vreg-pmxr2230-l19 { + regulator-name = "pmxr2230_l19"; + qcom,set = ; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2600000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L20B: pmxr2230_l20: vreg-pmxr2230-l20 { + regulator-name = "pmxr2230_l20"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L21B: pmxr2230_l21: vreg-pmxr2230-l21 { + regulator-name = "pmxr2230_l21"; + qcom,set = ; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob22 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob22"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L22B: pmxr2230_l22: vreg-pmxr2230-l22 { + regulator-name = "pmxr2230_l22"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob23 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob23"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L23B: pmxr2230_l23: vreg-pmxr2230-l23 { + regulator-name = "pmxr2230_l23"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobb1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + BOB: + pmxr2230_bob: vreg-pmxr2230-bob1 { + regulator-name = "pmxr2230_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MX_LEVEL: + VDD_MXA_LEVEL: + S1D_LEVEL: + pm_v6d_s1_level: pm_v6d-s1-level { + regulator-name = "pm_v6d_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MX_LEVEL_AO: + S1D_LEVEL_AO: + pm_v6d_s1_level_ao: pm_v6d-s1-level-ao { + regulator-name = "pm_v6d_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "ebi.lvl"; + + VDD_EBI_LEVEL: + S3D_LEVEL: + pm_v6d_s3_level: pm_v6d-s3-level { + regulator-name = "pm_v6d_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + + VDD_MODEM_LEVEL: + S4D_LEVEL: + pm_v6d_s4_level: pm_v6d-s4-level { + regulator-name = "pm_v6d_s4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: + S5D_LEVEL: + pm_v6d_s5_level: pm_v6d-s5-level { + regulator-name = "pm_v6d_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S5D_LEVEL_AO: + pm_v6d_s5_level_ao: pm_v6d-s5-level-ao { + regulator-name = "pm_v6d_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldod1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1D: pm_v6d_l1: vreg-pm_v6d-l1 { + regulator-name = "pm_v6d_l1"; + qcom,set = ; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldod2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldod2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2D: pm_v6d_l2: vreg-pm_v6d-l2 { + regulator-name = "pm_v6d_l2"; + qcom,set = ; + regulator-min-microvolt = <556000>; + regulator-max-microvolt = <816000>; + qcom,init-voltage = <556000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "lcx.lvl"; + + VDD_LPI_CX_LEVEL: + L3D_LEVEL: + pm_v6d_l3_level: pm_v6d-l3-level { + regulator-name = "pm_v6d_l3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "gfx.lvl"; + + VDD_GFX_LEVEL: + S1G_LEVEL: + pm_v6g_s1_level: pm_v6g-s1-level { + regulator-name = "pm_v6g_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpg3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg3"; + + S3G: pm_v6g_s3: vreg-pm_v6g-s3 { + regulator-name = "pm_v6g_s3"; + qcom,set = ; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1010000>; + }; + }; + + rpmh-regulator-smpg6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg6"; + + S6G: pm_v6g_s6: vreg-pm_v6g-s6 { + regulator-name = "pm_v6g_s6"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <300000>; + }; + }; + + rpmh-regulator-ldog1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1G: pm_v6g_l1: vreg-pm_v6g-l1 { + regulator-name = "pm_v6g_l1"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2G: pm_v6g_l2: vreg-pm_v6g-l2 { + regulator-name = "pm_v6g_l2"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldog3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldog3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3G: pm_v6g_l3: vreg-pm_v6g-l3 { + regulator-name = "pm_v6g_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpi1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpi1"; + + S1I: pmg1110i_s1: vreg-pmg1110i-s1 { + regulator-name = "pmg1110i_s1"; + qcom,set = ; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + qcom,init-voltage = <904000>; + }; + }; + + rpmh-regulator-smpj1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpj1"; + + S1J: pmg1110j_s1: vreg-pmg1110j-s1 { + regulator-name = "pmg1110j_s1"; + qcom,set = ; + regulator-min-microvolt = <556000>; + regulator-max-microvolt = <816000>; + qcom,init-voltage = <556000>; + }; + }; + + rpmh-regulator-ldok1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1K: pmr735b_l1: vreg-pmr735b-l1 { + regulator-name = "pmr735b_l1"; + qcom,set = ; + regulator-min-microvolt = <806000>; + regulator-max-microvolt = <901000>; + qcom,init-voltage = <806000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2K: pmr735b_l2: vreg-pmr735b-l2 { + regulator-name = "pmr735b_l2"; + qcom,set = ; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <969000>; + qcom,init-voltage = <920000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L3K: pmr735b_l3: vreg-pmr735b-l3 { + regulator-name = "pmr735b_l3"; + qcom,set = ; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1080000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + + L4K: pmr735b_l4: vreg-pmr735b-l4 { + regulator-name = "pmr735b_l4"; + qcom,set = ; + regulator-min-microvolt = <120000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L5K: pmr735b_l5: vreg-pmr735b-l5 { + regulator-name = "pmr735b_l5"; + qcom,set = ; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <931000>; + qcom,init-voltage = <866000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L6K: pmr735b_l6: vreg-pmr735b-l6 { + regulator-name = "pmr735b_l6"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldok7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldok7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L7K: pmr735b_l7: vreg-pmr735b-l7 { + regulator-name = "pmr735b_l7"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1M: pm8010m_l1: vreg-pm8010m-l1 { + regulator-name = "pm8010m_l1"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2M: pm8010m_l2: vreg-pm8010m-l2 { + regulator-name = "pm8010m_l2"; + qcom,set = ; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldom3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom3"; + + L3M: pm8010m_l3: vreg-pm8010m-l3 { + regulator-name = "pm8010m_l3"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldom4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom4"; + + L4M: pm8010m_l4: vreg-pm8010m-l4 { + regulator-name = "pm8010m_l4"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldom5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom5"; + + L5M: pm8010m_l5: vreg-pm8010m-l5 { + regulator-name = "pm8010m_l5"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1504000>; + }; + }; + + rpmh-regulator-ldom6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom6"; + + L6M: pm8010m_l6: vreg-pm8010m-l6 { + regulator-name = "pm8010m_l6"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldom7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldom7"; + + L7M: pm8010m_l7: vreg-pm8010m-l7 { + regulator-name = "pm8010m_l7"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldon1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L1N: pm8010n_l1: vreg-pm8010n-l1 { + regulator-name = "pm8010n_l1"; + qcom,set = ; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1050000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldon2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + + L2N: pm8010n_l2: vreg-pm8010n-l2 { + regulator-name = "pm8010n_l2"; + qcom,set = ; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldon3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon3"; + + L3N: pm8010n_l3: vreg-pm8010n-l3 { + regulator-name = "pm8010n_l3"; + qcom,set = ; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1792000>; + }; + }; + + rpmh-regulator-ldon4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon4"; + + L4N: pm8010n_l4: vreg-pm8010n-l4 { + regulator-name = "pm8010n_l4"; + qcom,set = ; + regulator-min-microvolt = <1792000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1792000>; + }; + }; + + rpmh-regulator-ldon5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon5"; + + L5N: pm8010n_l5: vreg-pm8010n-l5 { + regulator-name = "pm8010n_l5"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1620000>; + }; + }; + + rpmh-regulator-ldon6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon6"; + + L6N: pm8010n_l6: vreg-pm8010n-l6 { + regulator-name = "pm8010n_l6"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2700000>; + }; + }; + + rpmh-regulator-ldon7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldon7"; + + L7N: pm8010n_l7: vreg-pm8010n-l7 { + regulator-name = "pm8010n_l7"; + qcom,set = ; + regulator-min-microvolt = <3130000>; + regulator-max-microvolt = <3470000>; + qcom,init-voltage = <3130000>; + }; + }; + +}; diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 4a1f5de8..d4f43acc 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -19,10 +19,6 @@ }; &soc { - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - usb_emuphy: phy@a784000 { compatible = "qcom,usb-emu-phy"; reg = <0x0a784000 0x9500>; diff --git a/qcom/kera-thermal.dtsi b/qcom/kera-thermal.dtsi new file mode 100644 index 00000000..f042a59c --- /dev/null +++ b/qcom/kera-thermal.dtsi @@ -0,0 +1,1370 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + tsens0: tsens0@c228000 { + compatible = "qcom,tsens-v2"; + reg = <0xc228000 0x1ff>, /* TM */ + <0xc222000 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens1@c229000 { + compatible = "qcom,tsens-v2"; + reg = <0xc229000 0x1ff>, /* TM */ + <0xc223000 0x1ff>; /* SROT */ + #qcom,sensors = <14>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2: tsens2@c22a000 { + compatible = "qcom,tsens-v2"; + reg = <0xc22a000 0x1ff>, /* TM */ + <0xc224000 0x1ff>; /* SROT */ + #qcom,sensors = <5>; + interrupts = , + ; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "thermal-pause-1"; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "thermal-pause-2"; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "thermal-pause-4"; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "thermal-pause-8"; + #cooling-cells = <2>; + }; + + cpu4_pause: cpu4-pause { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "thermal-pause-10"; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "thermal-pause-20"; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "thermal-pause-40"; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "thermal-pause-80"; + #cooling-cells = <2>; + }; + + APC0_MX_CX_PAUSE: apc0-mx-cx-pause { + qcom,cpus = <&CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cdev-alias = "thermal-pause-3C"; + #cooling-cells = <2>; + }; + + APC1_MX_CX_PAUSE: apc1-mx-cx-pause { + qcom,cpus = <&CPU6 &CPU7>; + qcom,cdev-alias = "thermal-pause-C0"; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu4 { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "pause-cpu4"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + qcom,cdev-alias = "cpu-hotplug0"; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + qcom,cdev-alias = "cpu-hotplug1"; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + qcom,cdev-alias = "cpu-hotplug2"; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + qcom,cdev-alias = "cpu-hotplug3"; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + qcom,cdev-alias = "cpu-hotplug4"; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + qcom,cdev-alias = "cpu-hotplug5"; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + qcom,cdev-alias = "cpu-hotplug6"; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + qcom,cdev-alias = "cpu-hotplug7"; + #cooling-cells = <2>; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + + cpu-cluster0 { + qcom,cpus = <&CPU0 &CPU1 &CPU2>; + }; + + cpu-cluster1 { + qcom,cpus = <&CPU3 &CPU4 &CPU5 &CPU6>; + }; + + cpu-cluster2 { + qcom,cpus = <&CPU7>; + }; + }; + + qmi_tmd: qmi-tmd-devices { + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <16>; + #cooling-cells = <2>; + }; + }; + + limits_stat: limits-stat { + compatible = "qcom,limits-stat"; + qcom,limits-stat-sensor-names = "aoss-0", "cpuss-0", "cpuss-1", + "cpu-1-0-0", "cpu-1-0-1", "cpu-1-1-0", + "cpu-1-1-1", "cpu-1-2-0", "cpu-1-2-1", + "cpu-1-3-0", "cpu-1-3-1", "cpu-2-0-0", "cpu-2-0-1", + "aoss-1", "cpu-0-0-0", "cpu-0-1-0", "cpu-0-2-0", + "nsphvx-0", "nsphvx-1", "nsphmx-0", "nsphmx-1", + "gpuss-0", "gpuss-1", "video", "ddr", "camera-0", + "camera-1", "aoss-2", "mdmss-0", "mdmss-1", + "mdmss-2", "mdmss-3"; + }; +}; + +#include "sun-thermal-modem.dtsi" + +&thermal_zones { + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + cpu-1-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_emerg0: cpu2-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu100_cdev { + trip = <&cpu2_emerg0>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-1-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_emerg1: cpu2-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu101_cdev { + trip = <&cpu2_emerg1>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + + cpu-1-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_emerg0: cpu3-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu110_cdev { + trip = <&cpu3_emerg0>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + cpu-1-1-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_emerg1: cpu3-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu111_cdev { + trip = <&cpu3_emerg1>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + cpu-1-2-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu4_emerg0: cpu4-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu120_cdev { + trip = <&cpu4_emerg0>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-1-2-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu4_emerg1: cpu4-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu121_cdev { + trip = <&cpu4_emerg1>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-1-3-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu5_emerg0: cpu5-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point4 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu130_cdev { + trip = <&cpu5_emerg0>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-1-3-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu5_emerg1: cpu5-emerg1-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu131_cdev { + trip = <&cpu5_emerg1>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-2-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_emerg0: cpu7-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu200_cdev { + trip = <&cpu7_emerg0>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + cpu-2-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_emerg1: cpu7-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu201_cdev { + trip = <&cpu7_emerg1>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + cpu-0-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_emerg0: cpu0-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu000_cdev { + trip = <&cpu0_emerg0>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_emerg0: cpu1-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu010_cdev { + trip = <&cpu1_emerg0>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu6_emerg0: cpu6-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + cpu140_cdev { + trip = <&cpu6_emerg0>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + nsphvx-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + nsphvx-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + nsphmx-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + nsphmx-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + + gpuss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + gpuss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point2 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + }; + }; + + ddr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + aoss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + camera-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + camera-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + aoss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + mdmss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_scg_dsc 100 100>; + }; + + nr_cdev0 { + trip = <&mdmss0_config0>; + cooling-device = <&modem_nr_dsc 10 10>; + }; + + lte_cdev2 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss0_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_scg_dsc 100 100>; + }; + + nr_cdev0 { + trip = <&mdmss1_config0>; + cooling-device = <&modem_nr_dsc 10 10>; + }; + + lte_cdev2 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss1_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_scg_dsc 100 100>; + }; + + nr_cdev0 { + trip = <&mdmss2_config0>; + cooling-device = <&modem_nr_dsc 10 10>; + }; + + lte_cdev2 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss2_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; + + mdmss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + trip-point1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + + cooling-maps { + lte_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + nr_scg_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_scg_dsc 100 100>; + }; + + nr_cdev0 { + trip = <&mdmss3_config0>; + cooling-device = <&modem_nr_dsc 10 10>; + }; + + lte_cdev2 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev2 { + trip = <&mdmss3_config1>; + cooling-device = <&modem_nr_dsc 255 255>; + }; + }; + }; +}; diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index d6d689be..60032b6f 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -3,14 +3,19 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; - reg = <0xa600000 0x100000>; - reg-names = "core_base"; + reg = <0xa600000 0x100000>, + <0x1fc6000 0x4>; + reg-names = "core_base", + "tcsr_dyn_en_dis"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -25,23 +30,50 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,dis-sending-cm-l1-quirk; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-disconnected = <133333333>; - dwc3@a600000 { + qcom,use-pdc-interrupts; + qcom,use-eusb2-phy; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + + dummy-supply = <&apps_smmu>; + + + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd93c>; + reg = <0x0 0xa600000 0x0 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; + usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -51,10 +83,261 @@ snps,dis_u2_susphy_quirk; snps,ssp-u3-u0-quirk; tx-fifo-resize; - dr_mode = "otg"; - maximum-speed = "high-speed"; + dr_mode = "peripheral"; + maximum-speed = "super-speed-plus"; usb-role-switch; }; }; -}; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-snps-eusb2-phy"; + reg = <0x88e3000 0x154>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&L7K>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&L4B>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7K>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4B>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* based on tsmcn3e_USB3_Gen2_Seq v1.6 */ + + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100b 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xb>; + qcom,usb-audio-intr-num = <2>; + }; + +}; diff --git a/qcom/kera-vm-atp.dts b/qcom/kera-vm-atp.dts new file mode 100644 index 00000000..fe18d1e8 --- /dev/null +++ b/qcom/kera-vm-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + + qcom,board-id = <33 0>; +}; diff --git a/qcom/kera-vm-atp.dtsi b/qcom/kera-vm-atp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-vm-atp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-vm-cdp.dts b/qcom/kera-vm-cdp.dts new file mode 100644 index 00000000..2505df90 --- /dev/null +++ b/qcom/kera-vm-cdp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/qcom/kera-vm-cdp.dtsi b/qcom/kera-vm-cdp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-vm-cdp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-vm-dma-heaps.dtsi b/qcom/kera-vm-dma-heaps.dtsi new file mode 100644 index 00000000..b5cc90c3 --- /dev/null +++ b/qcom/kera-vm-dma-heaps.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + depends-on-supply = <&qcom_scm>; + + qcom,tui { + qcom,dma-heap-name = "qcom,tui"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,tui_demura { + qcom,dma-heap-name = "qcom,tui_demura"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms1 { + qcom,dma-heap-name = "qcom,ms1"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms2 { + qcom,dma-heap-name = "qcom,ms2"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms3 { + qcom,dma-heap-name = "qcom,ms3"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms4 { + qcom,dma-heap-name = "qcom,ms4"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms5 { + qcom,dma-heap-name = "qcom,ms5"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms6 { + qcom,dma-heap-name = "qcom,ms6"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms7 { + qcom,dma-heap-name = "qcom,ms7"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,tui_test { + qcom,dma-heap-name = "qcom,tui_test"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + }; +}; diff --git a/qcom/kera-vm-mtp.dts b/qcom/kera-vm-mtp.dts new file mode 100644 index 00000000..3a17f7fd --- /dev/null +++ b/qcom/kera-vm-mtp.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, <0x30008 1>; +}; diff --git a/qcom/kera-vm-mtp.dtsi b/qcom/kera-vm-mtp.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-vm-mtp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-vm-qrd.dts b/qcom/kera-vm-qrd.dts new file mode 100644 index 00000000..2ec17d3a --- /dev/null +++ b/qcom/kera-vm-qrd.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/qcom/kera-vm-qrd.dtsi b/qcom/kera-vm-qrd.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-vm-qrd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-vm-rcm.dts b/qcom/kera-vm-rcm.dts new file mode 100644 index 00000000..44db195e --- /dev/null +++ b/qcom/kera-vm-rcm.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, <0x30015 1>; +}; diff --git a/qcom/kera-vm-rcm.dtsi b/qcom/kera-vm-rcm.dtsi new file mode 100644 index 00000000..1510613d --- /dev/null +++ b/qcom/kera-vm-rcm.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { +}; diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi index 5ae595f2..452ce2e8 100644 --- a/qcom/kera-vm.dtsi +++ b/qcom/kera-vm.dtsi @@ -5,15 +5,16 @@ #include #include +#include / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <659 0x10000>; + qcom,msm-id = <659 0x10000>, <686 0x10000>; interrupt-parent = <&vgic>; chosen { - bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce memhp_default_state=online_movable memory_hotplug.memmap_on_memory=force rcupdate.rcu_expedited=1 rcu_nocbs=0-1"; }; cpus { @@ -52,6 +53,29 @@ }; }; + dmesg-dump { + compatible = "qcom,dmesg-dump"; + gunyah-label = <7>; + ddump-pubkey-size = <270>; + ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2 + 0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96 + 0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc + 0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7 + 0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e + 0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d + 0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b + 0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0 + 0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27 + 0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31 + 0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79 + 0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd + 0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0 + 0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf + 0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac + 0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50 + 0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>; + }; + qcom,vm-config { compatible = "qcom,vm-1.0"; vm-type = "aarch64-guest"; @@ -71,6 +95,10 @@ vm-attrs = "context-dump", "crash-restart"; + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0 + 0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>; + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. * QUP1_SE4: GPII5 : IRQ_316 * QUP2_SE7: GPII5 : IRQ_625 @@ -187,6 +215,100 @@ allocate-base; }; + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x3>; + allocate-base; + }; + }; + + msgqsock-msgq { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/msgqsock-msgq-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + peer = "vm-name:qcom,oemvm"; + qcom,label = <0x3>; + }; + + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + + ddump-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/ddump-shm"; + push-compatible = "qcom,ddump-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x7>; + allocate-base; + }; + }; + + gunyah-panic-notifier-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/gpn-shm"; + push-compatible = "qcom,gunyah-panic-gen"; + peer-default; + memory { + qcom,label = <0x9>; + allocate-base; + }; + }; + + gpiomem0 { + vdevice-type = "iomem"; + patch = "/soc/tlmm-vm-mem-access"; + push-compatible = "qcom,tlmm-vm-mem-access"; + peer-default; + memory { + qcom,label = <0x8>; + qcom,mem-info-tag = <0x3>; + allocate-base; + }; + }; + test-dbl-tuivm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-tuivm"; + qcom,label = <0x4>; + peer-default; + }; + + test-dbl-tuivm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-tuivm-source"; + qcom,label = <0x4>; + peer-default; + }; + + test-msgq-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x4>; + peer-default; + }; + + test-large-dmabuf-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xd>; + peer-default; + }; + }; }; @@ -216,11 +338,83 @@ wakeup-source; }; + vm_tlmm_irq: vm-tlmm-irq@0 { + compatible = "qcom,tlmm-vm-irq"; + reg = <0x0 0x0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,kera-vm-tlmm"; + reg = <0x0F000000 0x1000000>; + interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* Valid pins */ + gpios = /bits/ 16 <17 121 12 127 0 1 2 3 16 13 28 29 30 31>; + }; + + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0 + &tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>; + }; + + tlmm-vm-test { + compatible = "qcom,tlmm-vm-test"; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&qupv3_se1_7i2c_active>; + pinctrl-1 = <&qupv3_se1_7i2c_sleep>; + tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0 + &tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>; + }; + + pinctrl@f000000 { + qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins { + qupv3_se1_7i2c_active: qupv3_se1_7i2c_active { + mux { + pins = "gpio28"; + function = "qup1_se0_l0"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep { + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + drive-strength = <2>; + }; + }; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; }; + ipcc_mproc_ns1: qcom,ipcc@407000 { + compatible = "qcom,ipcc"; + reg = <0x407000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + vgic: interrupt-controller@17100000 { compatible = "arm,gic-v3"; interrupt-controller; @@ -245,11 +439,275 @@ compatible = "qcom,smcinvoke"; }; + qcom_mem_object { + compatible = "qcom,mem-object"; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <64>; qcom,support-hypervisor; }; + + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + gunyah-label = <9>; + }; + + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ + qcom,vmid = <45>; + }; + + mem_buf_msgq: qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; + }; + + qmsgq-gunyah { + compatible = "qcom,qmsgq-gh"; + msgq-label = <3>; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <3>; + }; + + virtio_mem_device { + compatible = "qcom,virtio-mem"; + depends-on-supply = <&mem_buf_msgq>; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x18000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + qcom,initial-movable-zone-size = <0x2000000>; + + }; + + /* + * QUP1 : SE0 - Secondary touch + * QUP2 : SE0 - Primary touch + */ + qup_iommu_group: qup_common_iommu_group { + iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>, + <&qupv3_1 0x00000000 0x00020000>, + <&gpi_dma2 0x00000000 0x00020000>, + <&qupv3_2 0x00000000 0x00020000>; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Secondary Tounch */ + qupv3_se0_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 0 3 64 0xc>, + <&gpi_dma1 1 0 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Secondary Touch */ + qupv3_se0_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + reg = <0xa80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 0 1 64 0xc>, + <&gpi_dma1 1 0 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + /* GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + #dma-cells = <5>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Touchscreen I2C Instance */ + qupv3_se8_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma2 0 0 3 64 0xc>, + <&gpi_dma2 1 0 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se8_spi: spi@880000 { + compatible = "qcom,spi-geni"; + reg = <0x880000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma2 0 0 1 64 0xc>, + <&gpi_dma2 1 0 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + qti,smmu-proxy { + compatible = "smmu-proxy-receiver"; + }; + + qti,smmu-proxy-camera-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + iommus = <&apps_smmu 0x1810 0x20>, + <&apps_smmu 0x1C10 0x0>, + <&apps_smmu 0x18F0 0x0>; + dma-coherent; + }; + + qti,smmu-proxy-display-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + iommus = <&apps_smmu 0x801 0x0>; + dma-coherent; + }; + + qti,smmu-proxy-eva-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00000000 0xffffffff>; + iommus = <&apps_smmu 0x1927 0x0>; + dma-coherent; + }; }; #include "msm-arm-smmu-kera-vm.dtsi" +#include "kera-vm-dma-heaps.dtsi" diff --git a/qcom/kera-walt.dtsi b/qcom/kera-walt.dtsi new file mode 100644 index 00000000..627030bc --- /dev/null +++ b/qcom/kera-walt.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&soc { + walt { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cycle-cntr@17d91000 { + compatible = "qcom,epss"; + reg = <0x17D91000 0x1000>, + <0x17D92000 0x1000>, + <0x17D93000 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + }; + }; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 89a39d8a..6e78dc8a 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -34,9 +34,43 @@ reg = <0 0 0 0>; }; + aliases: aliases { + serial0 = &qupv3_se13_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + hsuart0 = &qupv3_se5_4uart; + i2c0 = &qupv3_se0_i2c; + i2c1 = &qupv3_se1_i2c; + i2c2 = &qupv3_se2_i2c; + i2c3 = &qupv3_se3_i2c; + i2c4 = &qupv3_se4_i2c; + i2c6 = &qupv3_se6_i2c; + i2c7 = &qupv3_se7_i2c; + i2c8 = &qupv3_se8_i2c; + i2c9 = &qupv3_se9_i2c; + i2c10 = &qupv3_se10_i2c; + i2c11 = &qupv3_se11_i2c; + i2c12 = &qupv3_se12_i2c; + i2c14 = &qupv3_se14_i2c; + i2c15 = &qupv3_se15_i2c; + spi0 = &qupv3_se0_spi; + spi1 = &qupv3_se1_spi; + spi2 = &qupv3_se2_spi; + spi3 = &qupv3_se3_spi; + spi6 = &qupv3_se6_spi; + spi7 = &qupv3_se7_spi; + spi8 = &qupv3_se8_spi; + spi9 = &qupv3_se9_spi; + spi10 = &qupv3_se10_spi; + spi11 = &qupv3_se11_spi; + spi12 = &qupv3_se12_spi; + spi14 = &qupv3_se14_spi; + spi15 = &qupv3_se15_spi; + }; + chosen: chosen { bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; - stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8"; + stdout-path = "serial0:115200n8"; }; reserved_memory: reserved-memory {}; @@ -54,11 +88,6 @@ qcom_scm: qcom_scm { }; }; - aliases { - serial0 = &qupv3_se13_2uart; - ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -72,6 +101,9 @@ power-domains = <&CPU_PD0>; power-domain-names = "psci"; next-level-cache = <&L2_0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <1024>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -93,6 +125,9 @@ power-domains = <&CPU_PD1>; power-domain-names = "psci"; next-level-cache = <&L2_0>; + dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; }; CPU2: cpu@200 { @@ -104,6 +139,9 @@ power-domains = <&CPU_PD2>; power-domain-names = "psci"; next-level-cache = <&L2_2>; + #cooling-cells = <2>; + dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <1024>; L2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -120,6 +158,9 @@ power-domains = <&CPU_PD3>; power-domain-names = "psci"; next-level-cache = <&L2_3>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + capacity-dmips-mhz = <1566>; L2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -136,6 +177,9 @@ power-domains = <&CPU_PD4>; power-domain-names = "psci"; next-level-cache = <&L2_4>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + capacity-dmips-mhz = <1566>; L2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -152,6 +196,9 @@ power-domains = <&CPU_PD5>; power-domain-names = "psci"; next-level-cache = <&L2_5>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + capacity-dmips-mhz = <1566>; L2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -168,6 +215,9 @@ power-domains = <&CPU_PD6>; power-domain-names = "psci"; next-level-cache = <&L2_6>; + #cooling-cells = <2>; + dynamic-power-coefficient = <263>; + capacity-dmips-mhz = <1566>; L2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -184,6 +234,9 @@ power-domains = <&CPU_PD7>; power-domain-names = "psci"; next-level-cache = <&L2_7>; + #cooling-cells = <2>; + dynamic-power-coefficient = <289>; + capacity-dmips-mhz = <1607>; L2_7: l2-cache { compatible = "cache"; cache-level = <2>; @@ -339,11 +392,20 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qcom_mem_object { + compatible = "qcom,mem-object"; + }; }; #include "kera-reserved-memory.dtsi" #include "msm-arm-smmu-kera.dtsi" #include "kera-dma-heaps.dtsi" +#include "kera-vm-dma-heaps.dtsi" &reserved_memory { #address-cells = <2>; @@ -447,6 +509,13 @@ interrupts = ; }; + qcom,hdcp { + compatible = "qcom,hdcp"; + qcom,use-smcinvoke = <1>; + }; + + msm_gpu: qcom,kgsl-3d0@3d00000 { }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , @@ -528,6 +597,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm", "oem_vm"; }; apps_rsc: rsc@17a00000 { @@ -558,6 +628,13 @@ apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; + + dcvs_fp: qcom,dcvs-fp { + compatible = "qcom,dcvs-fp"; + qcom,ddr-bcm-name = "MC4"; + qcom,llcc-bcm-name = "SH5"; + + }; }; }; @@ -844,6 +921,116 @@ }; }; + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-ctrl-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp"; + }; + + qcom,glinkpkt-data-cdsp { + qcom,glinkpkt-edge = "cdsp"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP"; + qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp"; + }; + + qcom,glinkpkt-ctrl-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_lpass"; + }; + + qcom,glinkpkt-data-lpass { + qcom,glinkpkt-edge = "lpass"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_LPASS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_lpass"; + }; + + qcom,glinkpkt-ctrl-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_CTL_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_ctrl_mpss"; + }; + + qcom,glinkpkt-data-mpss { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "LOOPBACK_DATA_MPSS"; + qcom,glinkpkt-dev-name = "glink_pkt_data_mpss"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-qmc-dma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_dma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-qmc-cma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_cma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-ims-sub-1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "Ims_dc_sub1"; + qcom,glinkpkt-dev-name = "ims_dc_sub1"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-ims-sub-2 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "Ims_dc_sub2"; + qcom,glinkpkt-dev-name = "ims_dc_sub2"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-xpan_control { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "bt_cp_ctrl"; + qcom,glinkpkt-dev-name = "bt_cp_ctrl"; + }; + }; + sys-pm-vx@c320000 { compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kera"; reg = <0xc320000 0x400>; @@ -864,7 +1051,112 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qcom,gpios-reserved = <20 21 22 23 100 111 112 116>; + qcom,gpios-reserved = <20 21 22 23 111 112 118>; + }; + + qcom_tzlog: tz-log@14680720 { + compatible = "qcom,tz-log"; + reg = <0x14680720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + tmecrashdump-address-offset = <0x81CA0000>; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x28000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,offload-ops-support; + qcom,bam-pipe-offload-cpb-hlos = <1>; + qcom,bam-pipe-offload-hlos-cpb = <3>; + qcom,bam-pipe-offload-hlos-cpb-1 = <8>; + qcom,bam-pipe-offload-hlos-hlos = <4>; + qcom,bam-pipe-offload-hlos-hlos-1 = <9>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + qcom,no-clk-gating; + interconnect-names = "data_path"; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + iommus = <&apps_smmu 0x0480 0x0>, + <&apps_smmu 0x0481 0x0>; + qcom,iommu-dma = "atomic"; + dma-coherent; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x0481 0x0>; + dma-coherent; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x0483 0x0>; + qcom,iommu-vmid = <0x9>; + qcom,secure-context-bank; + dma-noncoherent; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,trng"; + reg = <0x10c3000 0x1000>; + }; + + slimbam: bamdma@6c04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>; + reg-names = "bam", "bam_remote_mem"; + interrupts = ; + num-channels = <31>; + #dma-cells = <1>; + qcom,controlled-remotely; + qcom,ee = <1>; + qcom,num-ees = <2>; + }; + + slim_msm: slim@6c40000 { + compatible = "qcom,slim-ngd-v1.5.0"; + reg = <0x6c40000 0x2c000>, <0x6c8E000 0x1000>; + reg-names = "ctrl", "slimbus_remote_mem"; + interrupts = ; + dmas = <&slimbam 3>, <&slimbam 4>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + qcom,master; + tuivm { + qcom,label = <0x08>; + qcom,vmid = <45>; + tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0 + &tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>; + }; + }; + + tlmm-vm-test { + compatible = "qcom,tlmm-vm-test"; + qcom,master; + tlmm-vm-gpio-list = <&tlmm 17 0 &tlmm 121 0 &tlmm 12 0 &tlmm 127 0 &tlmm 0 0 &tlmm 1 0 + &tlmm 2 0 &tlmm 3 0 &tlmm 16 0 &tlmm 13 0 &tlmm 28 0 &tlmm 29 0 &tlmm 30 0 &tlmm 31 0>; }; tcsr_mutex_block: syscon@1f40000 { @@ -946,6 +1238,14 @@ reg = <0x1fc0000 0x30000>; }; + qcom,tmecom-qmp-client { + compatible = "qcom,tmecom-qmp-client"; + mboxes = <&qmp_tme 0>; + mbox-names = "tmecom"; + label = "tmecom"; + depends-on-supply = <&qmp_tme>; + }; + qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -1289,6 +1589,43 @@ /* Outputs to wpss */ qcom,smem-states = <&wpss_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + }; + }; + + qcom,qrtr-gunyah-oemvm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <8>; + peer-name = <4>; + }; + + qcom,qrtr-gunyah-tuivm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; }; clocks { @@ -1494,6 +1831,10 @@ #reset-cells = <1>; }; + qti,smmu-proxy { + compatible = "smmu-proxy-sender"; + }; + clk_virt: interconnect@0 { compatible = "qcom,kera-clk_virt"; #interconnect-cells = <1>; @@ -1724,6 +2065,67 @@ ext-label = <0x7>; }; + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + qcom,primary; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + qcom,primary; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + qcom,primary; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + qcom,primary; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,primary; + }; + + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + qcom,primary-vm; + gunyah-label = <9>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + + dmesg-dump { + compatible = "qcom,dmesg-dump"; + qcom,primary-vm; + gunyah-label = <7>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + mmio_sram: mmio-sram@17D09400 { #address-cells = <2>; #size-cells = <2>; @@ -1965,6 +2367,90 @@ }; }; + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x400000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2_dma_resv: sdhc_2_dma_resv_region { + /* + * Restrict IOVA mappings for SDHC2 buffers to the 256 MB region + * from 0x40000000 - 0x4fffffff. + */ + iommu-addresses = <&sdhc_2 0x0 0x40000000>, + <&sdhc_2 0x50000000 0xb0000000>; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* + * DLL HSR settings. Refer go/hsr - DLL settings. + * Note that the DLL_CONFIG_2 value is not passed from the + * device tree, but it is calculated in the driver. + */ + qcom,dll-hsr-list = <0x0007442C 0x0 0x10 + 0x090106C0 0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + memory-region = <&sdhc_2_dma_resv>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + + qos0 { + mask = <0xf8>; + vote = <44>; + }; + + qos1 { + mask = <0x07>; + vote = <44>; + }; + }; + ufsphy_mem: ufsphy_mem@1d80000 { reg = <0x1d80000 0x2000>; reg-names = "phy_mem"; @@ -1988,15 +2474,46 @@ status = "disabled"; }; + ice_cfg: shared_ice { + alg1 { + alg-name = "alg1"; + rx-alloc-percent = <60>; + status = "disabled"; + }; + + alg2 { + alg-name = "alg2"; + status = "disabled"; + + }; + + alg3 { + alg-name = "alg3"; + num-core = <28 28 15 13>; + status = "ok"; + }; + }; + + ufshc_dma_resv: ufshc_dma_resv_region { + /* + * Restrict IOVA mappings for UFSHC buffers to the 3 GB region + * from 0x1000 - 0xffffffff. + */ + iommu-addresses = <&ufshc_mem 0x0 0x1000>; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; - reg = <0x1d84000 0x3000>; - reg-names = "ufs_mem"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x18000>; + reg-names = "ufs_mem", "ice"; interrupts = ; phys = <&ufsphy_mem>; phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice-use-hwkm; + lanes-per-direction = <2>; clock-names = "core_clk", @@ -2038,16 +2555,474 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "bypass"; + memory-region = <&ufshc_dma_resv>; + shared-ice-cfg = <&ice_cfg>; dma-coherent; qcom,bypass-pbl-rst-wa; qcom,max-cpus = <8>; - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; status = "disabled"; + + qos0 { + mask = <0xf8>; + vote = <44>; + perf; + cpu_freq_vote = <3 7>; + }; + + qos1 { + mask = <0x07>; + vote = <44>; + cpu_freq_vote = <0>; + }; + }; + + llcc_pmu: llcc-pmu@24095000 { + compatible = "qcom,llcc-pmu-ver2"; + reg = <0x24095000 0x300>; + reg-names = "lagg-base"; + }; + + qcom_pmu: qcom,pmu { + compatible = "qcom,pmu"; + qcom,long-counter; + qcom,pmu-events-tbl = + < 0x0008 0xFF 0x02 0xFF >, + < 0x0011 0xFF 0x01 0xFF >, + < 0x0017 0xFF 0xFF 0xFF >, + < 0x0037 0xFF 0xFF 0xFF >, + < 0x1000 0xFF 0xFF 0xFF >; + }; + + ddr_freq_table: ddr-freq-table { + ddr4 { + qcom,ddr-type = <7>; + qcom,freq-tbl = + < 547200 >, + < 681600 >, + < 768000 >, + < 1017600 >, + < 1353600 >, + < 1555200 >, + < 1708800 >, + < 2092800 >; + }; + + ddr5 { + qcom,ddr-type = <8>; + qcom,freq-tbl = + < 547200 >, + < 1353600 >, + < 1555200 >, + < 1708800 >, + < 2092800 >, + < 2736000 >, + < 3187200 >, + < 3686400 >, + < 4224000 >; + }; + }; + + llcc_freq_table: llcc-freq-table { + qcom,freq-tbl = + < 19200 >, + < 350000 >, + < 533000 >, + < 695000 >, + < 875000 >, + < 933000 >, + < 1066000 >; + }; + + ddrqos_freq_table: ddrqos-freq-table { + qcom,freq-tbl = + < 0 >, + < 1 >; + }; + + qcom_dcvs: qcom,dcvs { + compatible = "qcom,dcvs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom_l3_dcvs_hw: l3 { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <2>; + qcom,bus-width = <32>; + reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>; + reg-names = "l3-base", "l3tbl-base"; + + l3_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + qcom,shared-offset = <0x0090>; + }; + }; + + qcom_ddr_dcvs_hw: ddr { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <0>; + qcom,bus-width = <4>; + qcom,freq-tbl = <&ddr_freq_table>; + + ddr_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>; + }; + + ddr_dcvs_fp: fp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <1>; + qcom,fp-voter = <&dcvs_fp>; + }; + }; + + qcom_llcc_dcvs_hw: llcc { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <1>; + qcom,bus-width = <16>; + qcom,freq-tbl = <&llcc_freq_table>; + + llcc_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&gem_noc MASTER_APPSS_PROC + &gem_noc SLAVE_LLCC>; + }; + + llcc_dcvs_fp: fp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <1>; + qcom,fp-voter = <&dcvs_fp>; + }; + }; + + qcom_ddrqos_dcvs_hw: ddrqos { + compatible = "qcom,dcvs-hw"; + qcom,dcvs-hw-type = <3>; + qcom,bus-width = <1>; + qcom,freq-tbl = <&ddrqos_freq_table>; + + ddrqos_dcvs_sp: sp { + compatible = "qcom,dcvs-path"; + qcom,dcvs-path-type = <0>; + interconnects = <&mc_virt MASTER_LLCC + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + qcom_memlat: qcom,memlat { + compatible = "qcom,memlat"; + + ddr { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; + qcom,sampling-path = <&ddr_dcvs_fp>; + qcom,miss-ev = <0x1000>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1843200 1017000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 1113600 547000 >, + < 1497600 768000 >, + < 1843200 1555000 >; + }; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 940800 547000 >, + < 1190400 1017000 >, + < 2208000 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 940800 547000 >, + < 1190400 768000 >, + < 1612800 1555000 >, + < 1824000 1708000 >, + < 2208000 2092000 >, + < 2400000 3196000 >; + }; + }; + + prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1209600 1017000 >, + < 1459200 1555000 >, + < 1804800 1708000 >, + < 2304000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 960000 547000 >, + < 1209600 768000 >, + < 1459200 1555000 >, + < 1651200 1708000 >, + < 1804800 2092000 >, + < 2304000 3196000 >; + }; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 940800 547000 >, + < 1190400 768000 >, + < 1612800 1017000 >, + < 2208000 1708000 >, + < 2400000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 940800 547000 >, + < 1190400 768000 >, + < 1612800 1555000 >, + < 2208000 2092000 >, + < 2400000 3196000 >; + }; + }; + + prime-latfloor { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + ddr4-tbl { + qcom,ddr-type = <7>; + qcom,cpufreq-memfreq-tbl = + < 2284800 547000 >, + < 2592000 2092000 >; + }; + + ddr5-tbl { + qcom,ddr-type = <8>; + qcom,cpufreq-memfreq-tbl = + < 2284800 547000 >, + < 2592000 3196000 >; + }; + }; + }; + + llcc { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + qcom,sampling-path = <&llcc_dcvs_fp>; + qcom,miss-ev = <0x37>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 883200 350000 >, + < 1401600 533000 >, + < 2016000 600000 >; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 633600 350000 >, + < 1190400 533000 >, + < 1401600 600000 >, + < 1824000 806000 >, + < 2803200 933000 >, + < 2918400 1066000 >, + < 3014400 1211000 >; + }; + + gold-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + qcom,cpufreq-memfreq-tbl = + < 2073600 350000 >, + < 3014400 600000 >; + }; + }; + + l3 { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,sampling-path = <&l3_dcvs_sp>; + qcom,miss-ev = <0x17>; + + silver { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 441600 364800 >, + < 595200 556800 >, + < 787200 710400 >, + < 902400 806400 >, + < 1113600 998400 >, + < 1228800 1094400 >, + < 1344000 1209600 >, + < 1497600 1363200 >, + < 1708800 1497600 >, + < 1804800 1516800 >, + < 2054400 1804800 >; + }; + + gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 480000 364800 >, + < 940800 556800 >, + < 1190400 710400 >, + < 1286400 902400 >, + < 1497600 1209600 >, + < 1708800 1363200 >, + < 2073600 1497600 >, + < 2400000 1516800 >, + < 2707200 1804800 >; + }; + + prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 480000 364800 >, + < 633600 556800 >, + < 960000 806400 >, + < 1324800 998400 >, + < 1651200 1209600 >, + < 1766400 1363200 >, + < 2208000 1497600 >, + < 2496000 1516800 >, + < 2918400 1804800 >; + }; + + prime-compute { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + qcom,compute-mon; + qcom,cpufreq-memfreq-tbl = + < 1920000 364800 >, + < 2512200 1209600 >, + < 3206400 1804800 >; + }; + }; + + ddrqos { + compatible = "qcom,memlat-grp"; + qcom,target-dev = <&qcom_ddrqos_dcvs_hw>; + qcom,sampling-path = <&ddrqos_dcvs_sp>; + qcom,miss-ev = <0x1000>; + + ddrqos_gold_lat: gold { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 2300000 0 >, + < 2496000 1 >; + }; + + ddrqos_prime_lat: prime { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 1478400 0 >, + < 3206400 1 >; + }; + + ddrqos_prime_latfloor: prime-latfloor { + compatible = "qcom,memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,sampling-enabled; + qcom,cpufreq-memfreq-tbl = + < 2169600 0 >, + < 3206400 1 >; + }; + }; + }; + + qcom_llcc_l3_vote: qcom,llcc-l3-vote { + qcom,target-dev = <&qcom_l3_dcvs_hw>; + qcom,secondary-map = + < 350000 364800 >, + < 533000 518400 >, + < 600000 614400 >, + < 806000 806400 >, + < 933000 902400 >, + < 1066000 998400 >, + < 1211200 1209600 >; + }; + + bwmon_llcc: qcom,bwmon-llcc@240B7300 { + compatible = "qcom,bwmon4"; + reg = <0x240B7400 0x300>, <0x240B7300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_llcc_dcvs_hw>; + qcom,second-vote = <&qcom_llcc_l3_vote>; + }; + + bwmon_ddr: qcom,bwmon-ddr@24091000 { + compatible = "qcom,bwmon5"; + reg = <0x24091000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,count-unit = <0x10000>; + qcom,target-dev = <&qcom_ddr_dcvs_hw>; }; }; @@ -2170,20 +3145,6 @@ reg = <0x0 0x81c60000 0x0 0x20000>; }; - trust_ui_vm_mem: trust_ui_vm_region@f3800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf3800000 0x0 0x4400000>; - reusable; - alignment = <0x0 0x400000>; - }; - - oem_vm_mem: oem_vm_region@f7c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf7c00000 0x0 0x4c00000>; - reusable; - alignment = <0x0 0x400000>; - }; - vm_comm_mem: vm_comm_mem_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -2207,15 +3168,52 @@ alignment = <0x0 0x400000>; size = <0x0 0x4800000>; }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + size = <0x0 0xc800000>; + alignment = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; }; #include "kera-debug.dtsi" #include "kera-coresight.dtsi" #include "kera-pinctrl.dtsi" -#include "kera-stub-regulators.dtsi" +#include "kera-regulators.dtsi" +#include "kera-pmic-overlay.dtsi" #include "kera-usb.dtsi" #include "kera-qupv3.dtsi" +#include "kera-thermal.dtsi" +#include "kera-walt.dtsi" +#include "msm-rdbg.dtsi" &qupv3_se13_2uart { status = "ok"; }; + +&qupv3_se3_i2c { + status = "disabled"; + wcd_usbss: wcd939x_i2c@e { + compatible = "qcom,wcd939x-i2c"; + reg = <0xe>; + vdd-usb-cp-supply = <&L7B>; + }; +}; diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi new file mode 100644 index 00000000..1ed18475 --- /dev/null +++ b/qcom/kera_ufs2.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-niobe"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L6B>; + vdda-phy-max-microamp = <211860>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18330>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <1890>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L1D>; + vccq2-max-microamp = <750000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L3G>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq2-parent-supply = <&S1B>; + qcom,vccq2-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/kera_ufs3.dtsi b/qcom/kera_ufs3.dtsi new file mode 100644 index 00000000..537e2d6a --- /dev/null +++ b/qcom/kera_ufs3.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-niobe"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L6B>; + vdda-phy-max-microamp = <211860>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18330>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <1890>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L1D>; + vccq-max-microamp = <750000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L3G>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/kera_ufs4.dtsi b/qcom/kera_ufs4.dtsi new file mode 100644 index 00000000..025e5072 --- /dev/null +++ b/qcom/kera_ufs4.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-niobe"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L6B>; + vdda-phy-max-microamp = <211860>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18330>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <1890>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <1200000>; + + vccq-supply = <&L1D>; + vccq-max-microamp = <1200000>; + + /* VDD_PX10 is voted for the ufs_reset_n */ + qcom,vddp-ref-clk-supply = <&L3G>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; diff --git a/qcom/kerap.dts b/qcom/kerap.dts new file mode 100644 index 00000000..07c84dca --- /dev/null +++ b/qcom/kerap.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kerap.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KeraP SoC"; + compatible = "qcom,kerap"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/kerap.dtsi b/qcom/kerap.dtsi new file mode 100644 index 00000000..26a4c0b9 --- /dev/null +++ b/qcom/kerap.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KeraP SoC"; + compatible = "qcom,kerap"; + qcom,msm-id = <686 0x10000>; +}; diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index c7cc696b..f1eea377 100644 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -101,6 +101,7 @@ pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>, <&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>; qcom,wakeup-byte = <0xFD>; + qcom,suspend-ignore-children; status = "disabled"; }; diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index e5f15ae1..c0f541fa 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -29,7 +29,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@98c000:115200n8"; - bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on cgroup_disable=pressure"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never page_poison=on can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on cgroup_disable=pressure fw_devlink.strict=1"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 95d31391..57b2524b 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -77,6 +77,10 @@ _platform_map = { "dtb_list": [ {"name": "tuna.dtb"}, {"name": "tuna7.dtb"}, + { + "name": "tunap.dtb", + "apq": True, + }, ], "dtbo_list": [ { @@ -87,6 +91,7 @@ _platform_map = { {"name": "tuna-cdp-overlay.dtbo"}, {"name": "tuna-mtp-kiwi-harmonium-overlay.dtbo"}, {"name": "tuna-mtp-kiwi-overlay.dtbo"}, + {"name": "tuna-mtp-kiwi-pmd802x-overlay.dtbo"}, {"name": "tuna-mtp-nfc-overlay.dtbo"}, {"name": "tuna-mtp-overlay.dtbo"}, {"name": "tuna-mtp-qmp1000-overlay.dtbo"}, @@ -98,12 +103,35 @@ _platform_map = { "kera": { "dtb_list": [ {"name": "kera.dtb"}, + { + "name": "kerap.dtb", + "apq": True, + }, ], "dtbo_list": [ { "name": "kera-rumi-overlay.dtbo", "apq": False, }, + {"name": "kera-atp-overlay.dtbo"}, + {"name": "kera-mtp-qca6750-ufs4-overlay.dtbo"}, + {"name": "kera-mtp-qca6750-ufs3-overlay.dtbo"}, + {"name": "kera-mtp-qca6750-qmp1000-overlay.dtbo"}, + {"name": "kera-mtp-wcn7750-qmp1000-overlay.dtbo"}, + {"name": "kera-mtp-wcn7750-ufs3-overlay.dtbo"}, + {"name": "kera-mtp-wcn7750-ufs4-overlay.dtbo"}, + {"name": "kera-cdp-qca6750-ufs2-overlay.dtbo"}, + {"name": "kera-cdp-qca6750-ufs3-overlay.dtbo"}, + {"name": "kera-cdp-qca6750-ufs4-overlay.dtbo"}, + {"name": "kera-qrd-wcn7750-ufs4-overlay.dtbo"}, + {"name": "kera-qrd-wcn7750-ufs2-overlay.dtbo"}, + {"name": "kera-qrd-wcn7750-ufs3-overlay.dtbo"}, + {"name": "kera-rcm-qca6750-ufs4-overlay.dtbo"}, + {"name": "kera-rcm-qca6750-ufs2-overlay.dtbo"}, + {"name": "kera-rcm-qca6750-ufs3-overlay.dtbo"}, + {"name": "kera-rcm-wcn7750-ufs2-overlay.dtbo"}, + {"name": "kera-rcm-wcn7750-ufs3-overlay.dtbo"}, + {"name": "kera-rcm-wcn7750-ufs4-overlay.dtbo"}, ], }, "parrot-tuivm": { @@ -215,14 +243,34 @@ _platform_map = { "kera-tuivm": { "dtb_list": [ # keep sorted + {"name": "kera-oemvm-atp.dtb"}, + {"name": "kera-oemvm-cdp.dtb"}, + {"name": "kera-oemvm-mtp.dtb"}, + {"name": "kera-oemvm-qrd.dtb"}, + {"name": "kera-oemvm-rcm.dtb"}, {"name": "kera-oemvm-rumi.dtb"}, + {"name": "kera-vm-atp.dtb"}, + {"name": "kera-vm-cdp.dtb"}, + {"name": "kera-vm-mtp.dtb"}, + {"name": "kera-vm-qrd.dtb"}, + {"name": "kera-vm-rcm.dtb"}, {"name": "kera-vm-rumi.dtb"}, ], }, "kera-oemvm": { "dtb_list": [ # keep sorted + {"name": "kera-oemvm-atp.dtb"}, + {"name": "kera-oemvm-cdp.dtb"}, + {"name": "kera-oemvm-mtp.dtb"}, + {"name": "kera-oemvm-qrd.dtb"}, + {"name": "kera-oemvm-rcm.dtb"}, {"name": "kera-oemvm-rumi.dtb"}, + {"name": "kera-vm-atp.dtb"}, + {"name": "kera-vm-cdp.dtb"}, + {"name": "kera-vm-mtp.dtb"}, + {"name": "kera-vm-qrd.dtb"}, + {"name": "kera-vm-rcm.dtb"}, {"name": "kera-vm-rumi.dtb"}, ], }, diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi index 534a7689..c8f07c97 100644 --- a/qcom/pm7550ba.dtsi +++ b/qcom/pm7550ba.dtsi @@ -195,6 +195,32 @@ }; }; + vbat { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 2>; + + trips { + vbat_lvl0:vbat-lvl0 { + temperature = <2800>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl1:vbat-lvl1 { + temperature = <2600>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl2:vbat-lvl2 { + temperature = <2300>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + pm7550ba-bcl-lvl0 { polling-delay-passive = <50>; polling-delay = <0>; diff --git a/qcom/pmiv010x.dtsi b/qcom/pmiv010x.dtsi index d53c0606..a0a9578e 100644 --- a/qcom/pmiv010x.dtsi +++ b/qcom/pmiv010x.dtsi @@ -97,6 +97,24 @@ <0x7 0x7d 0x1 IRQ_TYPE_EDGE_RISING>, <0x7 0x98 0x1 IRQ_TYPE_EDGE_RISING>; }; + + pmiv010x_bcl: bcl@4700 { + compatible = "qcom,pmiv010x-bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x7 0x47 0x0 IRQ_TYPE_NONE>, + <0x7 0x47 0x1 IRQ_TYPE_NONE>, + <0x7 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; }; }; @@ -126,4 +144,162 @@ }; }; }; + + pmiv010x-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 0>; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmiv010x-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 1>; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <9000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 5>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl0: b-bcl-lvl0 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 6>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl1: b-bcl-lvl1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + pmiv010x-bcl-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 7>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + b_bcl_lvl2: b-bcl-lvl2 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + }; + }; + + socd { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&bcl_soc>; + + trips { + thermal-engine-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + thermal-hal-trip { + temperature = <100>; + hysteresis = <0>; + type = "passive"; + }; + + socd_trip:socd-trip { + temperature = <90>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + vbat { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmiv010x_bcl 2>; + + trips { + vbat_lvl0:vbat-lvl0 { + temperature = <2800>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl1:vbat-lvl1 { + temperature = <2600>; + hysteresis = <100>; + type = "passive"; + }; + + vbat_lvl2:vbat-lvl2 { + temperature = <2300>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/pmxr2230.dtsi b/qcom/pmxr2230.dtsi index 6a3e5b4c..1bc55ab0 100644 --- a/qcom/pmxr2230.dtsi +++ b/qcom/pmxr2230.dtsi @@ -170,7 +170,7 @@ }; pmxr2230_bcl: bcl@4700 { - compatible = "qcom,bcl-v5"; + compatible = "qcom,pm8550-bcl-v5"; reg = <0x4700 0x100>; interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>, <0x1 0x47 0x1 IRQ_TYPE_NONE>, diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi index e0aed3ad..a3c99b14 100644 --- a/qcom/ravelin-pinctrl.dtsi +++ b/qcom/ravelin-pinctrl.dtsi @@ -468,7 +468,7 @@ qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { mux { pins = "gpio8"; - function = "qup0_se4_l0_mira"; + function = "qup0_se4_l0"; }; config { @@ -481,7 +481,7 @@ qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { mux { pins = "gpio9"; - function = "qup0_se4_l1_mira"; + function = "qup0_se4_l1"; }; config { @@ -509,7 +509,7 @@ qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { mux { pins = "gpio8"; - function = "qup0_se4_l0_mira"; + function = "qup0_se4_l0"; }; config { @@ -522,7 +522,7 @@ qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { mux { pins = "gpio9"; - function = "qup0_se4_l1_mira"; + function = "qup0_se4_l1"; }; config { diff --git a/qcom/ravelin-vm.dtsi b/qcom/ravelin-vm.dtsi index 0f56a622..546df7db 100644 --- a/qcom/ravelin-vm.dtsi +++ b/qcom/ravelin-vm.dtsi @@ -103,7 +103,7 @@ , ; qcom,max-num-gpii = <12>; - qcom,static-gpii-mask = <0x40>; + qcom,static-gpii-mask = <0x20>; qcom,gpii-mask = <0x0>; qcom,ev-factor = <2>; qcom,gpi-ee-offset = <0x10000>; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index da1dece9..aa75a29a 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -28,7 +28,7 @@ chosen: chosen { stdout-path = "/soc/qcom,qup_uart@a88000:115200n8"; - bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat"; + bootargs = "loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat fw_devlink.strict=1"; }; memory { device_type = "memory"; reg = <0 0 0 0>; }; diff --git a/qcom/sdxkova-idp-m2.dts b/qcom/sdxkova-idp-m2.dts index 51d11ed7..7e88fd82 100644 --- a/qcom/sdxkova-idp-m2.dts +++ b/qcom/sdxkova-idp-m2.dts @@ -13,5 +13,6 @@ model = "Qualcomm Technologies, Inc. SDXKOVA IDP M2"; compatible = "qcom,sdxkova-idp", "qcom,sdxkova", "qcom,idp"; + qcom,msm-id = <556 0x10000>, <580 0x10000>, <609 0x10000>, <610 0x10000>; qcom,board-id = <0x4020022 0x304>; }; diff --git a/qcom/sdxkova-pcie.dtsi b/qcom/sdxkova-pcie.dtsi new file mode 100644 index 00000000..8d1a9c35 --- /dev/null +++ b/qcom/sdxkova-pcie.dtsi @@ -0,0 +1,834 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + pcie0: qcom,pcie@1bf0000 { + compatible = "qcom,pci-msm"; + device_type = "pci"; + + reg = <0x0 0x01bf0000 0x0 0x4000>, + <0x0 0x01bf7000 0x0 0x2000>, + <0x0 0x48000000 0x0 0xf20>, + <0x0 0x48000f20 0x0 0xa8>, + <0x0 0x48001000 0x0 0x2000>, + <0x0 0x48100000 0x0 0x100000>, + <0x0 0x01bf4000 0x0 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x48200000 0x0 0x48200000 0x0 0x100000>, + <0x02000000 0x0 0x48300000 0x0 0x48300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie0_msi>; + + perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep + &pcie0_perst_default + &pcie0_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>; + vreg-1p2-supply = <&L1B>; + vreg-0p9-supply = <&L4B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 21700>; + qcom,vreg-0p9-voltage-level = <880000 880000 177000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_sleep_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + + qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <0>; + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + qcom,smmu-sid-base = <0x0800>; + iommu-map = <0x0 &apps_smmu 0x0800 0x1>, + <0x100 &apps_smmu 0x0801 0x1>; + + qcom,boot-option = <0x0>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + qcom,pcie-phy-ver = <111>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x0030 0x18 0x0 + 0x0034 0x03 0x0 + 0x0078 0x01 0x0 + 0x007c 0x00 0x0 + 0x0080 0x51 0x0 + 0x00ac 0x34 0x0 + 0x0208 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0218 0x04 0x0 + 0x0220 0x16 0x0 + 0x0234 0x00 0x0 + 0x029c 0x80 0x0 + 0x02a0 0x7c 0x0 + 0x02b4 0x05 0x0 + 0x02d4 0x10 0x0 + 0x02e8 0x0a 0x0 + 0x030c 0x11 0x0 + 0x0320 0x0b 0x0 + 0x0348 0x1c 0x0 + 0x0388 0x20 0x0 + 0x0394 0x30 0x0 + 0x03dc 0x09 0x0 + 0x03f4 0xd4 0x0 + 0x03f8 0x73 0x0 + 0x03fc 0x18 0x0 + 0x0400 0x9a 0x0 + 0x0404 0x36 0x0 + 0x0408 0xb6 0x0 + 0x040c 0xee 0x0 + 0x0410 0xcb 0x0 + 0x0414 0xcb 0x0 + 0x0418 0xe0 0x0 + 0x041c 0xdf 0x0 + 0x0420 0x78 0x0 + 0x0424 0x76 0x0 + 0x0428 0xff 0x0 + 0x02e0 0x00 0x0 + 0x0830 0x18 0x0 + 0x0834 0x03 0x0 + 0x0878 0x01 0x0 + 0x087c 0x00 0x0 + 0x0880 0x51 0x0 + 0x08ac 0x34 0x0 + 0x0a08 0x0c 0x0 + 0x0a0c 0x0a 0x0 + 0x0a18 0x04 0x0 + 0x0a20 0x16 0x0 + 0x0a34 0x00 0x0 + 0x0a9c 0x80 0x0 + 0x0aa0 0x7c 0x0 + 0x0ab4 0x05 0x0 + 0x0ad4 0x10 0x0 + 0x0ae8 0x0a 0x0 + 0x0b0c 0x11 0x0 + 0x0b20 0x0b 0x0 + 0x0b48 0x1c 0x0 + 0x0b88 0x20 0x0 + 0x0b94 0x30 0x0 + 0x0bdc 0x09 0x0 + 0x0bf4 0xd4 0x0 + 0x0bf8 0x73 0x0 + 0x0bfc 0x18 0x0 + 0x0c00 0x9a 0x0 + 0x0c04 0x36 0x0 + 0x0c08 0xb6 0x0 + 0x0c0c 0xee 0x0 + 0x0c10 0xcb 0x0 + 0x0c14 0xcb 0x0 + 0x0c18 0xe0 0x0 + 0x0c1c 0xdf 0x0 + 0x0c20 0x78 0x0 + 0x0c24 0x76 0x0 + 0x0c28 0xff 0x0 + 0x0ae0 0x00 0x0 + 0x0ea0 0x01 0x0 + 0x0eb4 0x00 0x0 + 0x0ec4 0x02 0x0 + 0x0ec8 0x0d 0x0 + 0x0ed4 0xd4 0x0 + 0x0ed8 0x12 0x0 + 0x0edc 0xdb 0x0 + 0x0ee0 0x9a 0x0 + 0x0ee4 0x35 0x0 + 0x0ee8 0xb6 0x0 + 0x0eec 0x64 0x0 + 0x0ef0 0x1f 0x0 + 0x0ef4 0x1f 0x0 + 0x0ef8 0x1f 0x0 + 0x0efc 0x1f 0x0 + 0x0f00 0x1f 0x0 + 0x0f04 0x1f 0x0 + 0x0f0c 0x1f 0x0 + 0x0f14 0x1f 0x0 + 0x0f1c 0x1f 0x0 + 0x0f28 0x5b 0x0 + 0x1000 0x97 0x0 + 0x1004 0x0c 0x0 + 0x1010 0x06 0x0 + 0x1014 0x16 0x0 + 0x1018 0x36 0x0 + 0x101c 0x04 0x0 + 0x1020 0x14 0x0 + 0x1024 0x34 0x0 + 0x1028 0xd0 0x0 + 0x1030 0x55 0x0 + 0x1034 0x55 0x0 + 0x1038 0x05 0x0 + 0x103c 0x12 0x0 + 0x1060 0xde 0x0 + 0x1064 0x07 0x0 + 0x1070 0x06 0x0 + 0x1074 0x16 0x0 + 0x1078 0x36 0x0 + 0x107c 0x0a 0x0 + 0x1080 0x0a 0x0 + 0x1084 0x1a 0x0 + 0x1088 0x82 0x0 + 0x1090 0x55 0x0 + 0x1094 0x55 0x0 + 0x1098 0x03 0x0 + 0x109c 0x00 0x0 + 0x10bc 0x0e 0x0 + 0x10c0 0x01 0x0 + 0x10cc 0x31 0x0 + 0x10d0 0x01 0x0 + 0x10d8 0x40 0x0 + 0x10dc 0x14 0x0 + 0x10e0 0x90 0x0 + 0x10e4 0x82 0x0 + 0x10f4 0x0f 0x0 + 0x1110 0x08 0x0 + 0x1120 0x46 0x0 + 0x1124 0x04 0x0 + 0x1140 0x14 0x0 + 0x1164 0x34 0x0 + 0x1170 0xa0 0x0 + 0x1174 0x06 0x0 + 0x1184 0x88 0x0 + 0x1188 0x14 0x0 + 0x1198 0x0f 0x0 + 0x1378 0x2e 0x0 + 0x1390 0xcc 0x0 + 0x13f8 0x00 0x0 + 0x13fc 0x22 0x0 + 0x141c 0xc1 0x0 + 0x129c 0x83 0x0 + 0x12a0 0x09 0x0 + 0x12a4 0xa2 0x0 + 0x1450 0x03 0x0 + 0x1490 0x00 0x0 + 0x14a0 0x16 0x0 + 0x14f0 0x27 0x0 + 0x14f4 0x27 0x0 + 0x1508 0x02 0x0 + 0x155c 0x2e 0x0 + 0x157c 0x03 0x0 + 0x1584 0x28 0x0 + 0x13dc 0x04 0x0 + 0x13e0 0x02 0x0 + 0x1418 0xc0 0x0 + 0x140c 0x1d 0x0 + 0x158c 0x0f 0x0 + 0x15ac 0xf2 0x0 + 0x15c0 0xf2 0x0 + 0x1370 0x17 0x0 + 0x1a38 0x00 0x0 + 0x1e38 0x00 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + status = "disabled"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x0 0xa0000000 0x0 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + device_type = "pci"; + + reg = <0x0 0x01c08000 0x0 0x4000>, + <0x0 0x01c0e000 0x0 0x2000>, + <0x0 0x68000000 0x0 0xf1d>, + <0x0 0x68000f20 0x0 0xa8>, + <0x0 0x68001000 0x0 0x1000>, + <0x0 0x68100000 0x0 0x100000>, + <0x0 0x01c0c000 0x0 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, + <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie1_msi>; + + perst-gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 123 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_clkreq_sleep + &pcie1_perst_default + &pcie1_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>; + vreg-1p2-supply = <&L1B>; + vreg-0p9-supply = <&L4B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 12000>; + qcom,vreg-0p9-voltage-level = <912000 880000 77800>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie_1_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_pipe_div2_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + qcom,smmu-sid-base = <0x0880>; + iommu-map = <0x0 &apps_smmu 0x0880 0x1>, + <0x100 &apps_smmu 0x0881 0x1>; + + qcom,boot-option = <0x0>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + qcom,pcie-phy-ver = <112>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x00c0 0x01 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x0060 0xff 0x0 + 0x0064 0x06 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x02 0x0 + 0x0010 0x02 0x0 + 0x0074 0x16 0x0 + 0x0014 0x16 0x0 + 0x0078 0x36 0x0 + 0x0018 0x36 0x0 + 0x0110 0x08 0x0 + 0x00bc 0x0e 0x0 + 0x0120 0x42 0x0 + 0x0080 0x08 0x0 + 0x0084 0x1a 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0088 0x82 0x0 + 0x0028 0x68 0x0 + 0x0090 0xab 0x0 + 0x0094 0xea 0x0 + 0x0098 0x02 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x0d 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x1600 0x00 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x0d 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x06f4 0x27 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0614 0x07 0x0 + 0x0620 0xc1 0x0 + 0x0694 0x00 0x0 + 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 + 0x1424 0x00 0x0 + 0x1428 0x00 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + status = "disabled"; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + + }; + }; + + pcie1_msi: qcom,pcie1_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x0 0xa0000000 0x0 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; + + pcie2: qcom,pcie@1c10000 { + compatible = "qcom,pci-msm"; + device_type = "pci"; + + reg = <0x0 0x01c10000 0x0 0x4000>, + <0x0 0x1c16000 0x0 0x2000>, + <0x0 0x6c000000 0x0 0xf1d>, + <0x0 0x6c000f20 0x0 0xa8>, + <0x0 0x6c001000 0x0 0x1000>, + <0x0 0x6c100000 0x0 0x100000>, + <0x0 0x01c14000 0x0 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", "iatu", + "conf", "mhi"; + + cell-index = <2>; + linux,pci-domain = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x6c200000 0x0 0x6c200000 0x0 0x100000>, + <0x02000000 0x0 0x6c300000 0x0 0x6c300000 0x0 0x3d00000>; + + interrupt-parent = <&pcie2>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + + msi-parent = <&pcie2_msi>; + + perst-gpio = <&tlmm 122 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 120 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie2_clkreq_default + &pcie2_perst_default + &pcie2_wake_default>; + pinctrl-1 = <&pcie2_clkreq_sleep + &pcie2_perst_default + &pcie2_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_2_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_2_phy_gdsc>; + vreg-1p2-supply = <&L1B>; + vreg-0p9-supply = <&L4B>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <912000 880000 48000>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + qcom,bw-scale = /* Gen1 */ + ; + + interconnect-names = "icc_path"; + interconnects = <&pcie_anoc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_2_AUX_CLK>, + <&gcc GCC_PCIE_2_CFG_AHB_CLK>, + <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_AXI_CLK>, + <&gcc GCC_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_PIPE_DIV2_CLK>, + <&gcc GCC_PCIE_2_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_2_PIPE_CLK_SRC>, + <&pcie_2_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_aux_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_clkref_en", "pcie_slv_q2a_axi_clk", + "pcie_pipe_div2_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; + qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <100000000>, <0>, <0>; + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, + <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_2_BCR>, + <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "pcie_2_core_reset", + "pcie_2_phy_reset"; + + qcom,smmu-sid-base = <0x0900>; + iommu-map = <0x0 &apps_smmu 0x0900 0x1>, + <0x100 &apps_smmu 0x0901 0x1>; + + qcom,boot-option = <0x0>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,tpwr-on-scale = <1>; + qcom,tpwr-on-value = <9>; + qcom,eq-fmdc-t-min-phase23 = <1>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; + qcom,ep-latency = <10>; + qcom,num-parf-testbus-sel = <0xb9>; + + qcom,pcie-phy-ver = <105>; + qcom,phy-status-offset = <0x214>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x240>; + qcom,phy-sequence = <0x0240 0x03 0x0 + 0x0000 0x4c 0x0 + 0x0004 0x06 0x0 + 0x0010 0x02 0x0 + 0x0014 0x16 0x0 + 0x0018 0x36 0x0 + 0x001c 0x04 0x0 + 0x0020 0x14 0x0 + 0x0024 0x34 0x0 + 0x0028 0x68 0x0 + 0x0030 0xab 0x0 + 0x0034 0xaa 0x0 + 0x0038 0x02 0x0 + 0x003c 0x01 0x0 + 0x0048 0xb4 0x0 + 0x004c 0x03 0x0 + 0x0060 0xde 0x0 + 0x0064 0x07 0x0 + 0x0070 0x02 0x0 + 0x0074 0x16 0x0 + 0x0078 0x36 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 + 0x0088 0x82 0x0 + 0x0090 0xab 0x0 + 0x0094 0xea 0x0 + 0x0098 0x02 0x0 + 0x00a8 0x24 0x0 + 0x00bc 0x0e 0x0 + 0x00c0 0x00 0x0 + 0x00cc 0x31 0x0 + 0x00d0 0x01 0x0 + 0x00e0 0x90 0x0 + 0x00e4 0x82 0x0 + 0x00f4 0x07 0x0 + 0x0110 0x08 0x0 + 0x0120 0x42 0x0 + 0x0140 0x14 0x0 + 0x0164 0x34 0x0 + 0x0170 0xa0 0x0 + 0x0174 0x16 0x0 + 0x01bc 0x0f 0x0 + 0x02dc 0x05 0x0 + 0x0370 0x2e 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x03d0 0x0c 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x1d 0x0 + 0x0620 0xc1 0x0 + 0x0654 0x00 0x0 + 0x0694 0x00 0x0 + 0x06f4 0x27 0x0 + 0x0e3c 0x17 0x0 + 0x0e40 0x06 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ea4 0x12 0x0 + 0x0ee4 0x02 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x1034 0x7f 0x0 + 0x1044 0xf0 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1060 0x30 0x0 + 0x10cc 0xf0 0x0 + 0x10d4 0x04 0x0 + 0x10d8 0x0f 0x0 + 0x10dc 0x0d 0x0 + 0x10ec 0x0e 0x0 + 0x10f0 0x4a 0x0 + 0x10f4 0x0a 0x0 + 0x10f8 0x07 0x0 + 0x1110 0x14 0x0 + 0x1118 0x0c 0x0 + 0x115c 0x3f 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x1170 0xdc 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x11a4 0x38 0x0 + 0x11f8 0x08 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + status = "disabled"; + + pcie2_rp: pcie2_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie2_msi: qcom,pcie2_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x0 0xa0000000 0x0 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + ; + qcom,snps; + }; +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 4f0c8227..bf3ad21f 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -6,6 +6,8 @@ #include #include #include "sdx75.dtsi" +#include +#include /delete-node/ &apps_smmu; /delete-node/ &tcsr_mutex; #include "msm-arm-smmu-sdxkova.dtsi" @@ -293,6 +295,168 @@ }; }; + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio43"; + function = "pcie0_clkreq_n"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_clkreq_sleep: pcie0_clkreq_sleep { + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio124"; + function = "pcie1_clkreq_n"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_clkreq_sleep: pcie1_clkreq_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio121"; + function = "pcie2_clkreq_n"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_clkreq_sleep: pcie2_clkreq_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { qupv3_se3_default_cts: qupv3_se3_default_cts { mux { @@ -1086,7 +1250,7 @@ #include "sdxkova-regulators.dtsi" &chosen { - bootargs = "cpufreq.default_governor=performance"; + bootargs = "cpufreq.default_governor=performance pcie_ports=compat"; }; &soc { @@ -1820,6 +1984,7 @@ <&qupv3_se3_tx>, <&qupv3_se3_default_rx>; pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>, <&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>; + qcom,suspend-ignore-children; qcom,wakeup-byte = <0xFD>; status = "disabled"; }; @@ -2130,6 +2295,7 @@ #include "sdxkova-usb.dtsi" #include "ipcc-test-sdxkova.dtsi" +#include "sdxkova-pcie.dtsi" &CPU0 { /delete-property/ clocks; diff --git a/qcom/sun-coresight.dtsi b/qcom/sun-coresight.dtsi index 5c18f218..46a3d97a 100644 --- a/qcom/sun-coresight.dtsi +++ b/qcom/sun-coresight.dtsi @@ -330,7 +330,6 @@ coresight-name = "coresight-tpdm-eva"; - status = "disabled"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -354,7 +353,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; in-ports { #address-cells = <1>; @@ -1395,7 +1393,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - static = "disabled"; + status = "disabled"; out-ports { port { @@ -1766,6 +1764,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1789,6 +1788,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1812,6 +1812,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1835,6 +1836,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1858,6 +1860,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1881,6 +1884,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1904,6 +1908,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1927,6 +1932,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1950,6 +1956,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1973,6 +1980,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -1996,6 +2004,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -2019,6 +2028,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; out-ports { port { @@ -2056,6 +2066,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -2253,6 +2264,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2362,6 +2374,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2471,6 +2484,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2580,6 +2594,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2689,6 +2704,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2798,6 +2814,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2835,6 +2852,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -2929,6 +2947,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -2964,6 +2983,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -3001,6 +3021,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -3046,6 +3067,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD0>; + qcom,atclk-dependence; in-ports { port { @@ -3151,6 +3173,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { port { @@ -3259,6 +3282,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { port { @@ -3296,6 +3320,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -3358,6 +3383,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { port { @@ -3393,6 +3419,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { port { @@ -3430,6 +3457,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -3475,6 +3503,7 @@ clock-names = "apb_pclk", "atclk"; power-domains = <&CLUSTER_PD1>; + qcom,atclk-dependence; in-ports { port { @@ -3507,6 +3536,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; in-ports { #address-cells = <1>; @@ -4656,7 +4686,7 @@ reg = <19>; tn_ag_in_tpdm_qm: endpoint { remote-endpoint = - <&tpdm_prng_out_tn_ag>; + <&tpdm_qm_out_tn_ag>; }; }; @@ -5628,6 +5658,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; }; cti@12195000 { @@ -5642,6 +5673,7 @@ <&scmi_clk 0>; clock-names = "apb_pclk", "atclk"; + qcom,atclk-dependence; }; cti@10a05000 { diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index 3d9ec679..22d806c0 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -290,6 +290,8 @@ /* */ /* Adjust HS trasmit amplitude */ <0xa 0x51 + /* Squelch detection threshold */ + 0x4 0x54 /* Tx pre-emphasis tuning */ 0x3 0x57>; }; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 44909887..40e2f55a 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -33,12 +33,6 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; - - chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops slub_debug=-"; - stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; - }; - aliases: aliases { serial0 = &qupv3_se7_2uart; hsuart0 = &qupv3_se14_4uart; @@ -46,6 +40,11 @@ mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; + chosen: chosen { + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops slub_debug=-"; + stdout-path = "serial0:115200n8"; + }; + firmware: firmware { qcom_scm: qcom_scm { }; }; diff --git a/qcom/tuna-atp-overlay.dts b/qcom/tuna-atp-overlay.dts index 6c4d6b9a..890bec4f 100644 --- a/qcom/tuna-atp-overlay.dts +++ b/qcom/tuna-atp-overlay.dts @@ -15,6 +15,6 @@ compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", "qcom,atp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <33 0>; }; diff --git a/qcom/tuna-atp.dtsi b/qcom/tuna-atp.dtsi index 386415d7..ac5fccfa 100644 --- a/qcom/tuna-atp.dtsi +++ b/qcom/tuna-atp.dtsi @@ -4,3 +4,13 @@ */ #include "tuna-mtp.dtsi" + +&S1G { + regulator-min-microvolt = <806000>; + regulator-max-microvolt = <1003000>; + qcom,init-voltage = <852000>; +}; + +&L3G { + regulator-always-on; +}; diff --git a/qcom/tuna-cdp-overlay.dts b/qcom/tuna-cdp-overlay.dts index 04abc04c..0a3ff93e 100644 --- a/qcom/tuna-cdp-overlay.dts +++ b/qcom/tuna-cdp-overlay.dts @@ -14,6 +14,6 @@ compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", "qcom,cdp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <1 0>; }; diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index d048ade7..eb92e52c 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -4,6 +4,7 @@ */ #include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; @@ -42,7 +43,7 @@ }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + compatible = "qcom,ufs-phy-qmp-v4-niobe"; /* VDDA_UFS_CORE */ vdda-phy-supply = <&L1F>; diff --git a/qcom/tuna-coresight.dtsi b/qcom/tuna-coresight.dtsi index 5ec91dd5..00778ee5 100644 --- a/qcom/tuna-coresight.dtsi +++ b/qcom/tuna-coresight.dtsi @@ -96,7 +96,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -336,7 +335,6 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; - status = "disabled"; out-ports { port { @@ -3991,7 +3989,7 @@ real-name = "coresight-tmc-etr1"; qdss,buffer-size = <0x2000000>; qcom,secure-component; - /* memory-region = <&qdss_apps_mem>;*/ + memory-region = <&qdss_apps_mem>; coresight-csr = <&csr>; csr-atid-offset = <0x108>; csr-irqctrl-offset = <0x70>; diff --git a/qcom/tuna-debug.dtsi b/qcom/tuna-debug.dtsi index 008e38e9..1baaf8dd 100644 --- a/qcom/tuna-debug.dtsi +++ b/qcom/tuna-debug.dtsi @@ -20,12 +20,12 @@ dcc: dcc_v2@100ff000 { compatible = "qcom,dcc-v2"; reg = <0x100ff000 0x1000>, - <0x10084000 0x4000>; + <0x10080000 0x8000>; qcom,transaction_timeout = <0>; reg-names = "dcc-base", "dcc-ram-base"; - dcc-ram-offset = <0x4000>; + dcc-ram-offset = <0x0>; }; mem_dump { diff --git a/qcom/tuna-mtp-kiwi-harmonium-overlay.dts b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts index dfaff3ba..f5d40a7a 100644 --- a/qcom/tuna-mtp-kiwi-harmonium-overlay.dts +++ b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 3>; }; diff --git a/qcom/tuna-mtp-kiwi-overlay.dts b/qcom/tuna-mtp-kiwi-overlay.dts index bb6fefd8..73fc707a 100644 --- a/qcom/tuna-mtp-kiwi-overlay.dts +++ b/qcom/tuna-mtp-kiwi-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 2>; }; diff --git a/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts b/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts index a08d35a8..88cdeac5 100644 --- a/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts +++ b/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + pmd802x"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 2>; }; diff --git a/qcom/tuna-mtp-kiwi.dtsi b/qcom/tuna-mtp-kiwi.dtsi index 386415d7..ac5fccfa 100644 --- a/qcom/tuna-mtp-kiwi.dtsi +++ b/qcom/tuna-mtp-kiwi.dtsi @@ -4,3 +4,13 @@ */ #include "tuna-mtp.dtsi" + +&S1G { + regulator-min-microvolt = <806000>; + regulator-max-microvolt = <1003000>; + qcom,init-voltage = <852000>; +}; + +&L3G { + regulator-always-on; +}; diff --git a/qcom/tuna-mtp-nfc-overlay.dts b/qcom/tuna-mtp-nfc-overlay.dts index 440dcc09..9e5acb6f 100644 --- a/qcom/tuna-mtp-nfc-overlay.dts +++ b/qcom/tuna-mtp-nfc-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + SN220/SN300 NFC"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 4>; }; diff --git a/qcom/tuna-mtp-overlay.dts b/qcom/tuna-mtp-overlay.dts index 006e66f8..21a67a97 100644 --- a/qcom/tuna-mtp-overlay.dts +++ b/qcom/tuna-mtp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 0>; }; diff --git a/qcom/tuna-mtp-qmp1000-overlay.dts b/qcom/tuna-mtp-qmp1000-overlay.dts index 85d26b68..85add169 100644 --- a/qcom/tuna-mtp-qmp1000-overlay.dts +++ b/qcom/tuna-mtp-qmp1000-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 1>; }; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 339aa4f6..20a874ec 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -44,7 +44,7 @@ }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + compatible = "qcom,ufs-phy-qmp-v4-niobe"; /* VDDA_UFS_CORE */ vdda-phy-supply = <&L1F>; @@ -108,3 +108,6 @@ status = "ok"; }; +&usb0 { + qcom,wcd_usbss = <&wcd_usbss>; +}; diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 2efd2aae..2601180b 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -214,6 +214,15 @@ qcom,label = <0xe>; peer-default; }; + + msgqsock-msgq-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/msgqsock-msgq-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + peer = "vm-name:qcom,trustedvm"; + qcom,label = <0x3>; + }; }; }; @@ -321,6 +330,11 @@ gunyah-label = <8>; }; + qmsgq-gunyah { + compatible = "qcom,qmsgq-gh"; + msgq-label = <3>; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <512>; diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi index d50e57d9..1080a5ca 100644 --- a/qcom/tuna-pcie.dtsi +++ b/qcom/tuna-pcie.dtsi @@ -108,7 +108,7 @@ "gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", "pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; - clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, + qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>; diff --git a/qcom/tuna-pm7550ba-pmd802x.dtsi b/qcom/tuna-pm7550ba-pmd802x.dtsi index f338c006..e93d1138 100644 --- a/qcom/tuna-pm7550ba-pmd802x.dtsi +++ b/qcom/tuna-pm7550ba-pmd802x.dtsi @@ -19,6 +19,16 @@ status = "disabled"; }; +&spmi0_debug_bus { + pmd802x@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; +}; + &pmic_glink_debug { /delete-node/ i2c@104; /delete-node/ spmi@200; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index 341597f4..a4503e9a 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -258,6 +258,74 @@ }; }; }; + + pm7550ba-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_0_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7550ba-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; +}; + +&pm7550ba_eusb2_repeater { + vdd18-supply = <&L7B>; + vdd3-supply = <&L17B>; + status = "ok"; +}; + +&eusb2_phy0 { + dummy-supply = <&pm7550ba_eusb2_repeater>; + usb-repeater = <&pm7550ba_eusb2_repeater>; }; &pm7550ba_eusb2_repeater { diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi index bc82d7e3..f81e83c8 100644 --- a/qcom/tuna-pmic-overlay.dtsi +++ b/qcom/tuna-pmic-overlay.dtsi @@ -184,25 +184,6 @@ }; }; - sys-therm-1 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - active-config1 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - sys-therm-2 { polling-delay-passive = <0>; polling-delay = <0>; @@ -361,15 +342,6 @@ qcom,adc-tm-type = <1>; }; - pmxr2230_sys_therm_1 { - reg = ; - label = "pmxr2230_sys_therm_1"; - qcom,ratiometric; - qcom,hw-settle-time = <200>; - qcom,pre-scaling = <1 1>; - qcom,adc-tm-type = <1>; - }; - pmxr2230_sys_therm_2 { reg = ; label = "pmxr2230_sys_therm_2"; @@ -432,13 +404,13 @@ pm8550vs_g_die_temp { reg = ; - label = "pm8550vs_j_die_temp"; + label = "pm8550vs_g_die_temp"; qcom,pre-scaling = <1 1>; }; pm8550ve_f_die_temp { reg = ; - label = "pm8550ve_d_die_temp"; + label = "pm8550ve_f_die_temp"; qcom,pre-scaling = <1 1>; }; @@ -458,3 +430,8 @@ io-channels = <&pmk8550_vadc PM8550VX_ADC5_GEN3_DIE_TEMP(5)>; io-channel-names = "thermal"; }; + +&pmxr2230_tz { + io-channels = <&pmk8550_vadc PMXR2230_ADC5_GEN3_DIE_TEMP>; + io-channel-names = "thermal"; +}; diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi index e90b1c6e..e4baf8e7 100644 --- a/qcom/tuna-pmih010x.dtsi +++ b/qcom/tuna-pmih010x.dtsi @@ -197,6 +197,117 @@ }; }; }; + + pmih010x-ibat-lvl0 { + trips { + ibat-lvl0 { + temperature = <7000>; + }; + }; + }; + + pmih010x-ibat-lvl1 { + trips { + ibat-lvl1 { + temperature = <9000>; + }; + }; + }; + + pmih010x-2s-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmih010x_bcl 8>; + + trips { + ibat_2s_lvl0: ibat-2s-lvl0 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmih010x-2s-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmih010x_bcl 9>; + + trips { + ibat_2s_lvl1: ibat-2s-lvl1 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmih010x-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmih010x-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmih010x-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; +}; + +&pmih010x_eusb2_repeater { + vdd18-supply = <&L7B>; + vdd3-supply = <&L17B>; +}; + +&eusb2_phy0 { + dummy-supply = <&pmih010x_eusb2_repeater>; + usb-repeater = <&pmih010x_eusb2_repeater>; }; &pmih010x_eusb2_repeater { diff --git a/qcom/tuna-pmiv0108.dtsi b/qcom/tuna-pmiv0108.dtsi index fdb246ad..2c549098 100644 --- a/qcom/tuna-pmiv0108.dtsi +++ b/qcom/tuna-pmiv0108.dtsi @@ -183,6 +183,73 @@ }; }; }; + + pmiv010x-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmiv010x-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_1_gpu { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmiv010x-bcl-lvl2 { + cooling-maps { + lbat_2_gpu { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; +}; + +&pmiv010x_eusb2_repeater { + vdd18-supply = <&L7B>; + vdd3-supply = <&L17B>; +}; + +&eusb2_phy0 { + dummy-supply = <&pmiv010x_eusb2_repeater>; + usb-repeater = <&pmiv010x_eusb2_repeater>; }; &pmiv010x_eusb2_repeater { diff --git a/qcom/tuna-qrd-overlay.dts b/qcom/tuna-qrd-overlay.dts index 8ee4d7ae..74ee86f0 100644 --- a/qcom/tuna-qrd-overlay.dts +++ b/qcom/tuna-qrd-overlay.dts @@ -14,6 +14,6 @@ model = "Qualcomm Technologies, Inc. Tuna QRD"; compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", "qcom,qrd"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <11 0>; }; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index d6c949e5..f5b69fc1 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -46,7 +46,7 @@ }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-pineapple"; + compatible = "qcom,ufs-phy-qmp-v4-niobe"; /* VDDA_UFS_CORE */ vdda-phy-supply = <&L1F>; @@ -121,3 +121,54 @@ &thermal_zones { /delete-node/ sys-therm-11; }; + +&qupv3_se5_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + + vdd-supply = <&L7B>; + + lane-channel-swap; + + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x5 0x7 0x7 0x5>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x0 0x3 0x3 0x0>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; + +&usb_qmp_dp_phy { + pinctrl-names = "unused"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_gpio>; + gpios = <&tlmm 122 0>; + + ssusb_redriver = <&redriver>; + + qcom,wcd_usbss = <&wcd_usbss>; + +}; diff --git a/qcom/tuna-rcm-kiwi-overlay.dts b/qcom/tuna-rcm-kiwi-overlay.dts index 10c4409c..b71af0ea 100644 --- a/qcom/tuna-rcm-kiwi-overlay.dts +++ b/qcom/tuna-rcm-kiwi-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 1>; }; diff --git a/qcom/tuna-rcm-kiwi.dtsi b/qcom/tuna-rcm-kiwi.dtsi index eb5ff5d3..c41e8af8 100644 --- a/qcom/tuna-rcm-kiwi.dtsi +++ b/qcom/tuna-rcm-kiwi.dtsi @@ -4,3 +4,13 @@ */ #include "tuna-cdp.dtsi" + +&S1G { + regulator-min-microvolt = <806000>; + regulator-max-microvolt = <1003000>; + qcom,init-voltage = <852000>; +}; + +&L3G { + regulator-always-on; +}; diff --git a/qcom/tuna-rcm-overlay.dts b/qcom/tuna-rcm-overlay.dts index c47d003b..b80e2c2f 100644 --- a/qcom/tuna-rcm-overlay.dts +++ b/qcom/tuna-rcm-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna RCM"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 0>; }; diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index fd4dd00a..8071f35e 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -9,8 +9,8 @@ rpmh-regulator-smpb1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb1"; - S1B: - pmxr2230_s1: regulator-pmxr2230-s1 { + + S1B: pmxr2230_s1: vreg-pmxr2230-s1 { regulator-name = "pmxr2230_s1"; qcom,set = ; regulator-min-microvolt = <1856000>; @@ -22,8 +22,8 @@ rpmh-regulator-smpb2 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb2"; - S2B: - pmxr2230_s2: regulator-pmxr2230-s2 { + + S2B: pmxr2230_s2: vreg-pmxr2230-s2 { regulator-name = "pmxr2230_s2"; qcom,set = ; regulator-min-microvolt = <1256000>; @@ -35,8 +35,8 @@ rpmh-regulator-smpb3 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpb3"; - S3B: - pmxr2230_s3: regulator-pmxr2230-s3 { + + S3B: pmxr2230_s3: vreg-pmxr2230-s3 { regulator-name = "pmxr2230_s3"; qcom,set = ; regulator-min-microvolt = <880000>; @@ -51,10 +51,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1B: - pmxr2230_l1: regulator-pmxr2230-l1 { + + L1B: pmxr2230_l1: vreg-pmxr2230-l1 { regulator-name = "pmxr2230_l1"; qcom,set = ; regulator-min-microvolt = <866000>; @@ -70,16 +70,19 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L2B: - pmxr2230_l2: regulator-pmxr2230-l2 { + proxy-supply = <&L2B>; + + L2B: pmxr2230_l2: vreg-pmxr2230-l2 { regulator-name = "pmxr2230_l2"; qcom,set = ; regulator-min-microvolt = <880000>; - regulator-max-microvolt = <950000>; + regulator-max-microvolt = <925000>; qcom,init-voltage = <880000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <98000>; }; }; @@ -89,14 +92,14 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L3B: - pmxr2230_l3: regulator-pmxr2230-l3 { + + L3B: pmxr2230_l3: vreg-pmxr2230-l3 { regulator-name = "pmxr2230_l3"; qcom,set = ; - regulator-min-microvolt = <831000>; - regulator-max-microvolt = <919000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; qcom,init-voltage = <880000>; qcom,init-mode = ; }; @@ -108,16 +111,19 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L4B: - pmxr2230_l4: regulator-pmxr2230-l4 { + proxy-supply = <&L4B>; + + L4B: pmxr2230_l4: vreg-pmxr2230-l4 { regulator-name = "pmxr2230_l4"; qcom,set = ; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <16600>; }; }; @@ -127,11 +133,11 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000 30000>; - L5B: - pmxr2230_l5: regulator-pmxr2230-l5 { + + L5B: pmxr2230_l5: vreg-pmxr2230-l5 { regulator-name = "pmxr2230_l5"; qcom,set = ; regulator-min-microvolt = <1200000>; @@ -147,16 +153,18 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L6B: - pmxr2230_l6: regulator-pmxr2230-l6 { + status = "disabled"; + + L6B: pmxr2230_l6: vreg-pmxr2230-l6 { regulator-name = "pmxr2230_l6"; qcom,set = ; regulator-min-microvolt = <1170000>; regulator-max-microvolt = <1370000>; qcom,init-voltage = <1256000>; qcom,init-mode = ; + status = "disabled"; }; }; @@ -166,10 +174,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L7B: - pmxr2230_l7: regulator-pmxr2230-l7 { + + L7B: pmxr2230_l7: vreg-pmxr2230-l7 { regulator-name = "pmxr2230_l7"; qcom,set = ; regulator-min-microvolt = <1800000>; @@ -185,16 +193,19 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L8B: - pmxr2230_l8: regulator-pmxr2230-l8 { + proxy-supply = <&L8B>; + + L8B: pmxr2230_l8: vreg-pmxr2230-l8 { regulator-name = "pmxr2230_l8"; qcom,set = ; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <154000>; }; }; @@ -204,10 +215,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L9B: - pmxr2230_l9: regulator-pmxr2230-l9 { + + L9B: pmxr2230_l9: vreg-pmxr2230-l9 { regulator-name = "pmxr2230_l9"; qcom,set = ; regulator-min-microvolt = <756000>; @@ -223,10 +234,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L10B: - pmxr2230_l10: regulator-pmxr2230-l10 { + + L10B: pmxr2230_l10: vreg-pmxr2230-l10 { regulator-name = "pmxr2230_l10"; qcom,set = ; regulator-min-microvolt = <866000>; @@ -242,13 +253,13 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L11B: - pmxr2230_l11: regulator-pmxr2230-l11 { + + L11B: pmxr2230_l11: vreg-pmxr2230-l11 { regulator-name = "pmxr2230_l11"; qcom,set = ; - regulator-min-microvolt = <1620000>; + regulator-min-microvolt = <1080000>; regulator-max-microvolt = <2000000>; qcom,init-voltage = <1800000>; qcom,init-mode = ; @@ -261,10 +272,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L12B: - pmxr2230_l12: regulator-pmxr2230-l12 { + + L12B: pmxr2230_l12: vreg-pmxr2230-l12 { regulator-name = "pmxr2230_l12"; qcom,set = ; regulator-min-microvolt = <2400000>; @@ -280,10 +291,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L13B: - pmxr2230_l13: regulator-pmxr2230-l13 { + + L13B: pmxr2230_l13: vreg-pmxr2230-l13 { regulator-name = "pmxr2230_l13"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -299,16 +310,18 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L14B: - pmxr2230_l14: regulator-pmxr2230-l14 { + status = "disabled"; + + L14B: pmxr2230_l14: vreg-pmxr2230-l14 { regulator-name = "pmxr2230_l14"; qcom,set = ; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <3544000>; qcom,init-voltage = <2800000>; qcom,init-mode = ; + status = "disabled"; }; }; @@ -318,10 +331,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L15B: - pmxr2230_l15: regulator-pmxr2230-l15 { + + L15B: pmxr2230_l15: vreg-pmxr2230-l15 { regulator-name = "pmxr2230_l15"; qcom,set = ; regulator-min-microvolt = <1620000>; @@ -337,10 +350,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L16B: - pmxr2230_l16: regulator-pmxr2230-l16 { + + L16B: pmxr2230_l16: vreg-pmxr2230-l16 { regulator-name = "pmxr2230_l16"; qcom,set = ; regulator-min-microvolt = <2600000>; @@ -356,10 +369,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L17B: - pmxr2230_l17: regulator-pmxr2230-l17 { + + L17B: pmxr2230_l17: vreg-pmxr2230-l17 { regulator-name = "pmxr2230_l17"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -375,10 +388,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L18B: - pmxr2230_l18: regulator-pmxr2230-l18 { + + L18B: pmxr2230_l18: vreg-pmxr2230-l18 { regulator-name = "pmxr2230_l18"; qcom,set = ; regulator-min-microvolt = <1600000>; @@ -394,16 +407,19 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L19B: - pmxr2230_l19: regulator-pmxr2230-l19 { + proxy-supply = <&L19B>; + + L19B: pmxr2230_l19: vreg-pmxr2230-l19 { regulator-name = "pmxr2230_l19"; qcom,set = ; regulator-min-microvolt = <2650000>; regulator-max-microvolt = <3544000>; qcom,init-voltage = <3000000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <10000>; }; }; @@ -413,10 +429,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L20B: - pmxr2230_l20: regulator-pmxr2230-l20 { + + L20B: pmxr2230_l20: vreg-pmxr2230-l20 { regulator-name = "pmxr2230_l20"; qcom,set = ; regulator-min-microvolt = <1504000>; @@ -432,10 +448,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L21B: - pmxr2230_l21: regulator-pmxr2230-l21 { + + L21B: pmxr2230_l21: vreg-pmxr2230-l21 { regulator-name = "pmxr2230_l21"; qcom,set = ; regulator-min-microvolt = <1504000>; @@ -451,10 +467,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L22B: - pmxr2230_l22: regulator-pmxr2230-l22 { + + L22B: pmxr2230_l22: vreg-pmxr2230-l22 { regulator-name = "pmxr2230_l22"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -470,10 +486,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 10000>; - L23B: - pmxr2230_l23: regulator-pmxr2230-l23 { + + L23B: pmxr2230_l23: vreg-pmxr2230-l23 { regulator-name = "pmxr2230_l23"; qcom,set = ; regulator-min-microvolt = <1650000>; @@ -489,11 +505,11 @@ qcom,regulator-type = "pmic5-bob"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 1000000 2000000>; - BOB: - pmxr2230_bob: regulator-pmxr2230-bob1 { + + BOB: pmxr2230_bob: vreg-pmxr2230-bob1 { regulator-name = "pmxr2230_bob"; qcom,set = ; regulator-min-microvolt = <3008000>; @@ -505,9 +521,10 @@ rpmh-regulator-msslvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: S1D_LEVEL: - pm_v6d_s1_level: regulator-pm_v6d-s1-level { + pm_v6d_s1_level: vreg-pm_v6d-s1-level { regulator-name = "pm_v6d_s1_level"; qcom,set = ; regulator-min-microvolt = @@ -521,9 +538,10 @@ rpmh-regulator-nsplvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "nsp.lvl"; + VDD_NSP1_LEVEL: S4D_LEVEL: - pm_v6d_s4_level: regulator-pm_v6d-s4-level { + pm_v6d_s4_level: vreg-pm_v6d-s4-level { regulator-name = "pm-v6d_s4_level"; qcom,set = ; regulator-min-microvolt = @@ -537,9 +555,10 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S5F_LEVEL: - pm_v8f_s5_level: regulator-pm_v8f-s5-level { + pm_v8f_s5_level: vreg-pm_v8f-s5-level { regulator-name = "pm_v8f_s5_level"; qcom,set = ; regulator-min-microvolt = @@ -556,7 +575,7 @@ proxy-supply = <&VDD_MMCX_LEVEL>; VDD_MMCX_LEVEL: VDD_MM_LEVEL: S2F_LEVEL: - pm_v8f_s2_level: regulator-pm-v8f-s2-level { + pm_v8f_s2_level: vreg-pm-v8f-s2-level { regulator-name = "pm_v8f_s2_level"; qcom,set = ; regulator-min-microvolt = @@ -572,7 +591,7 @@ }; VDD_MMCX_LEVEL_AO: VDD_MM_LEVEL_AO: S2F_LEVEL_AO: - pm_v8f_s2_level_ao: regulator-pm-v8f-s2-level-ao { + pm_v8f_s2_level_ao: vreg-pm-v8f-s2-level-ao { regulator-name = "pm_v8f_s2_level_ao"; qcom,set = ; regulator-min-microvolt = @@ -583,7 +602,7 @@ ; }; - regulator-pm-v8f-s2-level-so { + vreg-pm-v8f-s2-level-so { regulator-name = "pm_v8i_s2_level_so"; qcom,set = ; regulator-min-microvolt = @@ -602,7 +621,7 @@ VDD_MXC_LEVEL: S2D_LEVEL: - pm_v6d_s2_level: regulator-pm_v6d-s2-level { + pm_v6d_s2_level: vreg-pm_v6d-s2-level { regulator-name = "pm_v6d_s2_level"; qcom,set = ; regulator-min-microvolt = @@ -618,7 +637,7 @@ VDD_MXC_LEVEL_AO: S2D_LEVEL_AO: - pm_v6d_s2_level_ao: regulator-pm_v6d-s2-level-ao { + pm_v6d_s2_level_ao: vreg-pm_v6d-s2-level-ao { regulator-name = "pm_v6d_s2_level_ao"; qcom,set = ; regulator-min-microvolt = @@ -629,7 +648,7 @@ }; VDD_MXC_MMCX_VOTER_LEVEL: VDD_MXC_MM_VOTER_LEVEL: - VDD_MM_MXC_VOTER_LEVEL: regulator-pm_v6d-s2-mmcx-voter-level { + VDD_MM_MXC_VOTER_LEVEL: vreg-pm_v6d-s2-mmcx-voter-level { regulator-name = "pm_v6d_s2_mmcx_voter_level"; pm_v6d_s2_mmcx_voter_level-parent-supply = <&VDD_MMCX_LEVEL>; @@ -643,7 +662,7 @@ }; VDD_MXC_GFX_VOTER_LEVEL: VDD_GFX_MXC_VOTER_LEVEL: - regulator-pm_v6d-s2-gfx-voter-level { + vreg-pm_v6d-s2-gfx-voter-level { regulator-name = "pm_v6d_s2_gfx_voter_level"; pm_v6d_s2_gfx_voter_level-parent-supply = <&VDD_GFX_LEVEL>; qcom,set = ; @@ -659,8 +678,8 @@ rpmh-regulator-smpd3 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpd3"; - S3D: - pm_v6d_s3: regulator-pm_v6d-s3 { + + S3D: pm_v6d_s3: vreg-pm_v6d-s3 { regulator-name = "pm_v6d_s3"; qcom,set = ; regulator-min-microvolt = <870000>; @@ -675,10 +694,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1D: - pm_v6d_l1: regulator-pm_v6d-l1 { + + L1D: pm_v6d_l1: vreg-pm_v6d-l1 { regulator-name = "pm_v6d_l1"; qcom,set = ; regulator-min-microvolt = <1710000>; @@ -691,9 +710,10 @@ rpmh-regulator-lmxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "lmx.lvl"; + VDD_LPI_MX_LEVEL: L2D_LEVEL: - pm_v6d_l2_level: regulator-pm_v6d-l2-level { + pm_v6d_l2_level: vreg-pm_v6d-l2-level { regulator-name = "pm_v6d_l2_level"; qcom,set = ; regulator-min-microvolt = @@ -710,16 +730,19 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L3D: - pm_v6d_l3: regulator-pm_v6d-l3 { + proxy-supply = <&L3D>; + + L3D: pm_v6d_l3: vreg-pm_v6d-l3 { regulator-name = "pm_v6d_l3"; qcom,set = ; regulator-min-microvolt = <1030000>; regulator-max-microvolt = <1100000>; qcom,init-voltage = <1060000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <220000>; }; }; @@ -730,7 +753,7 @@ VDD_CX_LEVEL: S1F_LEVEL: - pm_v8f_s1_level: regulator-pm_v8f-s1-level { + pm_v8f_s1_level: vreg-pm_v8f-s1-level { regulator-name = "pm_v8f_s1_level"; qcom,set = ; regulator-min-microvolt = @@ -746,7 +769,7 @@ VDD_CX_LEVEL_AO: S1F_LEVEL_AO: - pm_v8f_s1_level_ao: regulator-pm_v8f-s1-level-ao { + pm_v8f_s1_level_ao: vreg-pm_v8f-s1-level-ao { regulator-name = "pm_v8f_s1_level_ao"; qcom,set = ; regulator-min-microvolt = @@ -760,8 +783,8 @@ rpmh-regulator-smpf4 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpf4"; - S4F: - pm_v8f_s4: regulator-pm_v8f-s4 { + + S4F: pm_v8f_s4: vreg-pm_v8f-s4 { regulator-name = "pm_v8f_s4"; qcom,set = ; regulator-min-microvolt = <300000>; @@ -778,7 +801,7 @@ VDD_MX_LEVEL: VDD_MXA_LEVEL: S8F_LEVEL: - pm_v8f_s8_level: regulator-pm_v8f-s8-level { + pm_v8f_s8_level: vreg-pm_v8f-s8-level { regulator-name = "pm_v8f_s8_level"; qcom,set = ; regulator-min-microvolt = @@ -794,7 +817,7 @@ VDD_MXA_LEVEL_AO: S8F_LEVEL_AO: - pm_v8f_s8_level_ao: regulator-pm_v8f-s8-level-ao { + pm_v8f_s8_level_ao: vreg-pm_v8f-s8-level-ao { regulator-name = "pm_v8f_s8_level_ao"; qcom,set = ; regulator-min-microvolt = @@ -811,10 +834,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1F: - pm_v8f_l1: regulator-pm_v8f-l1 { + + L1F: pm_v8f_l1: vreg-pm_v8f-l1 { regulator-name = "pm_v8f_l1"; qcom,set = ; regulator-min-microvolt = <866000>; @@ -827,9 +850,10 @@ rpmh-regulator-lcxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "lcx.lvl"; + VDD_LPI_CX_LEVEL: L2F_LEVEL: - pm_v8f_l2_level: regulator-pm_v8-l2-level { + pm_v8f_l2_level: vreg-pm_v8-l2-level { regulator-name = "pm_v8f_l2_level"; qcom,set = ; regulator-min-microvolt = @@ -846,11 +870,11 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; proxy-supply = <&L3F>; - L3F: - pm_v8f_l3: regulator-pm_v8f-l3 { + + L3F: pm_v8f_l3: vreg-pm_v8f-l3 { regulator-name = "pm_v8f_l3"; qcom,set = ; regulator-min-microvolt = <1200000>; @@ -862,24 +886,11 @@ }; }; - rpmh-regulator-smpg1 { - compatible = "qcom,rpmh-vrm-regulator"; - qcom,resource-name = "smpg1"; - S1G: - pm_v6g_s1: regulator-pm_v6g-s1 { - regulator-name = "pm_v6g_s1"; - qcom,set = ; - regulator-min-microvolt = <2156000>; - regulator-max-microvolt = <2400000>; - qcom,init-voltage = <2200000>; - }; - }; - rpmh-regulator-smpg2 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpg2"; - S2G: - pm_v6g_s2: regulator-pm_v6g-s2 { + + S2G: pm_v6g_s2: vreg-pm_v6g-s2 { regulator-name = "pm_v6g_s2"; qcom,set = ; regulator-min-microvolt = <1010000>; @@ -891,9 +902,10 @@ rpmh-regulator-ebilvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "ebi.lvl"; + VDD_EBI_LEVEL: S3G_LEVEL: - pm_v6g_s3_level: regulator-pm_v6g-s3-level { + pm_v6g_s3_level: vreg-pm_v6g-s3-level { regulator-name = "pm_v6g_s3_level"; qcom,set = ; regulator-min-microvolt = @@ -904,16 +916,29 @@ }; }; + rpmh-regulator-smpg1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpg1"; + + S1G: pm_v6g_s1: vreg-pm_v6g-s1 { + regulator-name = "pm_v6g_s1"; + qcom,set = ; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2400000>; + qcom,init-voltage = <2200000>; + }; + }; + rpmh-regulator-ldog1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldog1"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1G: - pm_v6g_l1: regulator-pm_v6g-l1 { + + L1G: pm_v6g_l1: vreg-pm_v6g-l1 { regulator-name = "pm_v6g_l1"; qcom,set = ; regulator-min-microvolt = <1600000>; @@ -929,16 +954,17 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L2G: - pm_v6g_l2: regulator-pm_v6g-l2 { + + L2G: pm_v6g_l2: vreg-pm_v6g-l2 { regulator-name = "pm_v6g_l2"; qcom,set = ; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; qcom,init-voltage = <1200000>; qcom,init-mode = ; + regulator-always-on; }; }; @@ -948,10 +974,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L3G: - pm_v6g_l3: regulator-pm_v6g-l3 { + + L3G: pm_v6g_l3: vreg-pm_v6g-l3 { regulator-name = "pm_v6g_l3"; qcom,set = ; regulator-min-microvolt = <1800000>; @@ -964,12 +990,12 @@ rpmh-regulator-smpi1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpi1"; - S1I: - pmg1110i_s1: regulator-pmg1110i-s1 { + + S1I: pmg1110i_s1: vreg-pmg1110i-s1 { regulator-name = "pmg1110i_s1"; qcom,set = ; regulator-min-microvolt = <352000>; - regulator-max-microvolt = <1050000>; + regulator-max-microvolt = <952000>; qcom,init-voltage = <892000>; }; }; @@ -977,8 +1003,8 @@ rpmh-regulator-smpj1 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "smpj1"; - S1J: - pmg1110j_s1: regulator-pmg1110j-s1 { + + S1J: pmg1110j_s1: vreg-pmg1110j-s1 { regulator-name = "pmg1110j_s1"; qcom,set = ; regulator-min-microvolt = <504000>; @@ -993,10 +1019,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1K: - pmr_nalojr_l1: regulator-pmr-nalojr-l1 { + + L1K: pmr_nalojr_l1: vreg-pmr-nalojr-l1 { regulator-name = "pmr_nalojr_l1"; qcom,set = ; regulator-min-microvolt = <488000>; @@ -1012,10 +1038,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L2K: - pmr_nalojr_l2: regulator-pmr_nalojr_l2 { + + L2K: pmr_nalojr_l2: vreg-pmr_nalojr_l2 { regulator-name = "pmr_nalojr_l2"; qcom,set = ; regulator-min-microvolt = <920000>; @@ -1031,10 +1057,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L3K: - pmr_nalojr_l3: regulator-pmr_nalojr_l3 { + + L3K: pmr_nalojr_l3: vreg-pmr_nalojr_l3 { regulator-name = "pmr_nalojr_l3"; qcom,set = ; regulator-min-microvolt = <1080000>; @@ -1050,10 +1076,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L4K: - pmr_nalojr_l4: regulator-pmr_nalojr_l4 { + + L4K: pmr_nalojr_l4: vreg-pmr_nalojr_l4 { regulator-name = "pmr_nalojr_l4"; qcom,set = ; regulator-min-microvolt = <1200000>; @@ -1069,10 +1095,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L5K: - pmr_nalojr_l5: regulator-pmr_nalojr_l5 { + + L5K: pmr_nalojr_l5: vreg-pmr_nalojr_l5 { regulator-name = "pmr_nalojr_l5"; qcom,set = ; regulator-min-microvolt = <504000>; @@ -1088,10 +1114,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L6K: - pmr_nalojr_l6: regulator-pmr_nalojr_l6 { + + L6K: pmr_nalojr_l6: vreg-pmr_nalojr_l6 { regulator-name = "pmr_nalojr_l6"; qcom,set = ; regulator-min-microvolt = <1100000>; @@ -1107,10 +1133,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L7K: - pmr_nalojr_l7: regulator-pmr_nalojr_l7 { + + L7K: pmr_nalojr_l7: vreg-pmr_nalojr_l7 { regulator-name = "pmr_nalojr_l7"; qcom,set = ; regulator-min-microvolt = <504000>; @@ -1126,10 +1152,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1M: - pm8010m_l1: regulator-pm8010m-l1 { + + L1M: pm8010m_l1: vreg-pm8010m-l1 { regulator-name = "pm8010m_l1"; qcom,set = ; regulator-min-microvolt = <1000000>; @@ -1145,10 +1171,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L2M: - pm8010m_l2: regulator-pm8010m-l2 { + + L2M: pm8010m_l2: vreg-pm8010m-l2 { regulator-name = "pm8010m_l2"; qcom,set = ; regulator-min-microvolt = <950000>; @@ -1163,7 +1189,7 @@ qcom,resource-name = "ldom3"; L3M: - pm8010m_l3: regulator-pm8010m-l3 { + pm8010m_l3: vreg-pm8010m-l3 { regulator-name = "pm8010m_l3"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -1177,7 +1203,7 @@ qcom,resource-name = "ldom4"; L4M: - pm8010m_l4: regulator-pm8010m-l4 { + pm8010m_l4: vreg-pm8010m-l4 { regulator-name = "pm8010m_l4"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -1189,14 +1215,16 @@ rpmh-regulator-ldom5 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldom5"; + status = "disabled"; L5M: - pm8010m_l5: regulator-pm8010m-l5 { + pm8010m_l5: vreg-pm8010m-l5 { regulator-name = "pm8010m_l5"; qcom,set = ; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; qcom,init-voltage = <1200000>; + status = "disabled"; }; }; @@ -1205,7 +1233,7 @@ qcom,resource-name = "ldom6"; L6M: - pm8010m_l6: regulator-pm8010m-l6 { + pm8010m_l6: vreg-pm8010m-l6 { regulator-name = "pm8010m_l6"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -1219,7 +1247,7 @@ qcom,resource-name = "ldom7"; L7M: - pm8010m_l7: regulator-pm8010m-l7 { + pm8010m_l7: vreg-pm8010m-l7 { regulator-name = "pm8010m_l7"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -1234,10 +1262,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L1N: - pm8010n_l1: regulator-pm8010n-l1 { + + L1N: pm8010n_l1: vreg-pm8010n-l1 { regulator-name = "pm8010n_l1"; qcom,set = ; regulator-min-microvolt = <1050000>; @@ -1253,10 +1281,10 @@ qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = ; + RPMH_REGULATOR_MODE_HPM>; qcom,mode-threshold-currents = <0 30000>; - L2N: - pm8010n_l2: regulator-pm8010n-l2 { + + L2N: pm8010n_l2: vreg-pm8010n-l2 { regulator-name = "pm8010n_l2"; qcom,set = ; regulator-min-microvolt = <1050000>; @@ -1270,8 +1298,7 @@ compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldon3"; - L3N: - pm8010n_l3: regulator-pm8010n-l3 { + L3N: pm8010n_l3: vreg-pm8010n-l3 { regulator-name = "pm8010n_l3"; qcom,set = ; regulator-min-microvolt = <1792000>; @@ -1283,14 +1310,15 @@ rpmh-regulator-ldon4 { compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldon4"; + status = "disabled"; - L4N: - pm8010n_l4: regulator-pm8010n-l4 { + L4N: pm8010n_l4: vreg-pm8010n-l4 { regulator-name = "pm8010n_l4"; qcom,set = ; regulator-min-microvolt = <1792000>; regulator-max-microvolt = <3312000>; qcom,init-voltage = <1800000>; + status = "disabled"; }; }; @@ -1298,8 +1326,7 @@ compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldon5"; - L5N: - pm8010n_l5: regulator-pm8010n-l5 { + L5N: pm8010n_l5: vreg-pm8010n-l5 { regulator-name = "pm8010n_l5"; qcom,set = ; regulator-min-microvolt = <1504000>; @@ -1312,8 +1339,7 @@ compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldon6"; - L6N: - pm8010n_l6: regulator-pm8010n-l6 { + L6N: pm8010n_l6: vreg-pm8010n-l6 { regulator-name = "pm8010n_l6"; qcom,set = ; regulator-min-microvolt = <2700000>; @@ -1326,8 +1352,7 @@ compatible = "qcom,rpmh-vrm-regulator"; qcom,resource-name = "ldon7"; - L7N: - pm8010n_l7: regulator-pm8010n-l7 { + L7N: pm8010n_l7: vreg-pm8010n-l7 { regulator-name = "pm8010n_l7"; qcom,set = ; regulator-min-microvolt = <3130000>; diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi index 8a68886a..3ee901c5 100644 --- a/qcom/tuna-reserved-memory.dtsi +++ b/qcom/tuna-reserved-memory.dtsi @@ -117,6 +117,12 @@ reg = <0x0 0x82700000 0x0 0x100000>; }; + qdss_apps_mem: qdss_apps_region@82800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + dsm_partition_1_mem: dsm_partition_1_region@84a00000 { no-map; reg = <0x0 0x84a00000 0x0 0x3700000>; diff --git a/qcom/tuna-thermal-overlay.dtsi b/qcom/tuna-thermal-overlay.dtsi index 4d2ebf83..c0f874df 100644 --- a/qcom/tuna-thermal-overlay.dtsi +++ b/qcom/tuna-thermal-overlay.dtsi @@ -25,100 +25,6 @@ }; }; - pmih010x-bcl-lvl0 { - cooling-maps { - lbat_modem0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&modem_bcl 1 1>; - }; - - lbat_gpu0 { - trip = <&b_bcl_lvl0>; - cooling-device = <&msm_gpu 1 1>; - }; - }; - }; - - pmih010x-bcl-lvl1 { - cooling-maps { - lbat_modem1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&modem_bcl 2 2>; - }; - - lbat_gpu1 { - trip = <&b_bcl_lvl1>; - cooling-device = <&msm_gpu 2 2>; - }; - }; - }; - - pmih010x-bcl-lvl2 { - cooling-maps { - lbat_gpu2 { - trip = <&b_bcl_lvl2>; - cooling-device = <&msm_gpu 3 3>; - }; - }; - }; - - pm7550ba-bcl-lvl0 { - cooling-maps { - vph_0_nr_scg { - trip = <&bcl_lvl0>; - cooling-device = <&modem_nr_scg_dsc 3 3>; - }; - - vph_0_nr { - trip = <&bcl_lvl0>; - cooling-device = <&modem_nr_dsc 6 6>; - }; - - vph_0_mdm_lte { - trip = <&bcl_lvl0>; - cooling-device = <&modem_lte_dsc 8 8>; - }; - - vph_gpu0 { - trip = <&bcl_lvl0>; - cooling-device = <&msm_gpu 2 2>; - }; - }; - }; - - pm7550ba-bcl-lvl1 { - cooling-maps { - vph_1_nr_scg { - trip = <&bcl_lvl1>; - cooling-device = <&modem_nr_scg_dsc 10 10>; - }; - - vph_1_nr { - trip = <&bcl_lvl1>; - cooling-device = <&modem_nr_dsc 9 9>; - }; - - vph_1_mdm_lte { - trip = <&bcl_lvl1>; - cooling-device = <&modem_lte_dsc 10 10>; - }; - - vph_gpu1 { - trip = <&bcl_lvl1>; - cooling-device = <&msm_gpu 3 3>; - }; - }; - }; - - pm7550ba-bcl-lvl2 { - cooling-maps { - vph_gpu2 { - trip = <&bcl_lvl2>; - cooling-device = <&msm_gpu 7 7>; - }; - }; - }; - pmxr2230-bcl-lvl0 { cooling-maps { lbat_0_nr_scg { diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index c17dc0f9..387e9109 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -89,6 +89,7 @@ snps,dis_u2_susphy_quirk; snps,ssp-u3-u0-quirk; tx-fifo-resize; + num-hc-interrupters = /bits/ 16 <3>; dr_mode = "otg"; maximum-speed = "super-speed-plus"; usb-role-switch; @@ -127,6 +128,10 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; + + /* eUSB2 HPG version 1.0.2 update */ + qcom,param-override-seq = + <0x00 0x58>; }; usb_nop_phy: usb_nop_phy { diff --git a/qcom/tuna-vm-cdp.dtsi b/qcom/tuna-vm-cdp.dtsi index 1510613d..2c79ca42 100644 --- a/qcom/tuna-vm-cdp.dtsi +++ b/qcom/tuna-vm-cdp.dtsi @@ -5,3 +5,25 @@ &soc { }; + +&qupv3_se4_i2c { + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + st,irq-flags = <8>; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + }; +}; diff --git a/qcom/tuna-vm-dma-heaps.dtsi b/qcom/tuna-vm-dma-heaps.dtsi index 575b2573..b5cc90c3 100644 --- a/qcom/tuna-vm-dma-heaps.dtsi +++ b/qcom/tuna-vm-dma-heaps.dtsi @@ -38,5 +38,35 @@ qcom,dma-heap-type = ; qcom,dynamic-heap; }; + + qcom,ms4 { + qcom,dma-heap-name = "qcom,ms4"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms5 { + qcom,dma-heap-name = "qcom,ms5"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms6 { + qcom,dma-heap-name = "qcom,ms6"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,ms7 { + qcom,dma-heap-name = "qcom,ms7"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,tui_test { + qcom,dma-heap-name = "qcom,tui_test"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; }; }; diff --git a/qcom/tuna-vm-mtp.dtsi b/qcom/tuna-vm-mtp.dtsi index 1510613d..2c79ca42 100644 --- a/qcom/tuna-vm-mtp.dtsi +++ b/qcom/tuna-vm-mtp.dtsi @@ -5,3 +5,25 @@ &soc { }; + +&qupv3_se4_i2c { + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + st,irq-flags = <8>; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + }; +}; diff --git a/qcom/tuna-vm-rcm.dtsi b/qcom/tuna-vm-rcm.dtsi index 1510613d..2c79ca42 100644 --- a/qcom/tuna-vm-rcm.dtsi +++ b/qcom/tuna-vm-rcm.dtsi @@ -5,3 +5,25 @@ &soc { }; + +&qupv3_se4_i2c { + status = "ok"; + qcom,touch-active = "st,fts"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + st,irq-flags = <8>; + + st,touch-type = "primary"; + st,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <658>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 16 0 &tlmm 17 0 &tlmm 18 0 + &tlmm 19 0 &tlmm 189 0 &tlmm 176 0x2008>; + }; +}; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 0be182a4..93fd4c0c 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -290,6 +290,26 @@ peer-default; }; + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x3>; + allocate-base; + }; + }; + + msgqsock-msgq { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/msgqsock-msgq-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + peer = "vm-name:qcom,oemvm"; + qcom,label = <0x3>; + }; + }; }; @@ -430,10 +450,20 @@ qcom,support-hypervisor; }; + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <3>; + }; + qti,smmu-proxy { compatible = "smmu-proxy-receiver"; }; + qmsgq-gunyah { + compatible = "qcom,qmsgq-gh"; + msgq-label = <3>; + }; + qti,smmu-proxy-camera-cb { compatible = "smmu-proxy-cb"; qti,cb-id = ; @@ -534,6 +564,7 @@ reg-names = "gpi-top"; iommus = <&apps_smmu 0xb8 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; interrupts = , , @@ -567,6 +598,7 @@ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; iommus = <&apps_smmu 0xb8 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; ranges; status = "ok"; @@ -608,6 +640,7 @@ reg-names = "gpi-top"; iommus = <&apps_smmu 0x438 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; interrupts = , , @@ -641,6 +674,7 @@ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x438 0x0>; qcom,iommu-group = <&qup_iommu_group>; + memory-region = <&qup_iommu_group>; dma-coherent; ranges; status = "ok"; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 012fbe39..985a044a 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -37,26 +37,6 @@ reg = <0 0 0 0>; }; - chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket"; - stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; - }; - - reserved_memory: reserved-memory {}; - - ddr-regions { }; - - mem-offline { - compatible = "qcom,mem-offline"; - offline-sizes = <0x2 0xc0000000 0x1 0x0>; - granule = <512>; - qcom,qmp = <&aoss_qmp>; - }; - - firmware: firmware { - qcom_scm: qcom_scm {}; - }; - aliases: aliases { serial0 = &qupv3_se7_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ @@ -90,6 +70,27 @@ spi15 = &qupv3_se15_spi; }; + chosen: chosen { + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket"; + stdout-path = "serial0:115200n8"; + }; + + reserved_memory: reserved-memory {}; + + ddr-regions { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x0>; + granule = <512>; + qcom,qmp = <&aoss_qmp>; + status = "disabled"; + }; + + firmware: firmware { + qcom_scm: qcom_scm {}; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -154,7 +155,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_2>; - capacity-dmips-mhz = <1035>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_2: l2-cache { compatible = "cache"; @@ -175,7 +176,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_3>; - capacity-dmips-mhz = <1035>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_3: l2-cache { compatible = "cache"; @@ -196,7 +197,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_4>; - capacity-dmips-mhz = <1035>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_4: l2-cache { compatible = "cache"; @@ -217,7 +218,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_5>; - capacity-dmips-mhz = <1035>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_5: l2-cache { compatible = "cache"; @@ -238,7 +239,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_6>; - capacity-dmips-mhz = <1035>; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <121>; L2_6: l2-cache { compatible = "cache"; @@ -259,7 +260,7 @@ #cooling-cells = <2>; cpu-release-addr = <0x0 0xE3940000>; next-level-cache = <&L2_7>; - capacity-dmips-mhz = <1178>; + capacity-dmips-mhz = <1157>; dynamic-power-coefficient = <295>; L2_7: l2-cache { compatible = "cache"; @@ -432,7 +433,6 @@ #include "tuna-reserved-memory.dtsi" #include "msm-arm-smmu-tuna.dtsi" #include "tuna-dma-heaps.dtsi" -#include "tuna-vm-dma-heaps.dtsi" #include "tuna-pcie.dtsi" &reserved_memory { @@ -649,7 +649,7 @@ }; }; - cache-controller@24800000 { + llcc: cache-controller@24800000 { compatible = "qcom,tuna-llcc"; reg = <0x24800000 0x200000>, <0x25800000 0x200000>, <0x24C00000 0x200000>, <0x25C00000 0x200000>, @@ -771,6 +771,11 @@ , ; }; + + cam_bcm_voter0: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; }; cam_rsc_drv1: drv@1 { @@ -792,6 +797,11 @@ , ; }; + + cam_bcm_voter1: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; }; cam_rsc_drv2: drv@2 { @@ -813,6 +823,11 @@ , ; }; + + cam_bcm_voter2: bcm_voter { + compatible = "qcom,bcm-voter"; + qcom,no-amc; + }; }; }; @@ -1219,7 +1234,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; - qcom,gpios-reserved = <54 4 5 6 7 82 83 111 112>; + qcom,gpios-reserved = <54 4 5 6 7 82 83>; }; tlmm-vm-mem-access { @@ -1594,6 +1609,20 @@ }; + qcom,qrtr-mhi-cnss { + compatible = "qcom,qrtr-mhi"; + qcom,dev-id = <0x1103>; + qcom,net-id = <0>; + qcom,low-latency; + }; + + qcom,qrtr-mhi-cnss { + compatible = "qcom,qrtr-mhi"; + qcom,dev-id = <0x1107>; + qcom,net-id = <1>; + qcom,low-latency; + }; + qfprom: qfprom@221c8000 { compatible = "qcom,tuna-qfprom", "qcom,qfprom"; reg = <0x221c8000 0x1000>; @@ -1605,6 +1634,11 @@ reg = <0x0118 0x4>; }; + gpu_speed_bin: gpu_speed_bin@138 { + reg = <0x138 0x2>; + bits = <0 9>; + }; + feat_conf18: feat_conf18@0148 { reg = <0x0148 0x4>; }; @@ -2011,18 +2045,99 @@ compatible = "smmu-proxy-sender"; }; + pcie_crm_hw_0_bcm_voter: bcm_voter@0 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "pcie_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <5>; + }; + + disp_crm_hw_0_bcm_voter: bcm_voter@1 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_1_bcm_voter: bcm_voter@2 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <1>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_2_bcm_voter: bcm_voter@3 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <2>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_3_bcm_voter: bcm_voter@4 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <3>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_4_bcm_voter: bcm_voter@5 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <4>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_hw_5_bcm_voter: bcm_voter@6 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-client-idx = <5>; + qcom,crm-pwr-states = <2>; + }; + + disp_crm_sw_0_bcm_voter: bcm_voter@7 { + compatible = "qcom,bcm-voter"; + qcom,crm-name = "disp_crm"; + qcom,crm-sw-client; + qcom,crm-client-idx = <0>; + qcom,crm-pwr-states = <1>; + }; + clk_virt: interconnect@0 { compatible = "qcom,tuna-clk_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; }; mc_virt: interconnect@1 { compatible = "qcom,tuna-mc_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "cam_ife_0", + "cam_ife_1", + "cam_ife_2", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; }; config_noc: interconnect@1600000 { @@ -2056,8 +2171,10 @@ compatible = "qcom,tuna-pcie_anoc"; reg = <0x16c0000 0x11400>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "pcie_crm_hw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&pcie_crm_hw_0_bcm_voter>; qcom,skip-qos; }; @@ -2083,8 +2200,28 @@ compatible = "qcom,tuna-mmss_noc"; reg = <0x1780000 0x7d800>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "cam_ife_0", + "cam_ife_1", + "cam_ife_2", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; qcom,skip-qos; }; @@ -2092,8 +2229,30 @@ compatible = "qcom,tuna-gem_noc"; reg = <0x24100000 0x14d080>; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; + qcom,bcm-voter-names = "hlos", + "cam_ife_0", + "cam_ife_1", + "cam_ife_2", + "pcie_crm_hw_0", + "disp_crm_hw_0", + "disp_crm_hw_1", + "disp_crm_hw_2", + "disp_crm_hw_3", + "disp_crm_hw_4", + "disp_crm_hw_5", + "disp_crm_sw_0"; + qcom,bcm-voters = <&apps_bcm_voter>, + <&cam_bcm_voter0>, + <&cam_bcm_voter1>, + <&cam_bcm_voter2>, + <&pcie_crm_hw_0_bcm_voter>, + <&disp_crm_hw_0_bcm_voter>, + <&disp_crm_hw_1_bcm_voter>, + <&disp_crm_hw_2_bcm_voter>, + <&disp_crm_hw_3_bcm_voter>, + <&disp_crm_hw_4_bcm_voter>, + <&disp_crm_hw_5_bcm_voter>, + <&disp_crm_sw_0_bcm_voter>; qcom,skip-qos; }; @@ -2271,8 +2430,10 @@ ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, - <0x1d88000 0x18000>; - reg-names = "ufs_mem", "ice"; + <0x1d88000 0x18000>, + <0x1da5000 0x2000>, + <0x1da4000 0x10>; + reg-names = "ufs_mem", "ice", "mcq_sqd", "mcq_vs"; interrupts = ; phys = <&ufsphy_mem>; @@ -2280,6 +2441,9 @@ #reset-cells = <1>; qcom,ice-use-hwkm; + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x0f>; + qcom,esi-affinity-mask = <1 1 4 4 3 6 6 7>; lanes-per-direction = <2>; clock-names = @@ -2321,7 +2485,8 @@ depends-on-supply = <&apps_smmu>; iommus = <&apps_smmu 0x60 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; + qcom,iommu-msi-size = <0x1000>; memory-region = <&ufshc_dma_resv>; shared-ice-cfg = <&ice_cfg>; dma-coherent; @@ -2329,6 +2494,8 @@ qcom,bypass-pbl-rst-wa; qcom,max-cpus = <8>; + msi-parent = <&gic_its 0x60>; + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -2489,14 +2656,6 @@ qcom,can-sleep; }; - pmd802x@4 { - compatible = "qcom,spmi-pmic"; - reg = <4 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - qcom,can-sleep; - }; - pm8550ve@5 { compatible = "qcom,spmi-pmic"; reg = <5 SPMI_USID>; @@ -2519,6 +2678,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,can-sleep; + status = "disabled"; }; pmg1110@9 { @@ -2527,6 +2687,7 @@ #address-cells = <2>; #size-cells = <0>; qcom,can-sleep; + status = "disabled"; }; pmr735d@a { @@ -2702,6 +2863,13 @@ ext-label = <0x7>; }; + qcom,qrtr-gunyah-tuivm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <3>; + peer-name = <2>; + }; + qcom,pmic_glink_log { compatible = "qcom,qti-pmic-glink"; qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; @@ -2846,6 +3014,44 @@ compatible = "qcom,cpufreq-stats-v2"; }; + qcom_mpam: qcom,mpam { + compatible = "qcom,mpam"; + }; + + cpu_mpam: qcom,cpu_mpam { + compatible = "qcom,cpu-mpam"; + + L3 { + qcom,msc-id = <0>; + qcom,msc-name = "L3"; + }; + }; + + noc_bw_mpam: qcom,noc_bw_mpam { + compatible = "qcom,platform-mpam"; + reg = <0x17D2E800 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <3>; + qcom,msc-name = "noc_bw"; + qcom,gears = "low", "medium", "high", "veryhigh"; + qcom,gear-id = <1>, <2>, <3>, <4>; + + cpu { + qcom,client-id = <0x1>; + qcom,client-name = "cpu"; + }; + + gpu { + qcom,client-id = <0x10>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <0x100>; + qcom,client-name = "nsp"; + }; + }; + llcc_pmu: llcc-pmu@24095000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x24095000 0x300>; @@ -3218,6 +3424,58 @@ qcom,count-unit = <0x10000>; qcom,target-dev = <&qcom_ddr_dcvs_hw>; }; + + qcom-mpam-msc { + compatible = "qcom,mpam-msc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + qcom-slc-mpam@17D2EC00 { + compatible = "qcom,slc-mpam"; + reg = <0x17D2EC00 0x400>; + reg-names = "mon-base"; + qcom,msc-id = <2>; + qcom,msc-name = "slc"; + qcom,dev-index = <0>; + qcom,num-read-miss-cfg = <2>; + qcom,num-cap-cfg = <5>; + qcom,slc-clients = "APPS_CLIENT", "GPU_CLIENT", + "NSP_CLIENT"; + }; + }; + + qcom_slc_mpam: qcom,slc_mpam { + compatible = "qcom,mpam-slc"; + qcom,msc-name = "slc"; + + apps { + qcom,client-id = <0>; + qcom,client-name = "apps"; + + part-id0 { + qcom,part-id = <0>; + }; + + part-id1 { + qcom,part-id = <1>; + }; + + part-id2 { + qcom,part-id = <2>; + }; + }; + + gpu { + qcom,client-id = <1>; + qcom,client-name = "gpu"; + }; + + nsp { + qcom,client-id = <2>; + qcom,client-name = "nsp"; + }; + }; }; #include "tuna-gdsc.dtsi" @@ -3346,20 +3604,6 @@ #size-cells = <2>; ranges; - trust_ui_vm_mem: trust_ui_vm_region@f3800000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf3800000 0x0 0x4400000>; - reusable; - alignment = <0x0 0x400000>; - }; - - oem_vm_mem: oem_vm_region@f7c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0xf7c00000 0x0 0x4c00000>; - reusable; - alignment = <0x0 0x400000>; - }; - vm_comm_mem: vm_comm_mem_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; diff --git a/qcom/tuna7.dtsi b/qcom/tuna7.dtsi index 38eb356c..84e58645 100644 --- a/qcom/tuna7.dtsi +++ b/qcom/tuna7.dtsi @@ -14,3 +14,7 @@ &adsp_pas { firmware-name = "adsp2.mdt", "adsp2_dtb.mdt"; }; + +&llcc { + compatible = "qcom,tuna7-llcc"; +}; diff --git a/qcom/tunap.dts b/qcom/tunap.dts new file mode 100644 index 00000000..d31edb8c --- /dev/null +++ b/qcom/tunap.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "tunap.dtsi" +/ { + model = "Qualcomm Technologies, Inc. TunaP SoC"; + compatible = "qcom,tunap"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/tunap.dtsi b/qcom/tunap.dtsi new file mode 100644 index 00000000..beeb0ae8 --- /dev/null +++ b/qcom/tunap.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna.dtsi" +/ { + model = "Qualcomm Technologies, Inc. TunaP SoC"; + compatible = "qcom,tunap"; + qcom,msm-id = <694 0x10000>; +};