From f3bd05ce440dadc918d5f84ed795b20869497518 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Tue, 26 Dec 2023 12:46:49 +0530 Subject: [PATCH] ARM: dts: msm: Add CRMV regs disp, camera and pcie on sun CRMV regs have status captured for various commands/voltage levels. Map CRMV registers in device so that driver can dump them when required. Change-Id: I05911a0646b2317f90fd425e172d0458ce669ab0 Signed-off-by: Minghao Zhang --- qcom/sun.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 4c9ccc0e..1b9ece30 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1294,8 +1294,9 @@ disp_crm: crm@af21000 { label = "disp_crm"; compatible = "qcom,disp-crm-v2"; - reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>, <0xaf29f00 0x100>; - reg-names = "base", "crm_b", "crm_c", "common"; + reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27800 0x2000>, + <0xaf29800 0x700>, <0xaf29f00 0x100>; + reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; interrupts = ; interrupt-names = "disp_crm_drv0"; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; @@ -1306,8 +1307,9 @@ cam_crm: crm@adcb000 { label = "cam_crm"; compatible = "qcom,cam-crm-v2"; - reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>, <0xadcfd00 0x100>; - reg-names = "base", "crm_b", "crm_c", "common"; + reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd600 0x2000>, + <0xadcf600 0x700>, <0xadcfd00 0x100>; + reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; interrupts = ; interrupt-names = "cam_crm_drv0"; clocks = <&camcc CAM_CC_DRV_AHB_CLK>; @@ -1318,8 +1320,9 @@ pcie_crm: crm@1d01000 { label = "pcie_crm"; compatible = "qcom,pcie-crm-v2"; - reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>, <0x1d05f00 0x100>; - reg-names = "base", "crm_b", "crm_c", "common"; + reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03800 0x2000>, + <0x1d05800 0x700>, <0x1d05f00 0x100>; + reg-names = "base", "crm_b", "crm_c", "crm_v", "common"; interrupts = ; interrupt-names = "pcie_crm_drv0"; clocks = <&pcie_0_pipe_clk>;