ARM: dts: msm: Add ipa_hw support for ravelin

Enable IPA HW Accelerator block on ravelin.

Change-Id: I8c66461037435d4040c3ec568c5942e03b0aecb5
Signed-off-by: Pavan Kumar M <quic_rpavan@quicinc.com>
This commit is contained in:
Pavan Kumar M
2024-07-01 20:23:34 +05:30
parent 33bdb6d2d1
commit 9e7f0f2556
3 changed files with 85 additions and 0 deletions

4
Kbuild
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@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_MONACO),y)
dtbo-y += monaco-ipa.dtbo
endif
ifeq ($(CONFIG_ARCH_RAVELIN),y)
dtbo-y += ravelin-ipa.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

20
ravelin-ipa.dts Normal file
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@@ -0,0 +1,20 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/interconnect/qcom,ravelin.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include "ravelin-ipa.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Ravelin";
compatible = "qcom,ravelin";
qcom,msm-id = <568 0x10000>, <581 0x10000>, <653 0x10000>;
qcom,board-id = <0 0>;
};

61
ravelin-ipa.dtsi Normal file
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@@ -0,0 +1,61 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipa.dtsi"
&ipa_hw {
interrupts =
<0 654 IRQ_TYPE_LEVEL_HIGH>,
<0 432 IRQ_TYPE_LEVEL_HIGH>;
qcom,ipa-hw-ver = <23>; /* IPA core version = IPAv5.2 */
qcom,ipa-ulso-wa;
qcom,gfp-no-retry;
/delete-property/ qcom,rmnet-ll-enable;
/delete-property/ qcom,ipa-uc-holb-monitor;
qcom,ipa-gen-rx-cmn-page-pool-sz-factor = <2>;
qcom,ipa-gen-rx-cmn-temp-pool-sz-factor = <1>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<0 0 0 1900000 0 76800>;
/* SVS */
qcom,svs =
<1200000 0 1200000 2800000 0 150000>;
/* NOMINAL */
qcom,nominal =
<2400000 0 2400000 5500000 0 400000>;
/* TURBO */
qcom,turbo =
<3600000 0 3600000 5500000 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
};
&ipa_smmu_wlan {
/delete-property/ dma-coherent;
};
&ipa_smmu_uc {
/delete-property/ dma-coherent;
};
&ipa_smmu_11ad {
iommus = <&apps_smmu 0x4A3 0x0>;
};