From e5d54ea8bd8b330b40a49f4300e20987db5cc23e Mon Sep 17 00:00:00 2001
From: Vijayanand Jitta <quic_vjitta@quicinc.com>
Date: Tue, 22 Oct 2024 14:15:35 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add arm-smmu device on kera-vm

Describe the register, interrupts, and settings of the arm-smmu device.

Change-Id: I7a2be4e5b344a40c42657e5d03f2bc88696f29c1
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
---
 qcom/kera-vm.dtsi              |  2 ++
 qcom/msm-arm-smmu-kera-vm.dtsi | 62 ++++++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-kera-vm.dtsi

diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi
index a40e16dc..ba17e3a3 100644
--- a/qcom/kera-vm.dtsi
+++ b/qcom/kera-vm.dtsi
@@ -244,3 +244,5 @@
 		qcom,support-hypervisor;
 	};
 };
+
+#include "msm-arm-smmu-kera-vm.dtsi"
diff --git a/qcom/msm-arm-smmu-kera-vm.dtsi b/qcom/msm-arm-smmu-kera-vm.dtsi
new file mode 100644
index 00000000..f9dabb87
--- /dev/null
+++ b/qcom/msm-arm-smmu-kera-vm.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	vm-config {
+		vdevices {
+			vsmmu@15000000 {
+				vdevice-type = "vsmmu-v2";
+				smmu-handle = <0x15000000>;
+				num-cbs = <0x7>;
+				num-smrs = <0xe>;
+				patch = "/soc/apps-smmu@15000000";
+			};
+		};
+	};
+};
+
+&soc {
+	apps_smmu: apps-smmu@15000000 {
+		/*
+		 * reg, #global-interrupts & interrupts  properties will
+		 * be added dynamically by bootloader.
+		 */
+		compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		dma-coherent;
+
+		qcom,actlr =
+			/* CAM_HF:Camera */
+			<0x1c08 0x0000 0x00000001>,
+
+			/* Mnoc_HF_23:Display */
+			<0x0804 0x0002 0x00000001>,
+
+			/* NSP:Compute */
+			<0x0c0b 0x0000 0x00000303>,
+
+			/* SF:Camera IPE*/
+			<0x1808 0x0020 0x00000001>,
+
+			/* SF:Camera CDM IPE/IFE/OFE*/
+			<0x1841 0x0000 0x00000001>,
+			<0x1861 0x0000 0x00000001>,
+			<0x1881 0x0000 0x00000001>,
+
+			/* SF:Camera ICP*/
+			<0x18c2 0x0000 0x00000001>,
+			<0x1982 0x0000 0x00000001>,
+
+			/* SF:Camera CRE*/
+			<0x18e8 0x0000 0x00000103>,
+
+			/* SF:EVA */
+			<0x1901 0x0020 0x00000103>,
+			<0x1925 0x0000 0x00000103>;
+	};
+};

From 5d3122681a759747b1604233cea70866e1064d93 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Tue, 22 Oct 2024 14:45:39 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add gcc qcom-dummycc support for TVM on
 Kera

For upstream and tvm, qup common driver uses gcc phandles which
are common in dt and to avoid qup driver probe failure, add gcc
qcom-dummycc support as they are nop. This helps in avoiding
additional logic in qup driver to not conditionalize based on
variant.

Change-Id: I00c3c59116519822be0368511499874951d0d882
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/kera-vm.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi
index ba17e3a3..5ae595f2 100644
--- a/qcom/kera-vm.dtsi
+++ b/qcom/kera-vm.dtsi
@@ -205,6 +205,13 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	gcc: clock-controller@100000 {
+		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
 	virtio-mmio {
 		wakeup-source;
 	};