Merge "ARM: dts: msm: Update Tuna GPU frequency plan"
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@@ -1,19 +1,20 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/* ACD Control register values */
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#define ACD_LEVEL_TURBO_L2 0xa02f5ffd
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#define ACD_LEVEL_TURBO_L1 0xa8285ffd
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#define ACD_LEVEL_TURBO 0x88295ffd
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#define ACD_LEVEL_NOM_L1 0xa8295ffd
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#define ACD_LEVEL_NOM 0x882a5ffd
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#define ACD_LEVEL_SVS_L2 0x882a5ffd
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#define ACD_LEVEL_SVS_L1 0xa82a5ffd
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#define ACD_LEVEL_SVS 0xa82c5ffd
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#define ACD_LEVEL_LOW_SVS 0xc02c5ffd
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#define ACD_LEVEL_LOW_SVS_D1 0xc02c5ffd
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#define ACD_LEVEL_TURBO_L2 0xa8285ffd
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#define ACD_LEVEL_TURBO_L1 0x88295ffd
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#define ACD_LEVEL_TURBO_L0 0x882a5ffd
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#define ACD_LEVEL_TURBO 0x882a5ffd
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#define ACD_LEVEL_NOM_L1 0xa82a5ffd
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#define ACD_LEVEL_NOM 0x882b5ffd
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#define ACD_LEVEL_SVS_L2 0x882b5ffd
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#define ACD_LEVEL_SVS_L1 0xa82b5ffd
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#define ACD_LEVEL_SVS 0xc02c5ffd
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#define ACD_LEVEL_LOW_SVS 0xc8295ffd
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#define ACD_LEVEL_LOW_SVS_D1 0xc8295ffd
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&msm_gpu {
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/* Power levels */
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@@ -31,7 +32,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,initial-pwrlevel = <10>;
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qcom,speed-bin = <0>;
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/* Turbo_L2 */
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@@ -50,7 +51,7 @@
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <1050000000>;
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qcom,gpu-freq = <1100000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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@@ -60,35 +61,48 @@
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qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
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};
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/* Turbo */
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/* Turbo_L0 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <1050000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO_L0>;
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};
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/* Turbo */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <937000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <10>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO>;
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};
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/* Nom_L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <873000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_NOM_L1>;
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};
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/* Nom */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <763000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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@@ -100,8 +114,8 @@
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <688000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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@@ -113,8 +127,8 @@
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <644000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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@@ -126,12 +140,12 @@
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};
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/* SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <510000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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@@ -139,8 +153,8 @@
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <362000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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@@ -152,8 +166,8 @@
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-pwrlevel@10 {
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reg = <10>;
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qcom,gpu-freq = <264000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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@@ -193,7 +207,7 @@
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <10>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO>;
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};
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@@ -204,9 +218,9 @@
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qcom,gpu-freq = <873000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_NOM_L1>;
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};
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@@ -255,7 +269,7 @@
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qcom,gpu-freq = <510000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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@@ -293,7 +307,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,initial-pwrlevel = <9>;
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qcom,initial-pwrlevel = <10>;
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qcom,speed-bin = <0xf2>;
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/* Turbo_L2 */
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@@ -312,7 +326,7 @@
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <1050000000>;
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qcom,gpu-freq = <1100000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq = <11>;
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@@ -322,35 +336,48 @@
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qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
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};
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/* Turbo */
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/* Turbo_L0 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <1050000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L0>;
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qcom,bus-freq = <11>;
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qcom,bus-min = <11>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO_L0>;
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};
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/* Turbo */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <937000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <9>;
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qcom,bus-max = <10>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_TURBO>;
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};
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/* Nom_L1 */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <873000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq = <9>;
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qcom,bus-freq = <10>;
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qcom,bus-min = <7>;
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qcom,bus-max = <9>;
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qcom,bus-max = <11>;
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qcom,acd-level = <ACD_LEVEL_NOM_L1>;
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};
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/* Nom */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <763000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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@@ -362,8 +389,8 @@
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <688000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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@@ -375,8 +402,8 @@
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <644000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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@@ -388,12 +415,12 @@
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};
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/* SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <510000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq = <4>;
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qcom,bus-freq = <6>;
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qcom,bus-min = <2>;
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qcom,bus-max = <6>;
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@@ -401,8 +428,8 @@
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-freq = <362000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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@@ -414,8 +441,8 @@
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@9 {
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reg = <9>;
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qcom,gpu-pwrlevel@10 {
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reg = <10>;
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qcom,gpu-freq = <264000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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