From 73969c3c5f7f48bb2a0b3f81e888686f1676edd9 Mon Sep 17 00:00:00 2001
From: Melody Olvera <quic_molvera@quicinc.com>
Date: Wed, 3 May 2023 16:23:56 -0700
Subject: [PATCH] dt-bindings: arm: msm: Add bindings for qcom watchdogs

Add snapshot of bindings for qcom waatchdogs from qcom-6.1
commit 9dd5d1fa1 ("Merge "ARM: dts: msm: Add phandle for default CMA
area"").

Change-Id: I80da4682d786147f81fff34b84bb5c6a9c47f445
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 bindings/arm/msm/qcom,gh-watchdog.yaml  | 47 +++++++++++++++++++
 bindings/arm/msm/qcom,msm-watchdog.yaml | 60 +++++++++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 bindings/arm/msm/qcom,gh-watchdog.yaml
 create mode 100644 bindings/arm/msm/qcom,msm-watchdog.yaml

diff --git a/bindings/arm/msm/qcom,gh-watchdog.yaml b/bindings/arm/msm/qcom,gh-watchdog.yaml
new file mode 100644
index 00000000..07203f2c
--- /dev/null
+++ b/bindings/arm/msm/qcom,gh-watchdog.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/msm/gh_watchdog.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. GH Watchdog
+
+maintainers:
+  - Melody Olvera <quic_molvera@quicinc.com>
+
+description: |+
+  Watchdog timer is configured with a bark and a bite time.
+  If the watchdog is not "pet" at regular intervals, the system
+  is assumed to have become non responsive and needs to be reset.
+  A warning in the form of a bark timeout leads to a bark interrupt
+  and a kernel panic. If the watchdog timer is still not reset,
+  a bite timeout occurs, which leads to a reset of the VM via
+  the hypervisor. The driver needs the petting time, and the bark
+  timeout to be programmed into the watchdog, as well as the bark irq.
+
+  The device tree parameters for the watchdog are:
+
+properties:
+  compatible:
+    enum:
+      - qcom,gh-watchdog
+      - qcom,hh-watchdog
+
+  interrupts:
+    maxItems: 1
+    description: |
+      should contain the bark irq number
+
+required:
+  - compatible
+  - interrupts
+
+additionalProperties: false
+
+example:
+  - |
+    wdog_gh: qcom,wdt_gh {
+		    compatible = "qcom,gh-watchdog";
+		    interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+	    };
+...
diff --git a/bindings/arm/msm/qcom,msm-watchdog.yaml b/bindings/arm/msm/qcom,msm-watchdog.yaml
new file mode 100644
index 00000000..41df92f8
--- /dev/null
+++ b/bindings/arm/msm/qcom,msm-watchdog.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/bindings/arm/msm/qcom,msm-watchdog.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Technologies, Inc. MSM Watchdog
+
+maintainers:
+  - Prakruthi Deepak Heragu <quic_pheragu@quicinc.com>
+
+description: |+
+  Watchdog timer is configured with a bark and a bite time.
+  If the watchdog is not "pet" at regular intervals, the system
+  is assumed to have become non responsive and needs to be reset.
+  A warning in the form of a bark timeout leads to a bark interrupt
+  and a kernel panic. If the watchdog timer is still not reset,
+  a bite timeout occurs, which is an interrupt in the secure mode,
+  which leads to a reset of the SOC via the secure watchdog. The
+  driver needs the petting time, and the bark timeout to be programmed
+  into the watchdog, as well as the bark and bite irqs.
+
+  The device tree parameters for the watchdog are:
+
+properties:
+  compatible:
+    items:
+      - const: qcom,msm-watchdog
+
+  reg:
+    minItems: 1
+
+  reg-names:
+    items:
+      - const: wdt-base
+      - const: wdt-absent-base
+    minItems: 1
+
+  interrupts:
+    minItems: 2
+    maxItems: 2
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+
+additionalProperites: false
+
+example:
+  - |
+    wdog: qcom,wdt@17c10000{
+	compatible = "qcom,msm-watchdog";
+	reg = <0x17c10000 0x1000>;
+	reg-names = "wdt-base";
+	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                <0 1 IRQ_TYPE_LEVEL_HIGH>;
+    };
+...