Merge remote-tracking branch 'quic/display-kernel-dev.lnx.1.0' into display-kernel.lnx.11.0

CRs              SHA_ID     Commit Message
----------------------------------------------------------------------
3719188           I115682ff ARM: dts: msm: mm-drivers: Replace txt with yaml
3726524           Ib562686b ARM: dts: msm: add supported platform variants for sun target
3723552           If20659b1 ARM: dts: msm: mm-drivers: support cache coherence with shared memory

CRs-Included: 3723552,3719188,3726524 .

Change-Id: I5c685f0a94132a02098f372119ce4a9b155351d1
Signed-off-by: Linux Display <lnxdisplay@localhost>

Kbuild

@@ -13,7 +13,14 @@ ifeq ($(CONFIG_ARCH_SUN), y)
 		sun-mm-qrd-sku1-overlay.dtbo \
 		sun-mm-qrd-sku1-v8-overlay.dtbo \
 		sun-mm-qrd-sku2-v8-overlay.dtbo \
-		sun-mm-rumi-overlay.dtbo
+		sun-mm-rumi-overlay.dtbo \
+		sun-mm-rcm-overlay.dtbo \
+		sun-mm-atp-overlay.dtbo \
+		sun-mm-cdp-ganges-nodisplay-overlay.dtbo \
+		sun-mm-mtp-3-5mm-overlay.dtbo \
+		sun-mm-rcm-kiwi-overlay.dtbo \
+		sun-mm-rcm-kiwi-v8-overlay.dtbo \
+		sun-mm-rcm-v8-overlay.dtbo
 endif
 
 always-y    := $(dtb-y) $(dtbo-y)

bindings/hw-fence.txt

@@ -1,125 +0,0 @@
-Qualcomm Technologies, Inc. HW FENCE
-
-HW Fence implements Linux APIs to initialize, deinitialize, register-for-signal, and
-overall manage the hw-fences, for hw-to-hw communcation between hw cores.
-
-Required properties
-- compatible: Must be "qcom,msm-hw-fence".
-- qcom,ipcc-reg: Registers ranges for ipcc registers.
-- qcom,hw-fence-table-entries: A u32 indicating number of entries for the hw-fence table
-- qcom,hw-fence-queue-entries: A u32 indicating default number of entries for the Queues
-- hw_fence@1: Carved-out memory-mapping region, to be used for mapping of global tables and queues
-	     used by the hw-fence driver and fence controller running either in secondary vm or
-	     on SOCCP.
-Required properties on targets without SOCCP:
-- hw_fence@0: Doorbell configuration to communicate with secondary vm through hypervisor.
-Required properties on targets with SOCCP:
-- soccp_controller: Phandle for the soccp controller.
-- interrupts: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP).
-- interrupt-controller: Mark the device node as an interrupt controller.
-- #interrupt-cells: Should be one. The first cell is interrupt number.
-- iommus: Specifies the SID's used by this context bank.
-
-Optional properties:
-- qcom,hw-fence-ipc-ver: A u32 indicating ipc version. If not provided in device-tree, this is read
-                       from the registers.
-- qcom,hw-fence-client-type-[name]: A list of four u32 indicating <clients_num, queues_num,
-				  queue_entries, skip_txq_wr_idx>, where [name] specifies the client
-				  type these properties apply to. If provided, all four u32 values
-				  must be provided, and these override default values specified by
-				  the driver for some clients (e.g. dpu, gpu).
-				  -- clients_num: number of clients for given client type
-				  -- queues_num: 1 queue (TxQ) or 2 queues (RxQ and TxQ)
-				  -- queue_entries: number of entries per client queue
-				  -- skip_txq_wr_idx: bool indicating whether tx queue wr_idx update
-						    is skipped within hw fence driver and
-						    hfi_header->tx_wm is used instead
-- qcom,hw-fence-client-type-[name]-extra: A list of four u32 indicating extra client queue
-                                        properties: <start_padding, end_padding, txq_idx_start,
-					txq_idx_by_payload>. Later u32 values do not need to be
-					provided to provide values for earlier u32 values.
-				        -- start_padding: size of padding between queue table header
-					                and first queue header in bytes
-				        -- end_padding: size of padding between queue header(s) and
-						      first queue payload in bytes
-					-- txq_idx_start: start_index for TxQ rd_wr_index
-					-- txq_idx_by_payload: bool indicating whether TxQ rd_wr_idx
-							     indexes by payloads instead of default
-							     dwords
-
-Example for target with SOCCP:
-	msm_hw_fence: qcom,hw-fence {
-		compatible = "qcom,msm-hw-fence";
-		status = "ok";
-
-		/* SOCCP properties */
-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		iommus = <&apps_smmu 0x562 0x1>;
-		soccp_controller = <&soccp_pas>;
-
-		qcom,ipcc-reg = <0x400000 0x100000>;
-		qcom,hw-fence-table-entries = <8192>;
-		qcom,hw-fence-queue-entries = <800>;
-
-		/* time register */
-		qcom,qtime-reg = <0xC221000 0x1000>;
-
-		/* ipc version */
-		qcom,hw-fence-ipc-ver = <0x20003>;
-
-		/* base client queue properties */
-		qcom,hw-fence-client-type-dpu = <4 2 128 0>;
-		qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
-
-		/* extra client queue properties */
-		qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
-
-		/* haven io-mem specific */
-		hw_fence@1 {
-			compatible = "qcom,msm-hw-fence-mem";
-			qcom,master;
-			shared-buffer = <&hwfence_shbuf>;
-		};
-	};
-
-Example for target without SOCCP:
-	msm_hw_fence: qcom,hw-fence {
-		compatible = "qcom,msm-hw-fence";
-		status = "ok";
-
-		qcom,ipcc-reg = <0x400000 0x100000>;
-		qcom,hw-fence-table-entries = <8192>;
-		qcom,hw-fence-queue-entries = <800>;
-
-		/* time register */
-		qcom,qtime-reg = <0xC221000 0x1000>;
-
-		/* ipc version */
-		qcom,hw-fence-ipc-ver = <0x20003>;
-
-		/* base client queue properties */
-		qcom,hw-fence-client-type-dpu = <4 2 128 0>;
-		qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
-
-		/* extra client queue properties */
-		qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
-
-		/* haven doorbell specific */
-		hw_fence@0 {
-			compatible = "qcom,msm-hw-fence-db";
-			qcom,master;
-			gunyah-label = <6>;
-			peer-name = <3>;
-		};
-
-		/* haven io-mem specific */
-		hw_fence@1 {
-			compatible = "qcom,msm-hw-fence-mem";
-			qcom,master;
-			gunyah-label = <5>;
-			peer-name = <3>;
-			shared-buffer = <&hwfence_shbuf>;
-		};
-	};

bindings/hw-fence.yaml

@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hw-fence.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HW Fence
+
+maintainers:
+  - Grace An <quic_gracan@quicinc.com>
+  - Kalyan Thota <quic_kalyant@quicinc.com>
+
+description: |
+  HW Fence implements Linux APIs to initialize, deinitialize, register-for-signal, and
+  overall manage the hw-fences, for hw-to-hw communcation between hw cores.
+
+properties:
+  compatible:
+    const: qcom,msm-hw-fence
+
+  qcom,ipcc-reg:
+    description: Registers ranges for ipcc registers.
+
+  qcom,hw-fence-table-entries:
+    description: A u32 indicating number of entries for the hw-fence table
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,hw-fence-queue-entries:
+    description: A u32 indicating default number of entries for the Queues
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  hw_fence@0:
+    description: Doorbell configuration to communicate with secondary vm through hypervisor.
+    type: object
+    properties:
+      compatible:
+        const: qcom,msm-hw-fence-db
+      qcom,master: true
+      gunyah-label:
+        $ref: /schemas/types.yaml#/definitions/uint32
+      peer-name:
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+  hw_fence@1:
+    description: |
+      Carved-out memory-mapping region, to be used for mapping of global tables and
+      queues used by the hw-fence driver and fence controller running in secondary vm.
+    type: object
+    properties:
+      compatible:
+        const: qcom,msm-hw-fence-mem
+      qcom,master: true
+      gunyah-label:
+        $ref: /schemas/types.yaml#/definitions/uint32
+      peer-name:
+        $ref: /schemas/types.yaml#/definitions/uint32
+      shared-buffer:
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+  qcom,hw-fence-ipc-ver:
+    description: |
+      A u32 indicating ipc version. If not provided in device-tree, this is read from
+      the registers.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  soccp_controller:
+    description: phandle for the soccp controller.
+    $ref: /schemas/types.yaml#/definitions/phandle
+
+  interrupts:
+    description: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP).
+
+  interrupt-controller: true
+    description: Mark the device node as an interrupt controller.
+
+  '#interrupt-cells':
+    description: Should be one. The first cell is interrupt number.
+    const: 1
+
+  iommus:
+    description: Specifies the SID's used by this context bank.
+
+patternProperties:
+  "qcom,hw\-fence\-client\-type\-+\w":
+    description: |
+      A list of four u32 describing client properties that
+      override default values specified by the driver for some clients.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+    - description: number of clients for given type
+    - enum:
+      - 1
+      - 2
+      description: 1 (Tx) or 2 (Rx and Tx)
+    - description: number of entries per client queue
+    - enum:
+      - 0
+      - 1
+      description: |
+        bool indicating whether tx queue wr_idx update is skipped within hw fence
+        driver and hfi_header->tx_wm is used instead
+
+  "qcom,hw\-fence\-client\-type\-+\w+\-extra":
+    description: |
+      A list of four u32 indicating extra client queue properties.Later u32 values do not need to
+      be provided to provide values for earlier u32 values.
+    minItems: 1
+    maxItems: 4
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    items:
+    - description: size of padding between queue table header and first queue header in bytes
+    - description: size of padding between queue header(s) and first queue payload in bytes
+    - description: start_index for TxQ rd_wr_index
+    - enum:
+      - 0
+      - 1
+      description: |
+        bool indicating whether TxQ rd_wr_idx indexes by payloads instead of
+        default dwords
+
+required:
+  - compatible
+  - qcom,ipcc-reg
+  - qcom,hw-fence-table-entries
+  - qcom,hw-fence-queue-entries
+  - hw_fence@1
+
+if:
+  required:
+    - soccp-controller
+then:
+  required:
+    - interrupts
+    - interrupt-controller
+    - '#interrupt-cells'
+    - iommus
+    properties:
+      hw_fence@0: false
+else:
+  required:
+    - hw_fence@0
+  properties:
+    - interrupts: false
+    - interrupt-controller: false
+    - '#interrupt-cells': false
+    - iommus: false
+
+additionalProperties: false
+
+examples:
+  - |
+    msm_hw_fence: qcom,hw-fence {
+       compatible = "qcom,msm-hw-fence";
+       status = "ok";
+
+       qcom,ipcc-reg = <0x400000 0x100000>;
+       qcom,hw-fence-table-entries = <8192>;
+       qcom,hw-fence-queue-entries = <800>;
+
+       # time register
+       qcom,qtime-reg = <0xC221000 0x1000>;
+
+       # ipc version
+       qcom,hw-fence-ipc-ver = <0x20003>;
+
+       # client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx
+       qcom,hw-fence-client-type-dpu = <4 2 128 0>;
+       qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
+
+       # extra client queue properties
+       qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
+
+       # haven doorbell specific
+       hw_fence@0 {
+         compatible = "qcom,msm-hw-fence-db";
+         qcom,master;
+         gunyah-label = <6>;
+         peer-name = <3>;
+       };
+
+       # haven io-mem specific
+       hw_fence@1 {
+         compatible = "qcom,msm-hw-fence-mem";
+         qcom,master;
+         gunyah-label = <5>;
+         peer-name = <3>;
+         shared-buffer = <&hwfence_shbuf>;
+       };
+    };
+
+  - |
+    msm_hw_fence: qcom,hw-fence {
+      compatible = "qcom,msm-hw-fence";
+      status = "ok";
+
+      # SOCCP properties
+      interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-controller;
+      #interrupt-cells = <1>;
+      iommus = <&apps_smmu 0x562 0x1>;
+      soccp_controller = <&soccp_pas>;
+
+      qcom,ipcc-reg = <0x400000 0x100000>;
+      qcom,hw-fence-table-entries = <8192>;
+      qcom,hw-fence-queue-entries = <800>;
+
+      # time register
+      qcom,qtime-reg = <0xC221000 0x1000>;
+
+      # ipc version
+      qcom,hw-fence-ipc-ver = <0x20003>;
+
+      # base client queue properties
+      qcom,hw-fence-client-type-dpu = <4 2 128 0>;
+      qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
+
+      # extra client queue properties
+      qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
+
+      # haven io-mem specific
+      hw_fence@1 {
+        compatible = "qcom,msm-hw-fence-mem";
+        qcom,master;
+        shared-buffer = <&hwfence_shbuf>;
+      };
+    };
+...

hw_fence/sun-hw-fence.dtsi

@@ -15,6 +15,7 @@
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		iommus = <&apps_smmu 0x562 0x1>;
+		dma-coherent;
 		soccp_controller = <&soccp_pas>;
 
 		qcom,hw-fence-table-entries = <8192>;

sun-mm-atp-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun ATP";
+	compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x10021 0>;
+};

sun-mm-cdp-ganges-nodisplay-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP No Display";
+	compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x30001 0>;
+};

sun-mm-mtp-3-5mm-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x60008 0>;
+};

sun-mm-rcm-kiwi-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x40015 0>;
+};

sun-mm-rcm-kiwi-v8-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x20015 0>;
+};

sun-mm-rcm-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RCM";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x15 0>;
+};

sun-mm-rcm-v8-overlay.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "hw_fence/sun-hw-fence.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>;
+	qcom,board-id = <0x30015 0>;
+};